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eddr3
Commit 0bd9ef33 authored by Andrey Filippov's avatar Andrey Filippov
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change DM* I/O standard to SSTL15

parent 37d1bee7
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.project
View file @ 0bd9ef33
...@@ -46,77 +46,77 @@ ...@@ -46,77 +46,77 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140515155524262.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140531004107237.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140522174846453.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140531003924649.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140515155524262.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140531004107237.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140522174846453.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140531003924649.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140522174846453.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140531003924649.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140515155524262.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140531004107237.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140522174846453.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140531003924649.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140515155524262.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140531004107237.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140522174846453.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140531003924649.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140515155524262.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140531004107237.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140522174846453.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140531003924649.log</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-opt-phys.dcp</name> <name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140515155524262.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140531004107237.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-place.dcp</name> <name>vivado_state/eddr3-place.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140522174846453.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140531003924649.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-route.dcp</name> <name>vivado_state/eddr3-route.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140515155524262.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140531004107237.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-synth.dcp</name> <name>vivado_state/eddr3-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140522174846453.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140531003924649.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ddrc_test01.v
View file @ 0bd9ef33
...@@ -255,19 +255,20 @@ always @ (posedge axi_rst or posedge axi_aclk) begin ...@@ -255,19 +255,20 @@ always @ (posedge axi_rst or posedge axi_aclk) begin
if (axi_rst) select_status <= 1'b0; if (axi_rst) select_status <= 1'b0;
else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0); else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
end end
/*
// Clock and reset from PS // Clock and reset from PS
reg frst_inv; reg frst_inv;
always @ (negedge frst[0] or posedge axi_aclk) begin always @ (negedge frst[0] or posedge axi_aclk) begin
if (!frst[0]) frst_inv <= 1'b1; if (!frst[0]) frst_inv <= 1'b1;
else frst_inv <= 1'b0; else frst_inv <= 1'b0;
end end
*/
/*
`ifndef IVERILOG `ifndef IVERILOG
(* dont_touch = "true" *) (* dont_touch = "true" *)
`endif `endif
wire frst_inv= ~frst[0]; wire frst_inv= ~frst[0];
*/
//BUFG bufg_axi_rst_i (.O(axi_rst),.I(~frst[0])); //BUFG bufg_axi_rst_i (.O(axi_rst),.I(~frst[0]));
BUFG bufg_axi_rst_i (.O(axi_rst),.I(frst_inv)); BUFG bufg_axi_rst_i (.O(axi_rst),.I(frst_inv));
......
ddrc_test01.xdc
View file @ 0bd9ef33
...@@ -194,11 +194,13 @@ set_property PACKAGE_PIN G7 [get_ports {NDQSU}] ...@@ -194,11 +194,13 @@ set_property PACKAGE_PIN G7 [get_ports {NDQSU}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSU}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSU}]
# inout SDDML, // LDM I/O pad (actually only output) # inout SDDML, // LDM I/O pad (actually only output)
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDML}] #set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDML}]
set_property IOSTANDARD SSTL15 [get_ports {SDDML}]
set_property PACKAGE_PIN L5 [get_ports {SDDML}] set_property PACKAGE_PIN L5 [get_ports {SDDML}]
# inout SDDMU, // UDM I/O pad (actually only output) # inout SDDMU, // UDM I/O pad (actually only output)
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDMU}] #set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDMU}]
set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}] set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
......
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