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eddr3

ddr3 subproject for Elphel 393 camera

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eddr3

ddr3 subproject for Elphel 393 camera

This subproject is started to create a DDR3 memory controller for Elphel camera that does not depend on any non-documented features of Xilinx Zynq and can be simulated by Free Software tools (Icarus Verilog + GTKWave) without use of any encrypted modules. Everything in plain Verilog and constraints.

Detailed description of the project is available in the blog post: http://blog.elphel.com/2014/06/ddr3-memory-interface-on-xilinx-zynq-soc-free-software-compatible/