added pause bit to make sequneces more compact, implemented ddr3 read block test (37d1bee7) · Commits · Elphel / eddr3

ddrc_control.v

+59 −41

Original line number	Diff line number	Diff line
		@@ -22,33 +22,11 @@

		module ddrc_control #(
		parameter AXI_WR_ADDR_BITS= 12,
		// parameter SELECT_ADDR = 'h800, // address to select this module
		// parameter SELECT_ADDR_MASK = 'h800, // address mask to select this module
		// parameter BUSY_ADDR = 'hc00, // address to generate busy
		// parameter BUSY_ADDR_MASK = 'hc00, // address mask to generate busy

		parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers
		parameter CONTROL_ADDR_MASK = 'h1400, // AXI write address of control registers
		// parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers
		// parameter STATUS_ADDR_MASK = 'h1400, // AXI write address of status registers
		parameter BUSY_WR_ADDR = 'h1800, // AXI write address to generate busy
		parameter BUSY_WR_ADDR_MASK = 'h1c00, // AXI write address mask to generate busy

		// parameter DLY_LD_ADDR = 'h880, // address to generate delay load
		// parameter DLY_LD_ADDR_MASK = 'hb80, // address mask to generate delay load
		// parameter DLY_SET_ADDR = 'h870, // address to generate delay set
		// parameter DLY_SET_ADDR_MASK = 'hbff, // address mask to generate delay set
		// parameter RUN_CHN_ADDR = 'h800, // address to set sequnecer channel and run (4 LSB-s - channel)
		// parameter RUN_CHN_ADDR_MASK = 'hbf0, // address mask to generate sequencer channel/run
		// parameter PATTERNS_ADDR = 'h820, // address to set DQM and DQS patterns (16'h0055)
		// parameter PATTERNS_ADDR_MASK = 'hbff, // address mask to set DQM and DQS patterns
		// parameter PAGES_ADDR = 'h821, // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
		// parameter PAGES_ADDR_MASK = 'hbff, // address mask to set DQM and DQS patterns
		// parameter CMDA_EN_ADDR = 'h822, // address to enable('h823)/disable('h822) command/address outputs
		// parameter CMDA_EN_ADDR_MASK = 'hbfe, // address mask for command/address outputs
		// parameter EXTRA_ADDR = 'h824, // address to set extra parameters (currently just inv_clk_div)
		// parameter EXTRA_ADDR_MASK = 'hbff // address mask for extra parameters

		parameter DLY_LD_REL = 'h080, // address to generate delay load
		parameter DLY_LD_REL_MASK = 'h380, // address mask to generate delay load
		parameter DLY_SET_REL = 'h070, // address to generate delay set
		@@ -57,15 +35,19 @@ module ddrc_control #(
		parameter RUN_CHN_REL_MASK = 'h3f0, // address mask to generate sequencer channel/run
		parameter PATTERNS_REL = 'h020, // address to set DQM and DQS patterns (16'h0055)
		parameter PATTERNS_REL_MASK = 'h3ff, // address mask to set DQM and DQS patterns
		parameter PAGES_REL = 'h021, // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
		parameter PATTERNS_TRI_REL = 'h021, // address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
		parameter PATTERNS_TRI_REL_MASK = 'h3ff, // address mask to set DQM and DQS tristate patterns
		parameter WBUF_DELAY_REL = 'h022, // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
		parameter WBUF_DELAY_REL_MASK = 'h3ff, // address mask to set extra delay
		parameter PAGES_REL = 'h023, // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
		parameter PAGES_REL_MASK = 'h3ff, // address mask to set DQM and DQS patterns
		parameter CMDA_EN_REL = 'h022, // address to enable('h823)/disable('h822) command/address outputs
		parameter CMDA_EN_REL = 'h024, // address to enable('h823)/disable('h822) command/address outputs
		parameter CMDA_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
		parameter SDRST_ACT_REL = 'h024, // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory
		parameter SDRST_ACT_REL = 'h026, // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory
		parameter SDRST_ACT_REL_MASK = 'h3fe, // address mask for reset DDR3
		parameter CKE_EN_REL = 'h026, // address to enable('h827)/disable('h826) CKE signal to memory
		parameter CKE_EN_REL = 'h028, // address to enable('h827)/disable('h826) CKE signal to memory
		parameter CKE_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
		parameter EXTRA_REL = 'h028, // address to set extra parameters (currently just inv_clk_div)
		parameter EXTRA_REL = 'h02a, // address to set extra parameters (currently just inv_clk_div)
		parameter EXTRA_REL_MASK = 'h3ff // address mask for extra parameters
		)(
		input clk,
		@@ -96,6 +78,11 @@ module ddrc_control #(
		output inv_clk_div, // invert clk_div to ISERDES
		output [ 7:0] dqs_pattern, // DQS pattern during write (normally 8'h55)
		output [ 7:0] dqm_pattern, // DQM pattern (just for testing, should be 8'h0)
		output [ 3:0] dq_tri_on_pattern,
		output [ 3:0] dq_tri_off_pattern,
		output [ 3:0] dqs_tri_on_pattern,
		output [ 3:0] dqs_tri_off_pattern,
		output [ 3:0] wbuf_delay,
		// control: buffers pages
		output [ 1:0] port0_page, // port 0 buffer read page (to be controlled by arbiter later, set to 2'b0)
		output [ 1:0] port0_int_page, // port 0 PHY-side write to buffer page (to be controlled by arbiter later, set to 2'b0)
		@@ -103,6 +90,13 @@ module ddrc_control #(
		output [ 1:0] port1_int_page // port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0)

		);
		localparam DQSTRI_FIRST= 4'h3; // DQS tri-state control word, first when enabling output
		localparam DQSTRI_LAST= 4'hc; // DQS tri-state control word, first after disabling output
		localparam DQTRI_FIRST= 4'h7; // DQ tri-state control word, first when enabling output
		localparam DQTRI_LAST= 4'he; // DQ tri-state control word, first after disabling output
		localparam WBUF_DLY_DFLT= 4'h6; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)


		localparam DLY_LD_ADDR = CONTROL_ADDR \| DLY_LD_REL; // address to generate delay load
		localparam DLY_LD_ADDR_MASK = CONTROL_ADDR_MASK \| DLY_LD_REL_MASK; // address mask to generate delay load
		localparam DLY_SET_ADDR = CONTROL_ADDR \| DLY_SET_REL; // address to generate delay set
		@@ -111,6 +105,12 @@ module ddrc_control #(
		localparam RUN_CHN_ADDR_MASK = CONTROL_ADDR_MASK \| RUN_CHN_REL_MASK; // address mask to generate sequencer channel/run
		localparam PATTERNS_ADDR = CONTROL_ADDR \| PATTERNS_REL; // address to set DQM and DQS patterns (16'h0055)
		localparam PATTERNS_ADDR_MASK = CONTROL_ADDR_MASK \| PATTERNS_REL_MASK;// address mask to set DQM and DQS patterns

		localparam PATTERNS_TRI_ADDR = CONTROL_ADDR \| PATTERNS_TRI_REL; //address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
		localparam PATTERNS_TRI_ADDR_MASK = CONTROL_ADDR_MASK \| PATTERNS_TRI_REL_MASK;// address mask to set DQM and DQS tristate patterns
		localparam WBUF_DELAY_ADDR = CONTROL_ADDR \| WBUF_DELAY_REL; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
		localparam WBUF_DELAY_ADDR_MASK = CONTROL_ADDR_MASK \| WBUF_DELAY_REL_MASK; // address mask to set extra delay

		localparam PAGES_ADDR = CONTROL_ADDR \| PAGES_REL; // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
		localparam PAGES_ADDR_MASK = CONTROL_ADDR_MASK \| PAGES_REL_MASK; // address mask to set DQM and DQS patterns
		localparam CMDA_EN_ADDR = CONTROL_ADDR \| CMDA_EN_REL; // address to enable('h823)/disable('h822) command/address outputs
		@@ -151,6 +151,17 @@ module ddrc_control #(

		reg inv_clk_div_r; // invert clk_div to ISERDES

		reg [15:0] dqs_tri_pattern_r;
		reg [ 3:0] wbuf_delay_r;

		assign wbuf_delay= wbuf_delay_r;
		assign {
		dqs_tri_off_pattern[3:0],
		dqs_tri_on_pattern[3:0],
		dq_tri_off_pattern[3:0],
		dq_tri_on_pattern[3:0]
		} = dqs_tri_pattern_r;

		assign ld_delay = dly_ld_r;
		assign dly_set = dly_set_r;
		assign dly_data = wdata_fifo_out_r[ 7:0]; // WARNING: [Synth 8-3936] Found unconnected internal register 'wdata_fifo_out_r_reg' and it is trimmed from '32' to '11' bits. [ddrc_control.v:100]
		@@ -232,6 +243,13 @@ module ddrc_control #(
		else if (fifo_re && (((waddr_fifo_out ^ EXTRA_ADDR) & EXTRA_ADDR_MASK)==0))
		inv_clk_div_r <= wdata_fifo_out[0];

		if (rst) dqs_tri_pattern_r <= {DQSTRI_LAST,DQSTRI_FIRST,DQTRI_LAST,DQTRI_FIRST};
		else if (fifo_re && (((waddr_fifo_out ^ PATTERNS_TRI_ADDR) & PATTERNS_TRI_ADDR_MASK)==0))
		dqs_tri_pattern_r <= wdata_fifo_out[15:0];

		if (rst) wbuf_delay_r <= WBUF_DLY_DFLT;
		else if (fifo_re && (((waddr_fifo_out ^ WBUF_DELAY_ADDR) & WBUF_DELAY_ADDR_MASK)==0))
		wbuf_delay_r <= wdata_fifo_out[3:0];
		end
		always @ (posedge mclk) begin
		waddr_fifo_out_r <= waddr_fifo_out;

ddrc_test01.v

+70 −45

Original line number	Diff line number	Diff line
		@@ -68,15 +68,19 @@ module ddrc_test01 #(
		parameter RUN_CHN_REL_MASK = 'h3f0, // address mask to generate sequencer channel/run
		parameter PATTERNS_REL = 'h020, // address to set DQM and DQS patterns (16'h0055)
		parameter PATTERNS_REL_MASK = 'h3ff, // address mask to set DQM and DQS patterns
		parameter PAGES_REL = 'h021, // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
		parameter PATTERNS_TRI_REL = 'h021, // address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
		parameter PATTERNS_TRI_REL_MASK = 'h3ff, // address mask to set DQM and DQS tristate patterns
		parameter WBUF_DELAY_REL = 'h022, // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
		parameter WBUF_DELAY_REL_MASK = 'h3ff, // address mask to set extra delay
		parameter PAGES_REL = 'h023, // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
		parameter PAGES_REL_MASK = 'h3ff, // address mask to set DQM and DQS patterns
		parameter CMDA_EN_REL = 'h022, // address to enable('h823)/disable('h822) command/address outputs
		parameter CMDA_EN_REL = 'h024, // address to enable('h823)/disable('h822) command/address outputs
		parameter CMDA_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
		parameter SDRST_ACT_REL = 'h024, // address to activate('h825)/deactivate('h824) active-low reset signal to DDR3 memory
		parameter SDRST_ACT_REL = 'h026, // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory
		parameter SDRST_ACT_REL_MASK = 'h3fe, // address mask for reset DDR3
		parameter CKE_EN_REL = 'h026, // address to enable('h827)/disable('h826) CKE signal to memory
		parameter CKE_EN_REL = 'h028, // address to enable('h827)/disable('h826) CKE signal to memory
		parameter CKE_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
		parameter EXTRA_REL = 'h028, // address to set extra parameters (currently just inv_clk_div)
		parameter EXTRA_REL = 'h02a, // address to set extra parameters (currently just inv_clk_div)
		parameter EXTRA_REL_MASK = 'h3ff // address mask for extra parameters
		)(
		// DDR3 interface
		@@ -223,6 +227,13 @@ module ddrc_test01 #(
		wire axiwr_dev_busy;
		wire axird_dev_busy;

		wire [ 3:0] dq_tri_on_pattern;
		wire [ 3:0] dq_tri_off_pattern;
		wire [ 3:0] dqs_tri_on_pattern;
		wire [ 3:0] dqs_tri_off_pattern;
		wire [ 3:0] wbuf_delay;


		// assign en_cmd0_wr= axiwr_bram_wen && (axiwr_bram_waddr[11:10]==2'h1);
		// assign en_port0_rd= axird_bram_ren && (axird_bram_raddr[11:10]==2'h0);
		// assign en_port0_regen= axird_bram_regen && (axird_bram_raddr[11:10]==2'h0);
		@@ -338,6 +349,10 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
		.RUN_CHN_REL_MASK (RUN_CHN_REL_MASK),
		.PATTERNS_REL (PATTERNS_REL),
		.PATTERNS_REL_MASK (PATTERNS_REL_MASK),
		.PATTERNS_TRI_REL (PATTERNS_TRI_REL),
		.PATTERNS_TRI_REL_MASK (PATTERNS_TRI_REL_MASK),
		.WBUF_DELAY_REL (WBUF_DELAY_REL),
		.WBUF_DELAY_REL_MASK (WBUF_DELAY_REL_MASK),
		.PAGES_REL (PAGES_REL),
		.PAGES_REL_MASK (PAGES_REL_MASK),
		.CMDA_EN_REL (CMDA_EN_REL),
		@@ -371,6 +386,11 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
		.inv_clk_div (inv_clk_div), // output
		.dqs_pattern (dqs_pattern[7:0]), // output[7:0]
		.dqm_pattern (dqm_pattern[7:0]), // output[7:0]
		.dq_tri_on_pattern (dq_tri_on_pattern[3:0]), // output[3:0]
		.dq_tri_off_pattern (dq_tri_off_pattern[3:0]), // output[3:0]
		.dqs_tri_on_pattern (dqs_tri_on_pattern[3:0]), // output[3:0]
		.dqs_tri_off_pattern (dqs_tri_off_pattern[3:0]),// output[3:0]
		.wbuf_delay (wbuf_delay[3:0]), // output[3:0]
		.port0_page (port0_page[1:0]), // output[1:0]
		.port0_int_page (port0_int_page[1:0]), // output[1:0]
		.port1_page (port1_page[1:0]), // output[1:0]
		@@ -492,7 +512,12 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
		.ddr_cke (ddr_cke), // input
		.inv_clk_div (inv_clk_div), // input
		.dqs_pattern (dqs_pattern), // input[7:0]
		.dqm_pattern (dqm_pattern) // input[7:0]
		.dqm_pattern (dqm_pattern), // input[7:0]
		.dq_tri_on_pattern (dq_tri_on_pattern[3:0]), // input[3:0]
		.dq_tri_off_pattern (dq_tri_off_pattern[3:0]), // input[3:0]
		.dqs_tri_on_pattern (dqs_tri_on_pattern[3:0]), // input[3:0]
		.dqs_tri_off_pattern (dqs_tri_off_pattern[3:0]),// input[3:0]
		.wbuf_delay (wbuf_delay[3:0]) // input[3:0]
		);

ddrc_test01_testbench.sav

+441 −14

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ddrc_test01_testbench.tf

+371 −111

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phy/ddrc_sequencer.v

+35 −10

Original line number	Diff line number	Diff line
		@@ -43,8 +43,8 @@ module ddrc_sequencer #(
		parameter SS_EN = "FALSE",
		parameter SS_MODE = "CENTER_HIGH",
		parameter SS_MOD_PERIOD = 10000,
		parameter CMD_PAUSE_BITS= 6,
		parameter CMD_DONE_BIT= 6
		parameter CMD_PAUSE_BITS= 10,
		parameter CMD_DONE_BIT= 10
		)(
		// DDR3 interface
		output SDRST, // DDR3 reset (active low)
		@@ -114,8 +114,12 @@ module ddrc_sequencer #(
		input ddr_cke, // DDR clock enable , XOR-ed with command bit
		input inv_clk_div,
		input [7:0] dqs_pattern, // 8'h55
		input [7:0] dqm_pattern // 8'h00

		input [7:0] dqm_pattern, // 8'h00
		input [ 3:0] dq_tri_on_pattern, // DQ tri-state control word, first when enabling output
		input [ 3:0] dq_tri_off_pattern, // DQ tri-state control word, first after disabling output
		input [ 3:0] dqs_tri_on_pattern, // DQS tri-state control word, first when enabling output
		input [ 3:0] dqs_tri_off_pattern,// DQS tri-state control word, first after disabling output
		input [ 3:0] wbuf_delay
		);
		localparam ADDRESS_NUMBER = 15;

		@@ -131,7 +135,8 @@ module ddrc_sequencer #(
		reg [63:0] buf_wdata_negedge; // output[63:0]
		wire [63:0] buf_rdata; // multiplexed input from one of the write channels buffer
		wire [63:0] buf1_rdata;
		wire buf_wr; // output
		wire buf_wr; // delayed by specified number of clock cycles
		wire buf_wr_ndly; // before dealy
		wire buf_rd; // read next 64 bytes from the buffer, need one extra pre-read

		wire rst=rst_in;
		@@ -141,6 +146,8 @@ module ddrc_sequencer #(
		reg cmd_sel;
		reg [ 2:0] cmd_busy; // bit 0 - immediately,
		wire phy_cmd_nop; // decoded command (ras, cas, we) was NOP
		wire phy_cmd_add_pause; // decoded from the command word - add one pause command after the current one
		reg add_pause; // previos command had phy_cmd_add_pause set
		wire sequence_done;
		wire [CMD_PAUSE_BITS-1:0] pause_len;
		reg cmd_fetch; // previous cycle command was read from the command memory, current: command valid
		@@ -155,7 +162,7 @@ module ddrc_sequencer #(

		assign run_done=sequence_done;
		assign run_busy=cmd_busy[0]; //earliest
		assign pause=cmd_fetch? (phy_cmd_nop && (pause_len != 0)): (cmd_busy[2] && (pause_cntr[CMD_PAUSE_BITS-1:1]!=0));
		assign pause=cmd_fetch? (phy_cmd_add_pause \|\| (phy_cmd_nop && (pause_len != 0))): (cmd_busy[2] && (pause_cntr[CMD_PAUSE_BITS-1:1]!=0));
		/// debugging
		assign phy_cmd_word = cmd_sel?phy_cmd1_word:phy_cmd0_word; // TODO: hangs even with 0-s in phy_cmd
		/// assign phy_cmd_word = phy_cmd_word?0:0;
		@@ -175,6 +182,10 @@ module ddrc_sequencer #(
		// Fetch - command data valid
		if (rst) cmd_fetch <= 0;
		else cmd_fetch <= cmd_busy[0] && !pause;

		if (rst) add_pause <= 0;
		else add_pause <= cmd_fetch && phy_cmd_add_pause;

		// Command read address
		if (rst) cmd_addr <= 0;
		else if (run_seq) cmd_addr <= run_addr[9:0];
		@@ -358,19 +369,33 @@ module ddrc_sequencer #(
		// .phy_cmd_word (32'h0), //phy_cmd_word[31:0]), // input[31:0]
		.phy_cmd_word (phy_cmd_word[31:0]), // input[31:0]
		.phy_cmd_nop (phy_cmd_nop), // output
		.phy_cmd_add_pause (phy_cmd_add_pause), // one pause cycle (for 8-bursts)
		.add_pause (add_pause),
		.pause_len (pause_len), // output [CMD_PAUSE_BITS-1:0]
		.sequence_done (sequence_done), // output
		// .buf_addr (buf_addr[6:0]), // output[6:0]
		.buf_wdata (buf_wdata[63:0]), // output[63:0]
		.buf_rdata (buf_rdata[63:0]), // input[63:0]
		.buf_wr (buf_wr), // output
		.buf_wr (buf_wr_ndly), // output
		.buf_rd (buf_rd), // output
		.cmda_en (cmda_en), // input
		.ddr_rst (ddr_rst), // input ***************
		.ddr_cke (ddr_cke), // input ***************
		.ddr_rst (ddr_rst), // input
		.ddr_cke (ddr_cke), // input
		.inv_clk_div (inv_clk_div), // input
		.dqs_pattern (dqs_pattern), // input[7:0]
		.dqm_pattern (dqm_pattern) // input[7:0]
		.dqm_pattern (dqm_pattern), // input[7:0]
		.dq_tri_on_pattern (dq_tri_on_pattern[3:0]), // input[3:0]
		.dq_tri_off_pattern (dq_tri_off_pattern[3:0]), // input[3:0]
		.dqs_tri_on_pattern (dqs_tri_on_pattern[3:0]), // input[3:0]
		.dqs_tri_off_pattern (dqs_tri_off_pattern[3:0]) // input[3:0]
		);
		// delay buf_wr by 1-16 cycles to compensate for DDR and HDL code latency (~7 cycles?)
		dly01_16 buf_wr_dly_i (
		.clk(mclk), // input
		.rst(1'b0), // input
		.dly(wbuf_delay[3:0]), // input[3:0]
		.din(buf_wr_ndly), // input
		.dout(buf_wr) // output reg
		);

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