Commit e4816b14 authored by Alexey Grebenkin's avatar Alexey Grebenkin

Few more changes to make the project synth in vdt enviroment

parent ec00bd28
/home/alexey/tmp/sata2/x393/ddr3/1024Mb_ddr3_parameters.vh
\ No newline at end of file
/home/alexey/tmp/sata2/x393/ddr3/2048Mb_ddr3_parameters.vh
\ No newline at end of file
/home/alexey/tmp/sata2/x393/ddr3/4096Mb_ddr3_parameters.vh
\ No newline at end of file
......@@ -84,7 +84,7 @@
output wire [3:0] afi_awcache,
output wire [2:0] afi_awprot,
output wire [3:0] afi_awlen,
output wire [2:0] afi_awsize,
output wire [1:0] afi_awsize,
output wire [1:0] afi_awburst,
output wire [3:0] afi_awqos,
// write data
......@@ -113,7 +113,7 @@
output wire [3:0] afi_arcache,
output wire [2:0] afi_arprot,
output wire [3:0] afi_arlen,
output wire [2:0] afi_arsize,
output wire [1:0] afi_arsize,
output wire [1:0] afi_arburst,
output wire [3:0] afi_arqos,
// read data
......
......@@ -90,7 +90,7 @@ wire [ 1:0] afi0_awlock; // output[1:0]
wire [ 3:0] afi0_awcache; // output[3:0]
wire [ 2:0] afi0_awprot; // output[2:0]
wire [ 3:0] afi0_awlen; // output[3:0]
wire [ 2:0] afi0_awsize; // output[2:0]
wire [ 1:0] afi0_awsize; // output[2:0]
wire [ 1:0] afi0_awburst; // output[1:0]
wire [ 3:0] afi0_awqos; // output[3:0]
wire [63:0] afi0_wdata; // output[63:0]
......@@ -114,7 +114,7 @@ wire [ 1:0] afi0_arlock; // output[1:0]
wire [ 3:0] afi0_arcache; // output[3:0]
wire [ 2:0] afi0_arprot; // output[2:0]
wire [ 3:0] afi0_arlen; // output[3:0]
wire [ 2:0] afi0_arsize; // output[2:0]
wire [ 1:0] afi0_arsize; // output[2:0]
wire [ 1:0] afi0_arburst; // output[1:0]
wire [ 3:0] afi0_arqos; // output[3:0]
wire [63:0] afi0_rdata; // input[63:0]
......
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This diff is collapsed.
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, .INIT_0F (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000
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, .INITP_05 (INITP_05)
, .INITP_06 (INITP_06)
, .INITP_07 (INITP_07)
, .INIT_00 (INIT_00)
, .INIT_01 (INIT_01)
, .INIT_02 (INIT_02)
, .INIT_03 (INIT_03)
, .INIT_04 (INIT_04)
, .INIT_05 (INIT_05)
, .INIT_06 (INIT_06)
, .INIT_07 (INIT_07)
, .INIT_08 (INIT_08)
, .INIT_09 (INIT_09)
, .INIT_0A (INIT_0A)
, .INIT_0B (INIT_0B)
, .INIT_0C (INIT_0C)
, .INIT_0D (INIT_0D)
, .INIT_0E (INIT_0E)
, .INIT_0F (INIT_0F)
, .INIT_10 (INIT_10)
, .INIT_11 (INIT_11)
, .INIT_12 (INIT_12)
, .INIT_13 (INIT_13)
, .INIT_14 (INIT_14)
, .INIT_15 (INIT_15)
, .INIT_16 (INIT_16)
, .INIT_17 (INIT_17)
, .INIT_18 (INIT_18)
, .INIT_19 (INIT_19)
, .INIT_1A (INIT_1A)
, .INIT_1B (INIT_1B)
, .INIT_1C (INIT_1C)
, .INIT_1D (INIT_1D)
, .INIT_1E (INIT_1E)
, .INIT_1F (INIT_1F)
, .INIT_20 (INIT_20)
, .INIT_21 (INIT_21)
, .INIT_22 (INIT_22)
, .INIT_23 (INIT_23)
, .INIT_24 (INIT_24)
, .INIT_25 (INIT_25)
, .INIT_26 (INIT_26)
, .INIT_27 (INIT_27)
, .INIT_28 (INIT_28)
, .INIT_29 (INIT_29)
, .INIT_2A (INIT_2A)
, .INIT_2B (INIT_2B)
, .INIT_2C (INIT_2C)
, .INIT_2D (INIT_2D)
, .INIT_2E (INIT_2E)
, .INIT_2F (INIT_2F)
, .INIT_30 (INIT_30)
, .INIT_31 (INIT_31)
, .INIT_32 (INIT_32)
, .INIT_33 (INIT_33)
, .INIT_34 (INIT_34)
, .INIT_35 (INIT_35)
, .INIT_36 (INIT_36)
, .INIT_37 (INIT_37)
, .INIT_38 (INIT_38)
, .INIT_39 (INIT_39)
, .INIT_3A (INIT_3A)
, .INIT_3B (INIT_3B)
, .INIT_3C (INIT_3C)
, .INIT_3D (INIT_3D)
, .INIT_3E (INIT_3E)
, .INIT_3F (INIT_3F)
This diff is collapsed.
, .INITP_00 (INITP_00)
, .INITP_01 (INITP_01)
, .INITP_02 (INITP_02)
, .INITP_03 (INITP_03)
, .INITP_04 (INITP_04)
, .INITP_05 (INITP_05)
, .INITP_06 (INITP_06)
, .INITP_07 (INITP_07)
, .INITP_08 (INITP_08)
, .INITP_09 (INITP_09)
, .INITP_0A (INITP_0A)
, .INITP_0B (INITP_0B)
, .INITP_0C (INITP_0C)
, .INITP_0D (INITP_0D)
, .INITP_0E (INITP_0E)
, .INITP_0F (INITP_0F)
, .INIT_00 (INIT_00)
, .INIT_01 (INIT_01)
, .INIT_02 (INIT_02)
, .INIT_03 (INIT_03)
, .INIT_04 (INIT_04)
, .INIT_05 (INIT_05)
, .INIT_06 (INIT_06)
, .INIT_07 (INIT_07)
, .INIT_08 (INIT_08)
, .INIT_09 (INIT_09)
, .INIT_0A (INIT_0A)
, .INIT_0B (INIT_0B)
, .INIT_0C (INIT_0C)
, .INIT_0D (INIT_0D)
, .INIT_0E (INIT_0E)
, .INIT_0F (INIT_0F)
, .INIT_10 (INIT_10)
, .INIT_11 (INIT_11)
, .INIT_12 (INIT_12)
, .INIT_13 (INIT_13)
, .INIT_14 (INIT_14)
, .INIT_15 (INIT_15)
, .INIT_16 (INIT_16)
, .INIT_17 (INIT_17)
, .INIT_18 (INIT_18)
, .INIT_19 (INIT_19)
, .INIT_1A (INIT_1A)
, .INIT_1B (INIT_1B)
, .INIT_1C (INIT_1C)
, .INIT_1D (INIT_1D)
, .INIT_1E (INIT_1E)
, .INIT_1F (INIT_1F)
, .INIT_20 (INIT_20)
, .INIT_21 (INIT_21)
, .INIT_22 (INIT_22)
, .INIT_23 (INIT_23)
, .INIT_24 (INIT_24)
, .INIT_25 (INIT_25)
, .INIT_26 (INIT_26)
, .INIT_27 (INIT_27)
, .INIT_28 (INIT_28)
, .INIT_29 (INIT_29)
, .INIT_2A (INIT_2A)
, .INIT_2B (INIT_2B)
, .INIT_2C (INIT_2C)
, .INIT_2D (INIT_2D)
, .INIT_2E (INIT_2E)
, .INIT_2F (INIT_2F)
, .INIT_30 (INIT_30)
, .INIT_31 (INIT_31)
, .INIT_32 (INIT_32)
, .INIT_33 (INIT_33)
, .INIT_34 (INIT_34)
, .INIT_35 (INIT_35)
, .INIT_36 (INIT_36)
, .INIT_37 (INIT_37)
, .INIT_38 (INIT_38)
, .INIT_39 (INIT_39)
, .INIT_3A (INIT_3A)
, .INIT_3B (INIT_3B)
, .INIT_3C (INIT_3C)
, .INIT_3D (INIT_3D)
, .INIT_3E (INIT_3E)
, .INIT_3F (INIT_3F)
, .INIT_40 (INIT_40)
, .INIT_41 (INIT_41)
, .INIT_42 (INIT_42)
, .INIT_43 (INIT_43)
, .INIT_44 (INIT_44)
, .INIT_45 (INIT_45)
, .INIT_46 (INIT_46)
, .INIT_47 (INIT_47)
, .INIT_48 (INIT_48)
, .INIT_49 (INIT_49)
, .INIT_4A (INIT_4A)
, .INIT_4B (INIT_4B)
, .INIT_4C (INIT_4C)
, .INIT_4D (INIT_4D)
, .INIT_4E (INIT_4E)
, .INIT_4F (INIT_4F)
, .INIT_50 (INIT_50)
, .INIT_51 (INIT_51)
, .INIT_52 (INIT_52)
, .INIT_53 (INIT_53)
, .INIT_54 (INIT_54)
, .INIT_55 (INIT_55)
, .INIT_56 (INIT_56)
, .INIT_57 (INIT_57)
, .INIT_58 (INIT_58)
, .INIT_59 (INIT_59)
, .INIT_5A (INIT_5A)
, .INIT_5B (INIT_5B)
, .INIT_5C (INIT_5C)
, .INIT_5D (INIT_5D)
, .INIT_5E (INIT_5E)
, .INIT_5F (INIT_5F)
, .INIT_60 (INIT_60)
, .INIT_61 (INIT_61)
, .INIT_62 (INIT_62)
, .INIT_63 (INIT_63)
, .INIT_64 (INIT_64)
, .INIT_65 (INIT_65)
, .INIT_66 (INIT_66)
, .INIT_67 (INIT_67)
, .INIT_68 (INIT_68)
, .INIT_69 (INIT_69)
, .INIT_6A (INIT_6A)
, .INIT_6B (INIT_6B)
, .INIT_6C (INIT_6C)
, .INIT_6D (INIT_6D)
, .INIT_6E (INIT_6E)
, .INIT_6F (INIT_6F)
, .INIT_70 (INIT_70)
, .INIT_71 (INIT_71)
, .INIT_72 (INIT_72)
, .INIT_73 (INIT_73)
, .INIT_74 (INIT_74)
, .INIT_75 (INIT_75)
, .INIT_76 (INIT_76)
, .INIT_77 (INIT_77)
, .INIT_78 (INIT_78)
, .INIT_79 (INIT_79)
, .INIT_7A (INIT_7A)
, .INIT_7B (INIT_7B)
, .INIT_7C (INIT_7C)
, .INIT_7D (INIT_7D)
, .INIT_7E (INIT_7E)
, .INIT_7F (INIT_7F)
This diff is collapsed.
/*******************************************************************************
* File: x393_cur_params_target.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Memory controller parameters that need adjustment during training
* Target ,pde
* Copyright (c) 2015 Elphel, Inc.
* x393_cur_params_target.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_cur_params_target.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
localparam DLY_LANE0_ODELAY = 80'hd85c1014141814181218;
localparam DLY_LANE0_IDELAY = 72'h2c7a8380897c807b88;
localparam DLY_LANE1_ODELAY = 80'hd8581812181418181814;
localparam DLY_LANE1_IDELAY = 72'h108078807a887c8280;
localparam DLY_CMDA = 256'hd3d3d3d4dcd1d8cc494949494949494949d4d3ccd3d3dbd4ccd4d2d3d1d2d8cc;
localparam DLY_PHASE = 8'h33;
// localparam DFLT_WBUF_DELAY = 4'h9;
\ No newline at end of file
This diff is collapsed.
/*******************************************************************************
* File: x393_mcontr_encode_cmd.vh
* Date:2015-02-09
* Author: Andrey Filippov
* Description: Functions used to encode memory controller sequences
*
* Copyright (c) 2015 Elphel, Inc.
* x393_mcontr_encode_cmd.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_mcontr_encode_cmd.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
function [31:0] func_encode_skip;
input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
input done; // end of sequence
input [2:0] bank; // bank (here OK to be any)
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column address
bank[2:0], // bank (here OK to be any)
3'b0, // RAS/CAS/WE, positive logic
odt_en, // enable ODT
cke, // disable CKE
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // connect to external buffer (but only if not paused)
1'b0, // nop
buf_rst);
end
endfunction
function [31:0] func_encode_cmd;
input [14:0] addr; // 15-bit row/column address
input [2:0] bank; // bank (here OK to be any)
input [2:0] rcw; // RAS/CAS/WE, positive logic
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input nop; // add NOP after the current command, keep other data
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column address
bank [2:0], // bank
rcw[2:0], // RAS/CAS/WE
odt_en, // enable ODT
cke, // may be optimized (removed from here)?
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
nop, // add NOP after the current command, keep other data
buf_rst // Reserved for future use
};
end
endfunction
This diff is collapsed.
/*******************************************************************************
* File: x393_simulation_parameters.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation-specific parameters for the x393
*
* Copyright (c) 2015 Elphel, Inc.
* x393_simulation_parameters.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_simulation_parameters.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
, // to continue previous parameter list
parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,
parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,
parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1
parameter integer AXI_TASK_HOLD=1.0,
// parameter [1:0] DEFAULT_STATUS_MODE=3,
parameter SIMUL_AXI_READ_WIDTH=16,
parameter MEMCLK_PERIOD = 5.0,
parameter FCLK0_PERIOD = 41.667, // 10.417, 24MHz
parameter FCLK1_PERIOD = 0.0,
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
// parameter SENSOR12BITS_NCOLS = 66, //58; //56; // 129; //128; //1288;
// parameter SENSOR12BITS_NROWS = 18, // 16; // 1032;
// parameter SENSOR12BITS_NROWB = 1, // number of "blank rows" from vact to 1-st hact
// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
//parameter tDDO = 10; // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TMD = 4, //
parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TDDO1 = 5, //
// parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines
// parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat)
// parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18)
parameter HISTOGRAM_LEFT = 0, // 2; // left
parameter HISTOGRAM_TOP = 8, // 2, // top
parameter HISTOGRAM_WIDTH = 6, // width
parameter HISTOGRAM_HEIGHT = 6, // height
parameter HISTOGRAM_STRAT_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
parameter WOI_WIDTH= 64,
parameter QUADRANTS_PXD_HACT_VACT = 6'h01 // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
\ No newline at end of file
/*******************************************************************************
* File: x393_tasks01.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation tasks for the x393 (low level)
*
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks01.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks01.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// Low-level tasks
// alternative way to check for empty read queue (without a separate counter)
task write_contol_register;
input [29:0] reg_addr;
// input integer reg_addr;
input [31:0] data;
begin
axi_write_single_w(CONTROL_ADDR+reg_addr, data);
end
endtask
task read_contol_register;
input [29:0] reg_addr;
begin
read_and_wait_w(CONTROL_RBACK_ADDR+reg_addr);
end
endtask
task wait_read_queue_empty;
begin
wait (~rvalid && rready && (rid==LAST_ARID)); // nothing left in read queue?
SIMUL_AXI_FULL<=1'b0;
end
endtask
task axi_set_rd_lag;
input [3:0] lag;
begin
@(posedge CLK);
RD_LAG <= lag;
end
endtask
task axi_set_b_lag;
input [3:0] lag;
begin
@(posedge CLK);
B_LAG <= lag;
end
endtask
task read_and_wait_w;
input [29:0] address;
begin
read_and_wait ({address,2'b0});
end
endtask
task read_and_wait;
input [31:0] address;
begin
axi_read_addr(
GLOBAL_READ_ID, // id
address & 32'hfffffffc, // addr
4'h0, // len - single
1 // burst type - increment
);
GLOBAL_READ_ID <= GLOBAL_READ_ID+1;
wait (!CLK && rvalid && rready);
wait (CLK);
registered_rdata <= rdata;