Few more changes to make the project synth in vdt enviroment

ddr3/1024Mb_ddr3_parameters.vh

+/home/alexey/tmp/sata2/x393/ddr3/1024Mb_ddr3_parameters.vh
\ No newline at end of file

ddr3/2048Mb_ddr3_parameters.vh

+/home/alexey/tmp/sata2/x393/ddr3/2048Mb_ddr3_parameters.vh
\ No newline at end of file

ddr3/4096Mb_ddr3_parameters.vh

+/home/alexey/tmp/sata2/x393/ddr3/4096Mb_ddr3_parameters.vh
\ No newline at end of file

dma/sata_top.v

@@ -84,7 +84,7 @@
     output  wire    [3:0]   afi_awcache,
     output  wire    [2:0]   afi_awprot,
     output  wire    [3:0]   afi_awlen,
-    output  wire    [2:0]   afi_awsize,
+    output  wire    [1:0]   afi_awsize,
     output  wire    [1:0]   afi_awburst,
     output  wire    [3:0]   afi_awqos,
     // write data
@@ -113,7 +113,7 @@
     output  wire    [3:0]   afi_arcache,
     output  wire    [2:0]   afi_arprot,
     output  wire    [3:0]   afi_arlen,
-    output  wire    [2:0]   afi_arsize,
+    output  wire    [1:0]   afi_arsize,
     output  wire    [1:0]   afi_arburst,
     output  wire    [3:0]   afi_arqos,
     // read data

dma/top.v

@@ -90,7 +90,7 @@ wire [ 1:0] afi0_awlock;     // output[1:0]
 wire [ 3:0] afi0_awcache;     // output[3:0] 
 wire [ 2:0] afi0_awprot;     // output[2:0] 
 wire [ 3:0] afi0_awlen;     // output[3:0] 
-wire [ 2:0] afi0_awsize;     // output[2:0] 
+wire [ 1:0] afi0_awsize;     // output[2:0] 
 wire [ 1:0] afi0_awburst;     // output[1:0] 
 wire [ 3:0] afi0_awqos;     // output[3:0] 
 wire [63:0] afi0_wdata;     // output[63:0] 
@@ -114,7 +114,7 @@ wire [ 1:0] afi0_arlock;     // output[1:0]
 wire [ 3:0] afi0_arcache;     // output[3:0] 
 wire [ 2:0] afi0_arprot;     // output[2:0] 
 wire [ 3:0] afi0_arlen;     // output[3:0] 
-wire [ 2:0] afi0_arsize;     // output[2:0] 
+wire [ 1:0] afi0_arsize;     // output[2:0] 
 wire [ 1:0] afi0_arburst;     // output[1:0] 
 wire [ 3:0] afi0_arqos;     // output[3:0] 
 wire [63:0] afi0_rdata;     // input[63:0] 

includes/coring.dat.vh

+, .INIT_00 (256'h4444444433333333333333332222222222222222111111111111111100000000)
+, .INIT_01 (256'h8888888877777777777777776666666666666666555555555555555544444444)
+, .INIT_02 (256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888)
+, .INIT_03 (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_04 (256'h4444444433333333333333332222222222222222111111111111111100000000)
+, .INIT_05 (256'h8888888877777777777777776666666666666666555555555555555544444444)
+, .INIT_06 (256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888)
+, .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_08 (256'h4444444433333333333333322222222222222221111111111111100000000000)
+, .INIT_09 (256'h8888888877777777777777776666666666666666555555555555555544444444)
+, .INIT_0A (256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888)
+, .INIT_0B (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_0C (256'h4444444433333333333333322222222222222221111111111111100000000000)
+, .INIT_0D (256'h8888888877777777777777776666666666666666555555555555555544444444)
+, .INIT_0E (256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888)
+, .INIT_0F (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_10 (256'h4444444333333333333333322222222222222211111111111000000000000000)
+, .INIT_11 (256'h8888888877777777777777776666666666666666555555555555555444444444)
+, .INIT_12 (256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888)
+, .INIT_13 (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_14 (256'h4444444333333333333333322222222222222211111111111000000000000000)
+, .INIT_15 (256'h8888888877777777777777776666666666666666555555555555555444444444)
+, .INIT_16 (256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888)
+, .INIT_17 (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_18 (256'h4444443333333333333222222222211111111111100000000000000000000000)
+, .INIT_19 (256'h8888888877777777777777766666666666666665555555555555555444444444)
+, .INIT_1A (256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888)
+, .INIT_1B (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_1C (256'h4444443333333333333222222222211111111111100000000000000000000000)
+, .INIT_1D (256'h8888888877777777777777766666666666666665555555555555555444444444)
+, .INIT_1E (256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888)
+, .INIT_1F (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_20 (256'h3333333332222222222211111111111111000000000000000000000000000000)
+, .INIT_21 (256'h8888888777777777777777766666666666666665555555555555544444444444)
+, .INIT_22 (256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999888888888)
+, .INIT_23 (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_24 (256'h3333333332222222222211111111111111000000000000000000000000000000)
+, .INIT_25 (256'h8888888777777777777777766666666666666665555555555555544444444444)
+, .INIT_26 (256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999888888888)
+, .INIT_27 (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_28 (256'h2222222222211111111111111110000000000000000000000000000000000000)
+, .INIT_29 (256'h8888888777777777777777666666666666655555555554444444443333333333)
+, .INIT_2A (256'hCCCCCCCCBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA9999999999999999888888888)
+, .INIT_2B (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_2C (256'h2222222222211111111111111110000000000000000000000000000000000000)
+, .INIT_2D (256'h8888888777777777777777666666666666655555555554444444443333333333)
+, .INIT_2E (256'hCCCCCCCCBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA9999999999999999888888888)
+, .INIT_2F (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC)
+, .INIT_31 (256'h5555444444443333333333322222222222221111111111111111111111110000)
+, .INIT_32 (256'hCCCCCCCBBBBBBBBBBBBBBAAAAAAAAA9999999998888888777777766666665555)
+, .INIT_33 (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCCC)
+, .INIT_35 (256'h5555444444443333333333322222222222221111111111111111111111110000)
+, .INIT_36 (256'hCCCCCCCBBBBBBBBBBBBBBAAAAAAAAA9999999998888888777777766666665555)
+, .INIT_37 (256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCCC)
+, .INIT_3B (256'hFFFFFFFFFEEDCBA9987766555444333332222222211111111111111111111100)
+, .INIT_3F (256'hFFFFFFFFFEEDCBA9987766555444333332222222211111111111111111111100)

includes/focus_filt.dat.vh

+, .INIT_00 (256'h000008880FFF0FFF0888044401110111000008880FFF0FFF0888044401110000)
+, .INIT_01 (256'h00000222044408880FFF0FFF088808880000044408880FFF0FFF088804440444)
+, .INIT_02 (256'h0000000001110222044408880FFF0FFF000001110222044408880FFF0FFF0FFF)
+, .INIT_03 (256'h0000000000000000000000000000000000000000000001110222044408880888)
+, .INIT_04 (256'h00008888FFFFFFFF888844441111111100008888FFFFFFFF8888444411110000)
+, .INIT_05 (256'h0000222244448888FFFFFFFF88888888000044448888FFFFFFFF888844444444)
+, .INIT_06 (256'h000000001111222244448888FFFFFFFF00001111222244448888FFFFFFFFFFFF)
+, .INIT_07 (256'h0000000000000000000000000000000000000000000011112222444488888888)

includes/huffman.dat.vh

+, .INIT_00 (256'h000800F8000700780005001A0004000B0003000400020001000200000004000A)
+, .INIT_01 (256'h00020000000000000000000000000000000000000010FF830010FF82000A03F6)
+, .INIT_02 (256'h0010FF850010FF84000B07F6000901F6000700790005001B0004000C00000000)
+, .INIT_03 (256'h00030002000000000000000000000000000000000010FF880010FF870010FF86)
+, .INIT_04 (256'h0010FF8B0010FF8A0010FF89000C0FF4000A03F7000800F90005001C00000000)
+, .INIT_05 (256'h00030003000000000000000000000000000000000010FF8E0010FF8D0010FF8C)
+, .INIT_06 (256'h0010FF920010FF910010FF900010FF8F000C0FF5000901F70006003A00000000)
+, .INIT_07 (256'h00030004000000000000000000000000000000000010FF950010FF940010FF93)
+, .INIT_08 (256'h0010FF9A0010FF990010FF980010FF970010FF96000A03F80006003B00000000)
+, .INIT_09 (256'h00030005000000000000000000000000000000000010FF9D0010FF9C0010FF9B)
+, .INIT_0A (256'h0010FFA20010FFA10010FFA00010FF9F0010FF9E000B07F70007007A00000000)
+, .INIT_0B (256'h00030006000000000000000000000000000000000010FFA50010FFA40010FFA3)
+, .INIT_0C (256'h0010FFAA0010FFA90010FFA80010FFA70010FFA6000C0FF60007007B00000000)
+, .INIT_0D (256'h0004000E000000000000000000000000000000000010FFAD0010FFAC0010FFAB)
+, .INIT_0E (256'h0010FFB20010FFB10010FFB00010FFAF0010FFAE000C0FF7000800FA00000000)
+, .INIT_0F (256'h0005001E000000000000000000000000000000000010FFB50010FFB40010FFB3)
+, .INIT_10 (256'h0010FFBA0010FFB90010FFB80010FFB70010FFB6000F7FC0000901F800000000)
+, .INIT_11 (256'h0006003E000000000000000000000000000000000010FFBD0010FFBC0010FFBB)
+, .INIT_12 (256'h0010FFC30010FFC20010FFC10010FFC00010FFBF0010FFBE000901F900000000)
+, .INIT_13 (256'h0007007E000000000000000000000000000000000010FFC60010FFC50010FFC4)
+, .INIT_14 (256'h0010FFCC0010FFCB0010FFCA0010FFC90010FFC80010FFC7000901FA00000000)
+, .INIT_15 (256'h000800FE000000000000000000000000000000000010FFCF0010FFCE0010FFCD)
+, .INIT_16 (256'h0010FFD50010FFD40010FFD30010FFD20010FFD10010FFD0000A03F900000000)
+, .INIT_17 (256'h000901FE000000000000000000000000000000000010FFD80010FFD70010FFD6)
+, .INIT_18 (256'h0010FFDE0010FFDD0010FFDC0010FFDB0010FFDA0010FFD9000A03FA00000000)
+, .INIT_19 (256'h00000000000000000000000000000000000000000010FFE10010FFE00010FFDF)
+, .INIT_1A (256'h0010FFE70010FFE60010FFE50010FFE40010FFE30010FFE2000B07F800000000)
+, .INIT_1B (256'h00000000000000000000000000000000000000000010FFEA0010FFE90010FFE8)
+, .INIT_1C (256'h0010FFF10010FFF00010FFEF0010FFEE0010FFED0010FFEC0010FFEB00000000)
+, .INIT_1D (256'h00000000000000000000000000000000000000000010FFF40010FFF30010FFF2)
+, .INIT_1E (256'h0010FFFB0010FFFA0010FFF90010FFF80010FFF70010FFF60010FFF5000B07F9)
+, .INIT_1F (256'h00000000000000000000000000000000000000000010FFFE0010FFFD0010FFFC)
+, .INIT_20 (256'h000700780006003800050019000500180004000A000300040002000100020000)
+, .INIT_21 (256'h0002000000000000000000000000000000000000000C0FF4000A03F6000901F4)
+, .INIT_22 (256'h0010FF88000C0FF5000B07F6000901F5000800F6000600390004000B00000000)
+, .INIT_23 (256'h00020001000000000000000000000000000000000010FF8B0010FF8A0010FF89)
+, .INIT_24 (256'h0010FF8D0010FF8C000F7FC2000C0FF6000A03F7000800F70005001A00000000)
+, .INIT_25 (256'h00020002000000000000000000000000000000000010FF900010FF8F0010FF8E)
+, .INIT_26 (256'h0010FF930010FF920010FF91000C0FF7000A03F8000800F80005001B00000000)
+, .INIT_27 (256'h00030006000000000000000000000000000000000010FF960010FF950010FF94)
+, .INIT_28 (256'h0010FF9B0010FF9A0010FF990010FF980010FF97000901F60006003A00000000)
+, .INIT_29 (256'h0004000E000000000000000000000000000000000010FF9E0010FF9D0010FF9C)
+, .INIT_2A (256'h0010FFA30010FFA20010FFA10010FFA00010FF9F000A03F90006003B00000000)
+, .INIT_2B (256'h0005001E000000000000000000000000000000000010FFA60010FFA50010FFA4)
+, .INIT_2C (256'h0010FFAB0010FFAA0010FFA90010FFA80010FFA7000B07F70007007900000000)
+, .INIT_2D (256'h0006003E000000000000000000000000000000000010FFAE0010FFAD0010FFAC)
+, .INIT_2E (256'h0010FFB30010FFB20010FFB10010FFB00010FFAF000B07F80007007A00000000)
+, .INIT_2F (256'h0007007E000000000000000000000000000000000010FFB60010FFB50010FFB4)
+, .INIT_30 (256'h0010FFBC0010FFBB0010FFBA0010FFB90010FFB80010FFB7000800F900000000)
+, .INIT_31 (256'h000800FE000000000000000000000000000000000010FFBF0010FFBE0010FFBD)
+, .INIT_32 (256'h0010FFC50010FFC40010FFC30010FFC20010FFC10010FFC0000901F700000000)
+, .INIT_33 (256'h000901FE000000000000000000000000000000000010FFC80010FFC70010FFC6)
+, .INIT_34 (256'h0010FFCE0010FFCD0010FFCC0010FFCB0010FFCA0010FFC9000901F800000000)
+, .INIT_35 (256'h000A03FE000000000000000000000000000000000010FFD10010FFD00010FFCF)
+, .INIT_36 (256'h0010FFD70010FFD60010FFD50010FFD40010FFD30010FFD2000901F900000000)
+, .INIT_37 (256'h000B07FE000000000000000000000000000000000010FFDA0010FFD90010FFD8)
+, .INIT_38 (256'h0010FFE00010FFDF0010FFDE0010FFDD0010FFDC0010FFDB000901FA00000000)
+, .INIT_39 (256'h00000000000000000000000000000000000000000010FFE30010FFE20010FFE1)
+, .INIT_3A (256'h0010FFE90010FFE80010FFE70010FFE60010FFE50010FFE4000B07F900000000)
+, .INIT_3B (256'h00000000000000000000000000000000000000000010FFEC0010FFEB0010FFEA)
+, .INIT_3C (256'h0010FFF20010FFF10010FFF00010FFEF0010FFEE0010FFED000E3FE000000000)
+, .INIT_3D (256'h00000000000000000000000000000000000000000010FFF50010FFF40010FFF3)
+, .INIT_3E (256'h0010FFFB0010FFFA0010FFF90010FFF80010FFF70010FFF6000F7FC3000A03FA)
+, .INIT_3F (256'h00000000000000000000000000000000000000000010FFFE0010FFFD0010FFFC)

includes/quantization_100.dat.vh

+, .INIT_00 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+, .INIT_01 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+, .INIT_02 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+, .INIT_03 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+, .INIT_04 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+, .INIT_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+, .INIT_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+, .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+, .INIT_08 (256'h2000333040005550555040005550555055505550800080005550800080005550)
+, .INIT_09 (256'h19A017401550155019A0155020002AB02490249019A033304000400033303330)
+, .INIT_0A (256'h0F1010000BA010001740174012500F10125013B010000E40125013B017401740)
+, .INIT_0B (256'h0CD00C300CD00E400AB00CD00BA00AB00B20111015500C300C300C300CD00D80)
+, .INIT_0C (256'h0CD00CD013B0174013B00CD01C70333033301C70333040003330400040005550)
+, .INIT_0D (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
+, .INIT_0E (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
+, .INIT_0F (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)

includes/ram18_declare_init.vh

+    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
+    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000

includes/ram18_pass_init.vh

+, .INITP_00 (INITP_00)
+, .INITP_01 (INITP_01)
+, .INITP_02 (INITP_02)
+, .INITP_03 (INITP_03)
+, .INITP_04 (INITP_04)
+, .INITP_05 (INITP_05)
+, .INITP_06 (INITP_06)
+, .INITP_07 (INITP_07)
+, .INIT_00  (INIT_00)
+, .INIT_01  (INIT_01)
+, .INIT_02  (INIT_02)
+, .INIT_03  (INIT_03)
+, .INIT_04  (INIT_04)
+, .INIT_05  (INIT_05)
+, .INIT_06  (INIT_06)
+, .INIT_07  (INIT_07)
+, .INIT_08  (INIT_08)
+, .INIT_09  (INIT_09)
+, .INIT_0A  (INIT_0A)
+, .INIT_0B  (INIT_0B)
+, .INIT_0C  (INIT_0C)
+, .INIT_0D  (INIT_0D)
+, .INIT_0E  (INIT_0E)
+, .INIT_0F  (INIT_0F)
+, .INIT_10  (INIT_10)
+, .INIT_11  (INIT_11)
+, .INIT_12  (INIT_12)
+, .INIT_13  (INIT_13)
+, .INIT_14  (INIT_14)
+, .INIT_15  (INIT_15)
+, .INIT_16  (INIT_16)
+, .INIT_17  (INIT_17)
+, .INIT_18  (INIT_18)
+, .INIT_19  (INIT_19)
+, .INIT_1A  (INIT_1A)
+, .INIT_1B  (INIT_1B)
+, .INIT_1C  (INIT_1C)
+, .INIT_1D  (INIT_1D)
+, .INIT_1E  (INIT_1E)
+, .INIT_1F  (INIT_1F)
+, .INIT_20  (INIT_20)
+, .INIT_21  (INIT_21)
+, .INIT_22  (INIT_22)
+, .INIT_23  (INIT_23)
+, .INIT_24  (INIT_24)
+, .INIT_25  (INIT_25)
+, .INIT_26  (INIT_26)
+, .INIT_27  (INIT_27)
+, .INIT_28  (INIT_28)
+, .INIT_29  (INIT_29)
+, .INIT_2A  (INIT_2A)
+, .INIT_2B  (INIT_2B)
+, .INIT_2C  (INIT_2C)
+, .INIT_2D  (INIT_2D)
+, .INIT_2E  (INIT_2E)
+, .INIT_2F  (INIT_2F)
+, .INIT_30  (INIT_30)
+, .INIT_31  (INIT_31)
+, .INIT_32  (INIT_32)
+, .INIT_33  (INIT_33)
+, .INIT_34  (INIT_34)
+, .INIT_35  (INIT_35)
+, .INIT_36  (INIT_36)
+, .INIT_37  (INIT_37)
+, .INIT_38  (INIT_38)
+, .INIT_39  (INIT_39)
+, .INIT_3A  (INIT_3A)
+, .INIT_3B  (INIT_3B)
+, .INIT_3C  (INIT_3C)
+, .INIT_3D  (INIT_3D)
+, .INIT_3E  (INIT_3E)
+, .INIT_3F  (INIT_3F)

includes/ram36_pass_init.vh

+, .INITP_00 (INITP_00)
+, .INITP_01 (INITP_01)
+, .INITP_02 (INITP_02)
+, .INITP_03 (INITP_03)
+, .INITP_04 (INITP_04)
+, .INITP_05 (INITP_05)
+, .INITP_06 (INITP_06)
+, .INITP_07 (INITP_07)
+, .INITP_08 (INITP_08)
+, .INITP_09 (INITP_09)
+, .INITP_0A (INITP_0A)
+, .INITP_0B (INITP_0B)
+, .INITP_0C (INITP_0C)
+, .INITP_0D (INITP_0D)
+, .INITP_0E (INITP_0E)
+, .INITP_0F (INITP_0F)
+, .INIT_00  (INIT_00)
+, .INIT_01  (INIT_01)
+, .INIT_02  (INIT_02)
+, .INIT_03  (INIT_03)
+, .INIT_04  (INIT_04)
+, .INIT_05  (INIT_05)
+, .INIT_06  (INIT_06)
+, .INIT_07  (INIT_07)
+, .INIT_08  (INIT_08)
+, .INIT_09  (INIT_09)
+, .INIT_0A  (INIT_0A)
+, .INIT_0B  (INIT_0B)
+, .INIT_0C  (INIT_0C)
+, .INIT_0D  (INIT_0D)
+, .INIT_0E  (INIT_0E)
+, .INIT_0F  (INIT_0F)
+, .INIT_10  (INIT_10)
+, .INIT_11  (INIT_11)
+, .INIT_12  (INIT_12)
+, .INIT_13  (INIT_13)
+, .INIT_14  (INIT_14)
+, .INIT_15  (INIT_15)
+, .INIT_16  (INIT_16)
+, .INIT_17  (INIT_17)
+, .INIT_18  (INIT_18)
+, .INIT_19  (INIT_19)
+, .INIT_1A  (INIT_1A)
+, .INIT_1B  (INIT_1B)
+, .INIT_1C  (INIT_1C)
+, .INIT_1D  (INIT_1D)
+, .INIT_1E  (INIT_1E)
+, .INIT_1F  (INIT_1F)
+, .INIT_20  (INIT_20)
+, .INIT_21  (INIT_21)
+, .INIT_22  (INIT_22)
+, .INIT_23  (INIT_23)
+, .INIT_24  (INIT_24)
+, .INIT_25  (INIT_25)
+, .INIT_26  (INIT_26)
+, .INIT_27  (INIT_27)
+, .INIT_28  (INIT_28)
+, .INIT_29  (INIT_29)
+, .INIT_2A  (INIT_2A)
+, .INIT_2B  (INIT_2B)
+, .INIT_2C  (INIT_2C)
+, .INIT_2D  (INIT_2D)
+, .INIT_2E  (INIT_2E)
+, .INIT_2F  (INIT_2F)
+, .INIT_30  (INIT_30)
+, .INIT_31  (INIT_31)
+, .INIT_32  (INIT_32)
+, .INIT_33  (INIT_33)
+, .INIT_34  (INIT_34)
+, .INIT_35  (INIT_35)
+, .INIT_36  (INIT_36)
+, .INIT_37  (INIT_37)
+, .INIT_38  (INIT_38)
+, .INIT_39  (INIT_39)
+, .INIT_3A  (INIT_3A)
+, .INIT_3B  (INIT_3B)
+, .INIT_3C  (INIT_3C)
+, .INIT_3D  (INIT_3D)
+, .INIT_3E  (INIT_3E)
+, .INIT_3F  (INIT_3F)
+, .INIT_40  (INIT_40)
+, .INIT_41  (INIT_41)
+, .INIT_42  (INIT_42)
+, .INIT_43  (INIT_43)
+, .INIT_44  (INIT_44)
+, .INIT_45  (INIT_45)
+, .INIT_46  (INIT_46)
+, .INIT_47  (INIT_47)
+, .INIT_48  (INIT_48)
+, .INIT_49  (INIT_49)
+, .INIT_4A  (INIT_4A)
+, .INIT_4B  (INIT_4B)
+, .INIT_4C  (INIT_4C)
+, .INIT_4D  (INIT_4D)
+, .INIT_4E  (INIT_4E)
+, .INIT_4F  (INIT_4F)
+, .INIT_50  (INIT_50)
+, .INIT_51  (INIT_51)
+, .INIT_52  (INIT_52)
+, .INIT_53  (INIT_53)
+, .INIT_54  (INIT_54)
+, .INIT_55  (INIT_55)
+, .INIT_56  (INIT_56)
+, .INIT_57  (INIT_57)
+, .INIT_58  (INIT_58)
+, .INIT_59  (INIT_59)
+, .INIT_5A  (INIT_5A)
+, .INIT_5B  (INIT_5B)
+, .INIT_5C  (INIT_5C)
+, .INIT_5D  (INIT_5D)
+, .INIT_5E  (INIT_5E)
+, .INIT_5F  (INIT_5F)
+, .INIT_60  (INIT_60)
+, .INIT_61  (INIT_61)
+, .INIT_62  (INIT_62)
+, .INIT_63  (INIT_63)
+, .INIT_64  (INIT_64)
+, .INIT_65  (INIT_65)
+, .INIT_66  (INIT_66)
+, .INIT_67  (INIT_67)
+, .INIT_68  (INIT_68)
+, .INIT_69  (INIT_69)
+, .INIT_6A  (INIT_6A)
+, .INIT_6B  (INIT_6B)
+, .INIT_6C  (INIT_6C)
+, .INIT_6D  (INIT_6D)
+, .INIT_6E  (INIT_6E)
+, .INIT_6F  (INIT_6F)
+, .INIT_70  (INIT_70)
+, .INIT_71  (INIT_71)
+, .INIT_72  (INIT_72)
+, .INIT_73  (INIT_73)
+, .INIT_74  (INIT_74)
+, .INIT_75  (INIT_75)
+, .INIT_76  (INIT_76)
+, .INIT_77  (INIT_77)
+, .INIT_78  (INIT_78)
+, .INIT_79  (INIT_79)
+, .INIT_7A  (INIT_7A)
+, .INIT_7B  (INIT_7B)
+, .INIT_7C  (INIT_7C)
+, .INIT_7D  (INIT_7D)
+, .INIT_7E  (INIT_7E)
+, .INIT_7F  (INIT_7F)

includes/x393_cur_params_target.vh

+/*******************************************************************************
+ * File: x393_cur_params_target.vh
+ * Date:2015-02-07  
+ * Author: Andrey Filippov     
+ * Description: Memory controller parameters that need adjustment during training
+ * Target ,pde
+ * Copyright (c) 2015 Elphel, Inc.
+ * x393_cur_params_target.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * x393_cur_params_target.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+localparam  DLY_LANE0_ODELAY =  80'hd85c1014141814181218;
+localparam  DLY_LANE0_IDELAY =  72'h2c7a8380897c807b88;
+localparam  DLY_LANE1_ODELAY =  80'hd8581812181418181814;
+localparam  DLY_LANE1_IDELAY =  72'h108078807a887c8280;
+localparam          DLY_CMDA = 256'hd3d3d3d4dcd1d8cc494949494949494949d4d3ccd3d3dbd4ccd4d2d3d1d2d8cc;
+localparam         DLY_PHASE =   8'h33;
+// localparam   DFLT_WBUF_DELAY =   4'h9;
+    
\ No newline at end of file

includes/x393_mcontr_encode_cmd.vh

+/*******************************************************************************
+ * File: x393_mcontr_encode_cmd.vh
+ * Date:2015-02-09  
+ * Author: Andrey Filippov     
+ * Description: Functions used to encode memory controller sequences
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * x393_mcontr_encode_cmd.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * x393_mcontr_encode_cmd.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+
+    function [31:0] func_encode_skip;
+        input [CMD_PAUSE_BITS-1:0] skip;       // number of extra cycles to skip (and keep all the other outputs)
+        input                      done;       // end of sequence 
+        input [2:0]                bank;       // bank (here OK to be any)
+        input                      odt_en;     // enable ODT
+        input                      cke;        // disable CKE
+        input                      sel;        // first/second half-cycle, other will be nop (cke+odt applicable to both)
+        input                      dq_en;      // enable (not tristate) DQ  lines (internal timing sequencer for 0->1 and 1->0)
+        input                      dqs_en;     // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
+        input                      dqs_toggle; // enable toggle DQS according to the pattern
+        input                      dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+        input                      buf_wr;     // connect to external buffer (but only if not paused)
+        input                      buf_rd;     // connect to external buffer (but only if not paused)
+        input                      buf_rst;    // connect to external buffer (but only if not paused)
+        begin
+            func_encode_skip= func_encode_cmd (
+                {{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]},       // 15-bit row/column address
+                bank[2:0],  // bank (here OK to be any)
+                3'b0,       // RAS/CAS/WE, positive logic
+                odt_en,     // enable ODT
+                cke,        // disable CKE
+                sel,        // first/second half-cycle, other will be nop (cke+odt applicable to both)
+                dq_en,      // enable (not tristate) DQ  lines (internal timing sequencer for 0->1 and 1->0)
+                dqs_en,     // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
+                dqs_toggle, // enable toggle DQS according to the pattern
+                dci,        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+                buf_wr,     // connect to external buffer (but only if not paused)
+                buf_rd,     // connect to external buffer (but only if not paused)
+                1'b0,       // nop
+                buf_rst);
+        end
+    endfunction
+
+    function [31:0] func_encode_cmd;
+        input               [14:0] addr;       // 15-bit row/column address
+        input                [2:0] bank;       // bank (here OK to be any)
+        input                [2:0] rcw;        // RAS/CAS/WE, positive logic
+        input                      odt_en;     // enable ODT
+        input                      cke;        // disable CKE
+        input                      sel;        // first/second half-cycle, other will be nop (cke+odt applicable to both)
+        input                      dq_en;      // enable (not tristate) DQ  lines (internal timing sequencer for 0->1 and 1->0)
+        input                      dqs_en;     // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
+        input                      dqs_toggle; // enable toggle DQS according to the pattern
+        input                      dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+        input                      buf_wr;     // connect to external buffer (but only if not paused)
+        input                      buf_rd;     // connect to external buffer (but only if not paused)
+        input                      nop;        // add NOP after the current command, keep other data
+        input                      buf_rst;    // connect to external buffer (but only if not paused)
+        begin
+            func_encode_cmd={
+            addr[14:0], // 15-bit row/column address
+            bank [2:0], // bank
+            rcw[2:0],   // RAS/CAS/WE
+            odt_en,     // enable ODT
+            cke,        // may be optimized (removed from here)?
+            sel,        // first/second half-cycle, other will be nop (cke+odt applicable to both)
+            dq_en,      // enable (not tristate) DQ  lines (internal timing sequencer for 0->1 and 1->0)
+            dqs_en,     // enable (not tristate) DQS  lines (internal timing sequencer for 0->1 and 1->0)
+            dqs_toggle, // enable toggle DQS according to the pattern
+            dci,        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+            buf_wr,     // phy_buf_wr,   // connect to external buffer (but only if not paused)
+            buf_rd,     // phy_buf_rd,    // connect to external buffer (but only if not paused)
+            nop,        // add NOP after the current command, keep other data
+            buf_rst     // Reserved for future use
+           };
+        end
+    endfunction
+ 

includes/x393_simulation_parameters.vh

+ /*******************************************************************************
+ * File: x393_simulation_parameters.vh
+ * Date:2015-02-07  
+ * Author: Andrey Filippov     
+ * Description: Simulation-specific parameters for the x393
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * x393_simulation_parameters.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * x393_simulation_parameters.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+    , // to continue previous parameter list
+    parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,
+    parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,
+    parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1
+    parameter integer AXI_TASK_HOLD=1.0,
+    
+//    parameter [1:0] DEFAULT_STATUS_MODE=3,
+    parameter       SIMUL_AXI_READ_WIDTH=16,
+    
+    parameter       MEMCLK_PERIOD = 5.0,
+    parameter       FCLK0_PERIOD =  41.667, //  10.417, 24MHz
+    parameter       FCLK1_PERIOD =  0.0,
+    
+//    parameter SENSOR12BITS_LLINE   =   192,   //   1664;//   line duration in clocks
+//    parameter SENSOR12BITS_NCOLS   =    66,   //58; //56; // 129; //128;   //1288;
+//    parameter SENSOR12BITS_NROWS   =    18,   // 16;   //   1032;
+//    parameter SENSOR12BITS_NROWB   =     1,   // number of "blank rows" from vact to 1-st hact
+//    parameter SENSOR12BITS_NROWA   =     1,   // number of "blank rows" from last hact to end of vact
+//    parameter nAV   =      24,   //240;   // clocks from ARO to VACT (actually from en_dclkd)
+//    parameter SENSOR12BITS_NBPF =       20,   //16; // bpf length
+    parameter SENSOR12BITS_NGPL =        8,   // bpf to hact
+    parameter SENSOR12BITS_NVLO =        1,   // VACT=0 in video mode (clocks)
+    //parameter tMD   =   14;    //
+    //parameter tDDO   =   10;   //   some confusion here - let's assume that it is from DCLK to Data out
+    parameter SENSOR12BITS_TMD =         4,   //
+    parameter SENSOR12BITS_TDDO =        2,   //   some confusion here - let's assume that it is from DCLK to Data out
+    parameter SENSOR12BITS_TDDO1 =       5,   //
+//    parameter SENSOR12BITS_TRIGDLY =     8,   // delay between trigger input and start of output (VACT) in lines
+//    parameter SENSOR12BITS_RAMP =        1,   // 1 - ramp, 0 - random (now - sensor.dat)
+//    parameter SENSOR12BITS_NEW_BAYER =   0,   // 0 - "old" tiles (16x16, 1 - new - (18x18)   
+
+    parameter HISTOGRAM_LEFT =           0,   // 2;   // left   
+    parameter HISTOGRAM_TOP =            8,   // 2,   // top
+    parameter HISTOGRAM_WIDTH =          6,   // width
+    parameter HISTOGRAM_HEIGHT =         6,   // height
+    parameter HISTOGRAM_STRAT_PAGE =    20'h12345,
+    parameter FRAME_WIDTH_ROUND_BITS =   9,  // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
+    
+    parameter WOI_WIDTH=                 64,
+    parameter QUADRANTS_PXD_HACT_VACT =  6'h01 // 2 bits each: data-0, hact - 1, vact - 2 
+                                               // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
+    
+    
\ No newline at end of file

includes/x393_tasks01.vh

+ /*******************************************************************************
+ * File: x393_tasks01.vh
+ * Date:2015-02-07  
+ * Author: Andrey Filippov     
+ * Description: Simulation tasks for the x393 (low level)
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * x393_tasks01.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * x393_tasks01.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+ // Low-level tasks 
+// alternative way to check for empty read queue (without a separate counter)
+
+    task   write_contol_register;
+        input [29:0] reg_addr;
+//        input integer reg_addr;
+        input [31:0] data;
+        begin
+            axi_write_single_w(CONTROL_ADDR+reg_addr, data);
+        end
+    endtask   
+
+    task   read_contol_register;
+        input [29:0] reg_addr;
+        begin
+            read_and_wait_w(CONTROL_RBACK_ADDR+reg_addr);
+        end
+    endtask   
+
+    task wait_read_queue_empty;
+        begin
+        wait (~rvalid && rready && (rid==LAST_ARID)); // nothing left in read queue?   
+        SIMUL_AXI_FULL<=1'b0;
+        end
+    endtask
+    task axi_set_rd_lag;
+        input [3:0] lag;
+        begin
+            @(posedge CLK);
+            RD_LAG <= lag;
+        end
+    endtask
+
+    task axi_set_b_lag;
+        input [3:0] lag;
+        begin
+            @(posedge CLK);
+            B_LAG <= lag;
+        end
+    endtask
+
+    task read_and_wait_w;
+    input [29:0] address;
+        begin
+            read_and_wait ({address,2'b0});
+        end
+    endtask
+
+    task read_and_wait;
+    input [31:0] address;
+    begin
+        axi_read_addr(
+            GLOBAL_READ_ID,    // id
+            address & 32'hfffffffc, // addr
+            4'h0, // len - single
+            1     // burst type - increment
+            );
+        GLOBAL_READ_ID <= GLOBAL_READ_ID+1;
+        wait (!CLK && rvalid && rready);
+        wait (CLK);
+        registered_rdata <= rdata;
+        wait (!CLK); // registered_rdata should be valid on exit
+        
+    end
+    endtask
+    
+    task axi_write_single_w; // address in bytes, not words
+        input [29:0] address;
+        input [31:0] data;
+        begin
+`ifdef DEBUG_WR_SINGLE
+          $display("axi_write_single_w %h:%h @ %t",address,data,$time);
+`endif                
+            axi_write_single ({address,2'b0},data);
+        end
+    endtask
+
+    task axi_write_single; // address in bytes, not words
+        input [31:0] address;
+        input [31:0] data;
+        begin
+          axi_write_addr_data(
+                    GLOBAL_WRITE_ID,    // id
+//                    address << 2, // addr
+                    address & 32'hfffffffc, // addr
+                    data,
+                    4'h0, // len - single
+                    1,    // burst type - increment
+                    1'b1, // data_en
+                    4'hf, // wstrb
+                    1'b1 // last
+                );
+          GLOBAL_WRITE_ID <= GLOBAL_WRITE_ID+1;
+          #0.1; // without this delay axi_write_addr_data() used old value of GLOBAL_WRITE_ID
+        end
+    endtask
+   
+    task axi_write_addr_data;
+        input [11:0] id;
+        input [31:0] addr;
+        input [31:0] data;
+        input [ 3:0] len;
+        input [ 1:0] burst;
+        input        data_en; // if 0 - do not send data, only address
+        input [ 3:0] wstrb;
+        input        last;
+        reg          data_sent;
+//        wire         data_sent_d;
+//        assign #(.1) data_sent_d= data_sent;
+        begin
+            wait (!CLK && AW_READY);
+            AWID_IN_r    <= id;
+            AWADDR_IN_r  <= addr;
+            AWLEN_IN_r   <= len;
+            AWSIZE_IN_r  <= 3'b010;
+            AWBURST_IN_r <= burst;
+            AW_SET_CMD_r <= 1'b1;
+            if (data_en && W_READY) begin
+                WID_IN_r <= id;
+                WDATA_IN_r <= data;
+                WSTRB_IN_r <= wstrb;
+                WLAST_IN_r <= last;
+                W_SET_CMD_r <= 1'b1; 
+                data_sent <= 1'b1;
+            end else begin
+                data_sent <= 1'b0;
+            end
+            DEBUG1 <=1'b1;
+            wait (CLK);
+            DEBUG1 <=1'b0;
+            AWID_IN_r    <= 'hz;
+            AWADDR_IN_r  <= 'hz;
+            AWLEN_IN_r   <= 'hz;
+            AWSIZE_IN_r  <= 'hz;
+            AWBURST_IN_r <= 'hz;
+            AW_SET_CMD_r <= 1'b0;
+            DEBUG2 <=1'b1;
+            if (data_sent) begin
+                WID_IN_r    <= 'hz;
+                WDATA_IN_r  <= 'hz;
+                WSTRB_IN_r  <= 'hz;
+                WLAST_IN_r  <= 'hz;
+                W_SET_CMD_r <= 1'b0; 
+            end
+// Now sent data if it was not sent simultaneously with the address
+            if (data_en && !data_sent) begin
+                DEBUG3 <=1'b1;
+                wait (!CLK && W_READY);
+                DEBUG3 <=1'b0;
+                WID_IN_r    <= id;
+                WDATA_IN_r  <= data;
+                WSTRB_IN_r  <= wstrb;
+                WLAST_IN_r  <= last;
+                W_SET_CMD_r <= 1'b1; 
+                wait (CLK);
+                DEBUG3 <=1'bx;
+                WID_IN_r    <= 'hz;
+                WDATA_IN_r  <= 'hz;
+                WSTRB_IN_r  <= 'hz;
+                WLAST_IN_r  <= 'hz;
+                W_SET_CMD_r <= 1'b0; 
+            end
+            DEBUG2 <=1'b0;
+            #0.1;
+            data_sent <= 1'b0;
+            #0.1;
+        end
+    endtask
+
+    task axi_write_data;
+        input [11:0] id;
+        input [31:0] data;
+        input [ 3:0] wstrb;
+        input        last;
+        begin
+            wait (!CLK && W_READY);
+            WID_IN_r    <= id;
+            WDATA_IN_r  <= data;
+            WSTRB_IN_r  <= wstrb;
+            WLAST_IN_r  <= last;
+            W_SET_CMD_r <= 1'b1; 
+            wait (CLK);
+            WID_IN_r    <= 12'hz;
+            WDATA_IN_r  <= 'hz;
+            WSTRB_IN_r  <= 4'hz;
+            WLAST_IN_r  <= 1'bz;
+            W_SET_CMD_r <= 1'b0;
+            #0.1;
+        end
+    endtask
+
+    task axi_read_addr;
+        input [11:0] id;
+        input [31:0] addr;
+        input [ 3:0] len;
+        input [ 1:0] burst;
+        begin
+            wait (!CLK && AR_READY);
+            ARID_IN_r    <= id;
+            ARADDR_IN_r  <= addr;
+            ARLEN_IN_r   <= len;
+            ARSIZE_IN_r  <= 3'b010;
+            ARBURST_IN_r <= burst;
+            AR_SET_CMD_r <= 1'b1;
+            wait (CLK);
+            ARID_IN_r    <= 12'hz;
+            ARADDR_IN_r  <= 'hz;
+            ARLEN_IN_r   <= 4'hz;
+            ARSIZE_IN_r  <= 3'hz;
+            ARBURST_IN_r <= 2'hz;
+            AR_SET_CMD_r <= 1'b0;
+            LAST_ARID <= id;
+            NUM_WORDS_EXPECTED <= NUM_WORDS_EXPECTED+len+1;
+        end
+    endtask
+

includes/x393_tasks_afi.vh

+ /*******************************************************************************
+ * File: x393_tasks_afi.vh
+ * Date:2015-02-07  
+ * Author: Andrey Filippov     
+ * Description: Simulation tasks for the AXI_HP (AFI)
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * x393_tasks_afi.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * x393_tasks_afi.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+
+ task membridge_setup;
+    input [28:0] len64;    // number of 64-bit words to transfer
+    input [28:0] width64;  // frame width in 64-bit words
+    input [28:0] start64;  // relative start address of the transfer (set to 0 when writing lo_addr64)
+    input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words 
+    input [28:0] size64;    // size of the system memory range in 64-bit words
+     
+    begin
+        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_LO_ADDR64,        {3'b0,lo_addr64});    
+        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_SIZE64,           {3'b0,size64});    
+        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_START64,          {3'b0,start64});    
+        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_LEN64,            {3'b0,len64});    
+        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_WIDTH64,          {3'b0,width64});    
+    end
+endtask
+
+task membridge_start;
+    input continue;    // 0 start from start64, 1 - continue from where it was
+    begin
+        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL,         {29'b0,continue,2'b11});    
+    end
+endtask
+
+task membridge_en; // SuppressThisWarning VEditor - may be unused
+    input en;    // not needed to start, pauses axi if set to 0 whil running, resets "done" status bit
+    begin
+        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL,         {31'b0,en});    
+    end
+endtask
+
+
+task afi_setup;
+    input   [1:0] port_num;
+    begin
+        afi_write_reg(port_num,  'h0, 0); // AFI_RDCHAN_CTRL
+        afi_write_reg(port_num,  'h4, 7); // AFI_RDCHAN_ISSUINGCAP
+        afi_write_reg(port_num,  'h8, 0); // AFI_RDQOS
+        //afi_write_reg(port_num,  'hc, 0); // AFI_RDDATAFIFO_LEVEL
+        //afi_write_reg(port_num, 'h10, 0); // AFI_RDDEBUG
+        afi_write_reg(port_num, 'h14, 'hf00); // AFI_WRCHAN_CTRL
+        afi_write_reg(port_num, 'h18, 7); // AFI_WRCHAN_ISSUINGCAP
+        afi_write_reg(port_num, 'h1c, 0); // AFI_WRQOS
+        //afi_write_reg(port_num,  'h20, 0); // AFI_WRDATAFIFO_LEVEL
+        //afi_write_reg(port_num, 'h24, 0); // AFI_WRDEBUG
+    end
+endtask
+
+task afi_write_reg;
+    input   [1:0] port_num;
+    input integer rel_baddr; // relative byte address
+    input  [31:0] data;
+    begin
+       ps_write_reg(32'hf8008000+ (port_num << 12) + (rel_baddr & 'hfffffffc), data);
+    end
+endtask
+
+task afi_read_reg; // SuppressThisWarning VEditor - may be unused
+    input   [1:0] port_num;
+    input integer rel_baddr; // relative byte address
+    input  verbose;
+    begin
+       ps_read_reg(32'hf8008000+ (port_num << 12) + (rel_baddr & 'hfffffffc), verbose);
+    end
+endtask
+
+task ps_write_reg;
+    input [31:0] ps_reg_addr;
+    input [31:0] ps_reg_data;
+    begin
+        @(posedge HCLK);
+        PS_REG_ADDR <= ps_reg_addr;
+        PS_REG_DIN <= ps_reg_data;
+        PS_REG_WR <= 1'b1;
+        @(posedge HCLK);
+        PS_REG_ADDR <= 'bx;
+        PS_REG_DIN <= 'bx;
+        PS_REG_WR <= 1'b0;
+    end
+endtask
+
+task ps_read_reg;
+    input [31:0] ps_reg_addr;
+    input verbose;
+    begin
+        @(posedge HCLK);
+        PS_REG_ADDR <= ps_reg_addr;
+        PS_REG_RD <= 1'b1;
+        @(posedge HCLK);
+        PS_REG_ADDR <= 'bx;
+        PS_REG_DIN <= 'bx;
+        PS_REG_WR <= 1'b0;
+        @(negedge HCLK);
+        if (verbose) begin
+            $display("ps_read_reg(%x) -> %x @%t",ps_reg_addr,PS_RDATA,$time);
+        end
+    end
+endtask
+ 
\ No newline at end of file

includes/x393_tasks_mcntrl_buffers.vh

+ /*******************************************************************************
+ * File: x393_tasks_mcntrl_buffers.vh
+ * Date:2015-02-07  
+ * Author: Andrey Filippov     
+ * Description: Simulation tasks for software reading/writing (with test patterns)
+ * of the block buffers.
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * x393_tasks_mcntrl_buffers.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * x393_tasks_mcntrl_buffers.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+/* 
+task write_block_scanline_chn;  // S uppressThisWarning VEditor : may be unused
+    input integer chn; // buffer channel
+    input   [1:0] page;
+//    input integer num_words; // number of words to write (will be rounded up to multiple of 16)
+    input [NUM_XFER_BITS:0] num_bursts; // number of 8-bursts to write (will be rounded up to multiple of 16)
+    input integer startX;
+    input integer startY;
+    reg    [29:0] start_addr;
+    begin
+        $display("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%d @%t", chn, page, startX, startY,num_words, $time);
+        case (chn)
+            1:  start_addr=MCONTR_BUF0_WR_ADDR + (page << 8);
+            3:  start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
+            default: begin
+                $display("**** ERROR: Invalid channel for write_block_scanline_chn = %d @%t", chn, $time);
+                start_addr = MCONTR_BUF0_WR_ADDR+ (page << 8);
+            end
+        endcase
+//        write_block_incremtal (start_addr, num_words, (startX<<2) + (startY<<16)); // 1 of startX is 8x16 bit, 16 bytes or 4 32-bit words
+        write_block_incremtal (start_addr, num_bursts << 2, (startX<<2) + (startY<<16)); // 1 of startX is 8x16 bit, 16 bytes or 4 32-bit words
+    end
+endtask
+*/
+
+task write_block_incremtal;
+    input [29:0] start_word_address;
+    input integer num_words; // number of words to write (will be rounded up to multiple of 16)
+    input integer start_value;      
+    integer i, j;
+    begin
+        $display("**** write_block_buf  @%t", $time);
+        for (i = 0; i < num_words; i = i + 16) begin
+            axi_write_addr_data(
+                i,    // id
+                {start_word_address,2'b0}+( i << 2),
+                start_value+i,
+                4'hf, // len
+                1,    // burst type - increment
+                1'b1, // data_en
+                4'hf, // wstrb
+                1'b0 // last
+                );
+//            $display("+Write block data (addr:data): 0x%x:0x%08x @%t", i, i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24), $time);
+            $display("+Write block incremental (addr:data): 0x%x:0x%08x @%t", i, start_value+i, $time);
+            for (j = 1; j < 16; j = j + 1) begin
+                axi_write_data(
+                    i,        // id
+                    start_value+i+j,
+                    4'hf, // wstrb
+                    (j == 15) ? 1'b1 : 1'b0 // last
+                    );
+                $display(" Write block incremental (addr:data): 0x%08x:0x%x @%t", (i + j), start_value+i+j, $time);
+            end
+        end
+    end
+endtask
+
+task write_block_buf_chn;  // S uppressThisWarning VEditor : may be unused
+    input integer chn; // buffer channel
+    input   [1:0] page;
+    input integer num_words; // number of words to write (will be rounded up to multiple of 16)
+    reg    [29:0] start_addr;
+    begin
+        case (chn)
+            0:  start_addr=MCONTR_BUF0_WR_ADDR + (page << 8);
+//            1:  start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
+            2:  start_addr=MCONTR_BUF2_WR_ADDR + (page << 8);
+            3:  start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
+            4:  start_addr=MCONTR_BUF4_WR_ADDR + (page << 8);
+            default: begin
+                $display("**** ERROR: Invalid channel (not 0,2,3,4) for write buffer = %d @%t", chn, $time);
+                start_addr = MCONTR_BUF0_WR_ADDR+ (page << 8);
+            end
+        endcase
+        write_block_buf (start_addr, num_words);
+    end
+endtask
+
+task write_block_buf;
+    input [29:0] start_word_address;
+    input integer num_words; // number of words to write (will be rounded up to multiple of 16)
+    integer i, j;
+    begin
+        $display("**** write_block_buf  @%t", $time);
+        for (i = 0; i < num_words; i = i + 16) begin
+            axi_write_addr_data(
+                i,    // id
+                {start_word_address,2'b0}+( i << 2),
+//                (MCONTR_BUF0_WR_ADDR + (page <<8)+ i) << 2, // addr
+                i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24),
+                4'hf, // len
+                1,    // burst type - increment
+                1'b1, // data_en
+                4'hf, // wstrb
+                1'b0 // last
+                );
+            $display("+Write block data (addr:data): 0x%x:0x%08x @%t", i, i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24), $time);
+            for (j = 1; j < 16; j = j + 1) begin
+                axi_write_data(
+                    i,        // id
+                    (i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24),
+                    4'hf, // wstrb
+                    (j == 15) ? 1'b1 : 1'b0 // last
+                    );
+                $display(" Write block data (addr:data): 0x%08x:0x%x @%t", (i + j),
+                    (i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24), $time);
+            end
+        end
+    end
+endtask
+   
+   // read memory
+task read_block_buf_chn;  // S uppressThisWarning VEditor : may be unused
+//    input integer chn; // buffer channel
+    input [3:0] chn; // buffer channel
+    input   [1:0] page;
+    input integer num_read; // number of words to read (will be rounded up to multiple of 16)
+    input wait_done; 
+    reg    [29:0] start_addr;
+    begin
+        case (chn)
+            0:  start_addr=MCONTR_BUF0_RD_ADDR + (page << 8);
+            2:  start_addr=MCONTR_BUF2_RD_ADDR + (page << 8);
+            3:  start_addr=MCONTR_BUF3_RD_ADDR + (page << 8);
+            4:  start_addr=MCONTR_BUF4_RD_ADDR + (page << 8);
+            default: begin
+                $display("**** ERROR: Invalid channel (not 0,2,3,4) for read buffer = %d @%t", chn, $time);
+                start_addr = 30'b0+ (page << 8);
+            end
+        endcase
+        read_block_buf (start_addr, num_read, wait_done);
+    end
+endtask
+
+task read_block_buf; 
+    input [29:0] start_word_address;
+    input integer num_read; // number of words to read (will be rounded up to multiple of 16)
+    input wait_done; 
+    integer i; //,j;
+    begin
+        wait (~rstb);
+        SIMUL_AXI_FULL<=1'b0;
+        $display("**** read_block_buf  @%t", $time);
+        axi_set_rd_lag(0);
+        for (i = 0; i < num_read; i = i + 16) begin
+            wait(arready);
+//                $display ("read_block_buf (0x%x) @%t",i,$time);
+            axi_read_addr(
+                i,    // id
+                {start_word_address,2'b0}+( i << 2), // addr
+                4'hf, // len
+                1     // burst type - increment
+                );
+        end
+        if (wait_done) begin
+//            wait (AXI_RD_EMPTY);
+            wait_read_queue_empty;
+        end
+    end
+endtask

includes/x393_tasks_mcntrl_en_dis_priority.vh

+ /*******************************************************************************
+ * File: x393_tasks_mcntrl_en_dis_priority.vh
+ * Date:2015-02-07  
+ * Author: Andrey Filippov     
+ * Description: Simulation tasks for software reading/writing (with test patterns)
+ * of the block buffers.
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * x393_tasks_mcntrl_en_dis_priority.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * x393_tasks_mcntrl_en_dis_priority.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+task enable_cmda;
+   input en;
+   begin
+        write_contol_register(MCONTR_PHY_0BIT_ADDR +  MCONTR_PHY_0BIT_CMDA_EN + en, 0);
+   end
+endtask
+
+task enable_cke;
+    input en;
+    begin
+        write_contol_register(MCONTR_PHY_0BIT_ADDR +  MCONTR_PHY_0BIT_CKE_EN + en, 0);
+    end
+endtask
+
+task activate_sdrst;
+    input en;
+    begin
+        write_contol_register(MCONTR_PHY_0BIT_ADDR +  MCONTR_PHY_0BIT_SDRST_ACT + en, 0);
+    end
+endtask
+
+task enable_refresh;
+    input en;
+    begin
+        write_contol_register(MCONTR_TOP_0BIT_ADDR +  MCONTR_TOP_0BIT_REFRESH_EN + en, 0);
+    end
+endtask
+
+task enable_memcntrl;
+    input en;
+    begin
+        write_contol_register(MCONTR_TOP_0BIT_ADDR +  MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
+    end
+endtask
+
+task enable_memcntrl_channels;
+    input [15:0] chnen; // bit-per-channel, 1 - enable;
+    begin
+        ENABLED_CHANNELS = chnen; // currently enabled memory channels
+        write_contol_register(MCONTR_TOP_16BIT_ADDR +  MCONTR_TOP_16BIT_CHN_EN, {16'b0,chnen});
+    end
+endtask
+
+task enable_memcntrl_en_dis;
+    input [3:0] chn;
+    input       en;
+    begin
+        if (en) begin
+            ENABLED_CHANNELS = ENABLED_CHANNELS | (1<<chn);
+        end else begin
+            ENABLED_CHANNELS = ENABLED_CHANNELS & ~(1<<chn);
+        end
+        write_contol_register(MCONTR_TOP_16BIT_ADDR +  MCONTR_TOP_16BIT_CHN_EN, {16'b0,ENABLED_CHANNELS});
+    end
+endtask
+
+
+task configure_channel_priority;
+    input [ 3:0] chn;
+    input [15:0] priority; // (higher is more important)
+    begin
+        write_contol_register(MCONTR_ARBIT_ADDR + chn, {16'b0,priority});
+    end
+endtask

includes/x393_tasks_mcntrl_timing.vh

+ /*******************************************************************************
+ * File: x393_tasks_mcntrl_timing.vh
+ * Date:2015-02-07  
+ * Author: Andrey Filippov     
+ * Description: Simulation tasks for programming I/O delays and other timing
+ * parameters in the memory controller
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * x393_tasks_mcntrl_timing.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * x393_tasks_mcntrl_timing.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+
+      task axi_set_same_delays;  //SuppressThisWarning VEditor : may be unused
+        input [7:0] dq_idelay;
+        input [7:0] dq_odelay;
+        input [7:0] dqs_idelay;
+        input [7:0] dqs_odelay;
+        input [7:0] dm_odelay;
+        input [7:0] cmda_odelay;
+        begin
+           $display("SET DELAYS(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x) @ %t",
+           dq_idelay,dq_odelay,dqs_idelay,dqs_odelay,dm_odelay,cmda_odelay,$time);
+            axi_set_dq_idelay(dq_idelay);
+            axi_set_dq_odelay(dq_odelay);
+            axi_set_dqs_idelay(dqs_idelay);
+            axi_set_dqs_odelay(dqs_odelay);
+            axi_set_dm_odelay(dm_odelay);
+            axi_set_cmda_odelay(cmda_odelay);
+        end
+    endtask
+
+    task axi_set_dqs_odelay_nominal; //SuppressThisWarning VEditor : may be unused
+     begin
+        $display("axi_set_dqs_odelay_nominal(0x%x,0x%x) @ %t",
+        (DLY_LANE0_ODELAY >> (8<<3)) & 32'hff,
+        (DLY_LANE1_ODELAY >> (8<<3)) & 32'hff,
+        $time);
+//        axi_set_dqs_idelay(
+        write_contol_register(LD_DLY_LANE0_ODELAY + 8,      (DLY_LANE0_ODELAY >> (8<<3)) & 32'hff);
+        write_contol_register(LD_DLY_LANE1_ODELAY + 8,      (DLY_LANE1_ODELAY >> (8<<3)) & 32'hff);
+        write_contol_register(DLY_SET,0);
+     end
+    endtask
+
+    task axi_set_dqs_idelay_nominal;  //SuppressThisWarning VEditor : may be unused
+     begin
+//        axi_set_dqs_idelay(
+        write_contol_register(LD_DLY_LANE0_IDELAY + 8,      (DLY_LANE0_IDELAY >> (8<<3)) & 32'hff);
+        write_contol_register(LD_DLY_LANE1_IDELAY + 8,      (DLY_LANE1_IDELAY >> (8<<3)) & 32'hff);
+        write_contol_register(DLY_SET,0);
+     end
+    endtask
+    
+    task axi_set_dqs_idelay_wlv;  //SuppressThisWarning VEditor : may be unused
+     begin
+        write_contol_register(LD_DLY_LANE0_IDELAY + 8,      DLY_LANE0_DQS_WLV_IDELAY);
+        write_contol_register(LD_DLY_LANE1_IDELAY + 8,      DLY_LANE1_DQS_WLV_IDELAY);
+        write_contol_register(DLY_SET,0);
+     end
+    endtask
+
+    task axi_set_delays; // set all individual delays
+     integer i;
+     begin
+         $display("axi_set_delays @ %t",$time);
+     
+        for (i=0;i<10;i=i+1) begin
+            write_contol_register(LD_DLY_LANE0_ODELAY + i,     (DLY_LANE0_ODELAY >> (i<<3)) & 32'hff);
+        end
+        for (i=0;i<9;i=i+1) begin
+            write_contol_register(LD_DLY_LANE0_IDELAY + i,      (DLY_LANE0_IDELAY >> (i<<3)) & 32'hff);
+        end
+        for (i=0;i<10;i=i+1) begin
+            write_contol_register(LD_DLY_LANE1_ODELAY + i,      (DLY_LANE1_ODELAY >> (i<<3)) & 32'hff);
+        end
+        for (i=0;i<9;i=i+1) begin
+            write_contol_register(LD_DLY_LANE1_IDELAY + i,      (DLY_LANE1_IDELAY >> (i<<3)) & 32'hff);
+        end
+        for (i=0;i<32;i=i+1) begin
+            write_contol_register(LD_DLY_CMDA + i,      (DLY_CMDA >> (i<<3)) & 32'hff);
+        end
+//        write_contol_register(DLY_SET,0);
+        axi_set_phase(DLY_PHASE); // also sets all delays
+     end
+    endtask
+
+    task axi_get_delays; // set all individual delays
+     integer i;
+     begin
+         $display("axi_get_delays @ %t",$time);
+     
+        for (i=0;i<10;i=i+1) begin
+            read_contol_register(LD_DLY_LANE0_ODELAY + i);
+        end
+        for (i=0;i<9;i=i+1) begin
+            read_contol_register(LD_DLY_LANE0_IDELAY + i);
+        end
+        for (i=0;i<10;i=i+1) begin
+            read_contol_register(LD_DLY_LANE1_ODELAY + i);
+        end
+        for (i=0;i<9;i=i+1) begin
+            read_contol_register(LD_DLY_LANE1_IDELAY + i);
+        end
+        for (i=0;i<32;i=i+1) begin
+            read_contol_register(LD_DLY_CMDA + i);
+        end
+        read_contol_register(LD_DLY_PHASE);
+     end
+    endtask
+
+
+    task axi_set_dq_idelay; // sets same delay to all dq idelay
+        input [7:0] delay;
+        begin
+           $display("SET DQ IDELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_LANE0_IDELAY, 8, delay);
+           axi_set_multiple_delays(LD_DLY_LANE1_IDELAY, 8, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+    task axi_set_dq_odelay;
+        input [7:0] delay;
+        begin
+           $display("SET DQ ODELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_LANE0_ODELAY, 8, delay);
+           axi_set_multiple_delays(LD_DLY_LANE1_ODELAY, 8, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+    task axi_set_dqs_idelay;
+        input [7:0] delay;
+        begin
+           $display("SET DQS IDELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_LANE0_IDELAY + 8, 1, delay);
+           axi_set_multiple_delays(LD_DLY_LANE1_IDELAY + 8, 1, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+    task axi_set_dqs_odelay;
+        input [7:0] delay;
+        begin
+           $display("SET DQS ODELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_LANE0_ODELAY + 8, 1, delay);
+           axi_set_multiple_delays(LD_DLY_LANE1_ODELAY + 8, 1, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+    task axi_set_dm_odelay;
+        input [7:0] delay;
+        begin
+           $display("SET DQM IDELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_LANE0_ODELAY + 9, 1, delay);
+           axi_set_multiple_delays(LD_DLY_LANE1_ODELAY + 9, 1, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+    task axi_set_cmda_odelay;
+        input [7:0] delay;
+        begin
+           $display("SET COMMAND and ADDRESS ODELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_CMDA, 32, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+
+    task axi_set_multiple_delays;
+        input [29:0] reg_addr;
+        input integer number;
+        input [7:0]  delay;
+        integer i;
+        begin
+           for (i=0;i<number;i=i+1) begin
+                write_contol_register(reg_addr + i, {24'b0,delay}); // control regiter address
+           end
+        end
+    endtask
+
+    task axi_set_phase;
+        input [PHASE_WIDTH-1:0] phase;
+        begin
+            $display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
+            write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
+            write_contol_register(DLY_SET,0);
+            target_phase <= phase;
+        end
+    endtask
+ 
+     task axi_set_wbuf_delay;
+        input [3:0] delay;
+        begin
+            $display("SET WBUF DELAY to 0x%x @ %t",delay,$time);
+            write_contol_register(MCONTR_PHY_16BIT_ADDR+MCONTR_PHY_16BIT_WBUF_DELAY, {28'h0, delay});
+        end
+    endtask
+ 
+ 
+// set dq /dqs tristate on/off patterns
+    task axi_set_tristate_patterns;
+        begin
+            $display("SET TRISTATE PATTERNS @ %t",$time);    
+            write_contol_register(MCONTR_PHY_16BIT_ADDR +MCONTR_PHY_16BIT_PATTERNS_TRI,
+                {16'h0, DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
+        end
+    endtask
+
+ task axi_set_dqs_dqm_patterns;
+        begin
+            $display("SET DQS+DQM PATTERNS @ %t",$time);    
+ // set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)        
+            write_contol_register(MCONTR_PHY_16BIT_ADDR + MCONTR_PHY_16BIT_PATTERNS,
+                32'h0055);
+        end
+ endtask
+ 

includes/x393_tasks_ps_pio.vh

+ /*******************************************************************************
+ * File: x393_tasks_ps_pio.vh
+ * Date:2015-02-07  
+ * Author: Andrey Filippov     
+ * Description: Simulation tasks for mcntrl_ps_pio module (launching software
+ * - programmed memory transaction sequences)
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * x393_tasks_ps_pio.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * x393_tasks_ps_pio.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+task schedule_ps_pio; // schedule software-control memory operation (may need to check FIFO status first)
+    input [9:0] seq_addr; // sequence start address
+    input [1:0] page;     // buffer page number
+    input       urgent;   // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
+    input       chn;      // channel buffer to use: 0 - memory read, 1 - memory write
+    input       wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
+    begin
+//        wait_ps_pio_ready(DEFAULT_STATUS_MODE); // wait FIFO not half full 
+        write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_CMD, {17'b0,wait_complete,chn,urgent,page,seq_addr});
+    end
+endtask
+
+task wait_ps_pio_ready; // wait PS PIO module can accept comamnds (fifo half empty)
+    input [1:0] mode;
+    input       sync_seq; //  synchronize sequences
+    begin
+        wait_status_condition (
+            MCNTRL_PS_STATUS_REG_ADDR,
+            MCNTRL_PS_ADDR+MCNTRL_PS_STATUS_CNTRL,
+            mode,
+            0,
+            2 << STATUS_2LSB_SHFT,
+            0,
+            sync_seq);
+    end
+endtask
+task wait_ps_pio_done; // wait PS PIO module has no pending/running memory transaction
+    input [1:0] mode;
+    input       sync_seq; //  synchronize sequences
+    begin
+        wait_status_condition (
+            MCNTRL_PS_STATUS_REG_ADDR,
+            MCNTRL_PS_ADDR+MCNTRL_PS_STATUS_CNTRL,
+            mode,
+            0,
+            3 << STATUS_2LSB_SHFT,
+            0,
+            sync_seq);
+    end
+endtask
+ 

includes/x393_tasks_status.vh

+ /*******************************************************************************
+ * File: x393_status.vh
+ * Date:2015-02-07  
+ * Author: Andrey Filippov     
+ * Description: Simulation tasks for the x393 related to status
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * x393_status.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * x393_status.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+
+// CVC bug that is supposed to be already fixed 
+`ifdef CVC 
+task wait_status_condition;
+    input [STATUS_DEPTH-1:0] status_address;
+    input [29:0] status_control_address;
+    input  [1:0] status_mode;
+    input [25:0] pattern;        // bits as in read registers
+    input [25:0] mask;           // which bits to compare
+    input        invert_match;   // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
+    input        wait_seq;
+    reg          match;
+    reg    [5:0] seq_num;
+    reg [31:0] pattern1;
+    reg [31:0] mask1;
+    begin
+        WAITING_STATUS = 1;
+        pattern1 = {6'h0,pattern};
+        mask1 = {6'h0,mask};
+        for (match=0; !match; match = invert_match ^ (((registered_rdata ^ pattern1) & mask1)==0)) begin
+            read_status(status_address);
+            if (wait_seq) begin 
+                seq_num = (registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20)&'h30;
+                write_contol_register(status_control_address, {24'b0,status_mode,seq_num});
+                read_status(status_address);
+                while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ seq_num) & 6'h30)!=0) begin // match just 2 MSBs
+                    read_status(status_address);
+                end
+            end
+        pattern1 = {6'h0,pattern};
+        mask1 = {6'h0,mask};
+        end
+        WAITING_STATUS = 0;
+    end
+endtask
+`else
+task wait_status_condition;
+    input [STATUS_DEPTH-1:0] status_address;
+    input [29:0] status_control_address;
+    input  [1:0] status_mode;
+    input [25:0] pattern;        // bits as in read registers
+    input [25:0] mask;           // which bits to compare
+    input        invert_match;   // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
+    input        wait_seq;
+    reg          match;
+    reg    [5:0] seq_num;
+    begin
+        WAITING_STATUS = 1;
+        for (match=0; !match; match = invert_match ^ (((registered_rdata ^ {6'h0,pattern}) & {6'h0,mask})==0)) begin
+            read_status(status_address);
+            if (wait_seq) begin 
+                seq_num = (registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20)&'h30;
+                write_contol_register(status_control_address, {24'b0,status_mode,seq_num});
+                read_status(status_address);
+                while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ seq_num) & 6'h30)!=0) begin // match just 2 MSBs
+                    read_status(status_address);
+                end
+            end
+        end
+        WAITING_STATUS = 0;
+    end
+endtask    
+`endif
+/*
+task wait_status_condition_auto; // assumes status is already updating
+    input [STATUS_DEPTH-1:0] status_address;
+    input [29:0] status_control_address;
+    input  [1:0] status_mode;
+    input [25:0] pattern;        // bits as in read registers
+    input [25:0] mask;           // which bits to compare
+    input        invert_match;   // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
+    reg          match;
+    begin
+        WAITING_STATUS = 1;
+        for (match=0; !match; match = invert_match ^ (((registered_rdata ^ {6'h0,pattern}) & {6'h0,mask})==0)) begin
+            read_status(status_address);
+        end
+        WAITING_STATUS = 0;
+    end
+endtask    
+*/
+
+ task wait_phase_shifter_ready;
+    begin
+        WAITING_STATUS = 1;
+        read_status(MCONTR_PHY_STATUS_REG_ADDR);
+        while (((registered_rdata & STATUS_PSHIFTER_RDY_MASK) == 0) || (((registered_rdata ^ {24'h0,target_phase}) & 'hff) != 0)) begin
+            read_status(MCONTR_PHY_STATUS_REG_ADDR); // exits after negedge CLK
+        end
+        WAITING_STATUS = 0;
+    end
+ endtask
+ 
+ task read_all_status;
+    begin
+        $display (" read_all_status @%t",$time);
+        read_status (MCONTR_PHY_STATUS_REG_ADDR);
+        read_status (MCONTR_TOP_STATUS_REG_ADDR);
+        read_status (MCNTRL_PS_STATUS_REG_ADDR);
+        read_status (MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR);
+        read_status (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR);
+        read_status (MCNTRL_TILED_STATUS_REG_CHN2_ADDR);
+        read_status (MCNTRL_TILED_STATUS_REG_CHN4_ADDR);
+//        read_status (MCNTRL_TEST01_STATUS_REG_CHN1_ADDR);
+        read_status (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR);
+        read_status (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR);
+        read_status (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR);
+        read_status (MEMBRIDGE_STATUS_REG);
+        
+    end
+ endtask 
+  
+ task read_status;
+    input [STATUS_DEPTH-1:0] address;
+    begin
+        read_and_wait_w(STATUS_ADDR + address ); // Will set:       registered_rdata <= rdata;
+        
+    end
+ endtask
+  
+  
+ task program_status_all;
+    input [1:0] mode;
+    input [5:0] seq_num;
+    begin
+        program_status (MCONTR_PHY_16BIT_ADDR,     MCONTR_PHY_STATUS_CNTRL,        mode,seq_num); //MCONTR_PHY_STATUS_REG_ADDR=          'h0,
+        program_status (MCONTR_TOP_16BIT_ADDR,     MCONTR_TOP_16BIT_STATUS_CNTRL,  mode,seq_num); //MCONTR_TOP_STATUS_REG_ADDR=          'h1,
+        program_status (MCNTRL_PS_ADDR,            MCNTRL_PS_STATUS_CNTRL,         mode,seq_num); //MCNTRL_PS_STATUS_REG_ADDR=           'h2,
+        program_status (MCNTRL_SCANLINE_CHN1_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL,   mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
+        program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL,   mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
+        program_status (MCNTRL_TILED_CHN2_ADDR,    MCNTRL_TILED_STATUS_CNTRL,      mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR=   'h6,
+        program_status (MCNTRL_TILED_CHN4_ADDR,    MCNTRL_TILED_STATUS_CNTRL,      mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR=   'h6,
+//        program_status (MCNTRL_TEST01_ADDR,        MCNTRL_TEST01_CHN1_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,
+        program_status (MCNTRL_TEST01_ADDR,        MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,
+        program_status (MCNTRL_TEST01_ADDR,        MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR=  'h3d,
+        program_status (MCNTRL_TEST01_ADDR,        MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR=  'h3e,
+        program_status (MEMBRIDGE_ADDR    ,        MEMBRIDGE_STATUS_CNTRL,         mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR=  'h3e,
+    end
+ endtask
+  
+ task   program_status;
+    input [29:0] base_addr;
+    input  [7:0] reg_addr;
+    input  [1:0] mode;
+ // mode bits:
+ // 0 disable status generation,
+ // 1 single status request,
+ // 2 - auto status, keep specified seq number,
+ // 3 - auto, inc sequence number 
+    input  [5:0] seq_number;
+    begin
+//        axi_write_single_w(CONTROL_ADDR+base_addr+reg_addr, {24'b0,mode,seq_number});
+        write_contol_register(base_addr + reg_addr, {24'b0,mode,seq_number});
+    end
+ endtask   
+    

system_defines.vh

+  // This file may be used to define same pre-processor macros to be included into each parsed file
+`ifndef SYSTEM_DEFINES
+  `define SYSTEM_DEFINES
+  `define PRELOAD_BRAMS
+// Enviroment-dependent options
+  `ifdef IVERILOG
+    `define SIMULATION
+    `define OPEN_SOURCE_ONLY
+  `else
+    `ifdef CVC
+      `define SIMULATION
+      `define OPEN_SOURCE_ONLY
+    `endif // CVC
+  `endif // IVERILOG
+  
+// will not use simultaneous reset in shift registers, just and input data with ~rst  
+ `define SHREG_SEQUENTIAL_RESET 1
+// synthesis does to recognize global clock as G input of the primitive latch 
+ `undef INFER_LATCHES
+ // define when using CDC - it does not support them
+ `undef IGNORE_ATTR
+//`define MEMBRIDGE_DEBUG_READ 1
+  `define use200Mhz 1
+  `define USE_CMD_ENCOD_TILED_32_RD 1  
+  // It can be used to check different `ifdef branches
+  //`define XIL_TIMING //Simprim 
+  `define den4096Mb 1
+//  `define IVERILOG
+  // defines for memory channels
+  // chn 0 is read from memory and write to memory
+ `define def_enable_mem_chn0
+ `define def_read_mem_chn0
+ `define def_write_mem_chn0
+ `undef  def_scanline_chn0
+ `undef  def_tiled_chn0
+ 
+  // chn 1 is scanline r+w
+ `define  def_enable_mem_chn1
+ `define  def_read_mem_chn1
+ `define  def_write_mem_chn1
+ `define  def_scanline_chn1
+ `undef   def_tiled_chn1
+
+  // chn 2 is tiled r+w
+ `define  def_enable_mem_chn2
+ `define  def_read_mem_chn2
+ `define  def_write_mem_chn2
+ `undef   def_scanline_chn2
+ `define  def_tiled_chn2
+
+  // chn 3 is scanline r+w (reuse later)
+ `define  def_enable_mem_chn3
+ `define  def_read_mem_chn3
+ `define  def_write_mem_chn3
+ `define  def_scanline_chn3
+ `undef   def_tiled_chn3
+
+  // chn 4 is tiled r+w (reuse later)
+ `define  def_enable_mem_chn4
+ `define  def_read_mem_chn4
+ `define  def_write_mem_chn4
+ `undef   def_scanline_chn4
+ `define  def_tiled_chn4
+
+  // chn 5 is disabled
+ `undef def_enable_mem_chn5
+
+  // chn 6 is disabled
+ `undef  def_enable_mem_chn6
+ 
+  // chn 7 is disabled
+ `undef  def_enable_mem_chn7
+ 
+  // chn 8 is scanline w (sensor channel 0)
+ `define  def_enable_mem_chn8
+ `undef   def_read_mem_chn8
+ `define  def_write_mem_chn8
+ `define  def_scanline_chn8
+ `undef   def_tiled_chn8
+
+  // chn 9 is scanline w (sensor channel 1)
+ `define  def_enable_mem_chn9
+ `undef   def_read_mem_chn9
+ `define  def_write_mem_chn9
+ `define  def_scanline_chn9
+ `undef   def_tiled_chn9
+
+  // chn 10 is scanline w (sensor channel 2)
+ `define  def_enable_mem_chn10
+ `undef   def_read_mem_chn10
+ `define  def_write_mem_chn10
+ `define  def_scanline_chn10
+ `undef   def_tiled_chn10
+
+  // chn 11 is scanline w (sensor channel 3)
+ `define  def_enable_mem_chn11
+ `undef   def_read_mem_chn11
+ `define  def_write_mem_chn11
+ `define  def_scanline_chn11
+ `undef   def_tiled_chn11
+
+  // chn 12 is tiled read (compressor channel 0)
+ `define  def_enable_mem_chn12
+ `define  def_read_mem_chn12
+ `undef   def_write_mem_chn12
+ `undef   def_scanline_chn12
+ `define  def_tiled_chn12
+ 
+  // chn 12 is tiled read (compressor channel 1)
+ `define  def_enable_mem_chn13
+ `define  def_read_mem_chn13
+ `undef   def_write_mem_chn13
+ `undef   def_scanline_chn13
+ `define  def_tiled_chn13
+ 
+  // chn 12 is tiled read (compressor channel 2)
+ `define  def_enable_mem_chn14
+ `define  def_read_mem_chn14
+ `undef   def_write_mem_chn14
+ `undef   def_scanline_chn14
+ `define  def_tiled_chn14
+ 
+  // chn 12 is tiled read (compressor channel 3)
+ `define  def_enable_mem_chn15
+ `define  def_read_mem_chn15
+ `undef   def_write_mem_chn15
+ `undef   def_scanline_chn15
+ `define  def_tiled_chn15
+`endif
+ 
\ No newline at end of file

wrapper/GTXE2_GPL.v

@@ -88,7 +88,7 @@ module gtxe2_chnl_cpll(
     input   wire    [4:0]   PMARSVDIN,
     input   wire    [4:0]   PMARSVDIN2,
     input   wire    [19:0]  TSTIN,
-    output  wire            TSTOUT,
+    output  wire    [9:0]   TSTOUT,
 
 // internal
     input   wire    ref_clk,
@@ -287,7 +287,7 @@ module gtxe2_chnl_clocking(
     output  wire            rx_sipo_clk,
 
 // additional ports to cpll
-    output              TSTOUT,
+    output  [9:0]       TSTOUT,
     input   [15:0]      GTRSVD,
     input   [15:0]      PCSRSVDIN,
     input   [4:0]       PCSRSVDIN2,
@@ -2208,7 +2208,7 @@ module gtxe2_chnl(
     output  wire            rx_serial_clk,
 
 // additional ports to pll
-    output              TSTOUT,
+    output  [9:0]       TSTOUT,
     input   [15:0]      GTRSVD,
     input   [15:0]      PCSRSVDIN,
     input   [4:0]       PCSRSVDIN2,
@@ -2428,7 +2428,7 @@ module GTXE2_GPL(
     output              CPLLFBCLKLOST,
     output              CPLLLOCK,
     output              CPLLREFCLKLOST,
-    output              TSTOUT,
+    output  [9:0]       TSTOUT,
     input   [15:0]      GTRSVD,
     input   [15:0]      PCSRSVDIN,
     input   [4:0]       PCSRSVDIN2,
@@ -2445,7 +2445,7 @@ module GTXE2_GPL(
     input               TXPMARESET,
     output              TXRESETDONE,
     input               TXUSERRDY,
-    output              PCSRSVDOUT,
+    output  [15:0]      PCSRSVDOUT,
 // RX Reset ports, UG476 p.73
     input               GTRXRESET,
     input               RXPMARESET,
@@ -2651,8 +2651,8 @@ module GTXE2_GPL(
     input               RXDLYOVRDEN,
     input               RXDDIEN,
     output              RXPHALIGNDONE,
-    output              RXPHMONITOR,
-    output              RXPHSLIPMONITOR,
+    output  [4:0]       RXPHMONITOR,
+    output  [4:0]       RXPHSLIPMONITOR,
     output              RXDLYSRESETDONE,
 // RX Buffer Ports, ug476 p.259
     output  [2:0]       RXBUFSTATUS,

wrapper/gtxe2_channel_wrapper.v

@@ -18,7 +18,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
-`define OPEN_SOURCE_ONLY
 module gtxe2_channel_wrapper(
 // clocking ports, UG476 p.37
     input   [2:0]       CPLLREFCLKSEL,
@@ -40,7 +39,7 @@ module gtxe2_channel_wrapper(
     output              CPLLFBCLKLOST,
     output              CPLLLOCK,
     output              CPLLREFCLKLOST,
-    output              TSTOUT,
+    output  [9:0]       TSTOUT,
     input   [15:0]      GTRSVD,
     input   [15:0]      PCSRSVDIN,
     input   [4:0]       PCSRSVDIN2,
@@ -57,7 +56,7 @@ module gtxe2_channel_wrapper(
     input               TXPMARESET,
     output              TXRESETDONE,
     input               TXUSERRDY,
-    output              PCSRSVDOUT,
+    output     [15:0]   PCSRSVDOUT,
 // RX Reset ports, UG476 p.73
     input               GTRXRESET,
     input               RXPMARESET,
@@ -263,8 +262,8 @@ module gtxe2_channel_wrapper(
     input               RXDLYOVRDEN,
     input               RXDDIEN,
     output              RXPHALIGNDONE,
-    output              RXPHMONITOR,
-    output              RXPHSLIPMONITOR,
+    output  [4:0]       RXPHMONITOR,
+    output  [4:0]       RXPHSLIPMONITOR,
     output              RXDLYSRESETDONE,
 // RX Buffer Ports, ug476 p.259
     output  [2:0]       RXBUFSTATUS,
@@ -358,10 +357,10 @@ parameter   TXPHDLY_CFG                  = 24'h0;
 parameter   TXDLY_CFG                    = 16'h0;
 parameter   TXDLY_LCFG                   = 9'h0;
 parameter   TXDLY_TAP_CFG                = 16'h0;
-parameter   TXSYNC_MULTILANE             = 1'b0;
-parameter   TXSYNC_SKIP_DA               = 1'b0;
-parameter   TXSYNC_OVRD                  = 1'b1;
-parameter   LOOPBACK_CFG                 = 1'b0;
+//parameter   TXSYNC_MULTILANE             = 1'b0;
+//parameter   TXSYNC_SKIP_DA               = 1'b0;
+//parameter   TXSYNC_OVRD                  = 1'b1;
+//parameter   LOOPBACK_CFG                 = 1'b0;
 // TX Pattern Generator, ug476 p.147
 parameter   RXPRBS_ERR_LOOPBACK          = 1'b0;
 // TX Fabric Clock Output Control Attributes, ug476 p. 153
@@ -459,7 +458,7 @@ parameter   RX_DATA_WIDTH                = 20;
 parameter   RX_INT_DATAWIDTH             = 0;
 parameter   ES_PMA_CFG                   = 10'h0;
 // Pattern Checker Attributes, ug476 p.226
-parameter   RX_PRBS_ERR_CNT              = 16'h15c;
+//parameter   RX_PRBS_ERR_CNT              = 16'h15c;
 // RX Byte and Word Alignment Attributes, ug476 p.235
 parameter   ALIGN_COMMA_WORD             = 1;
 parameter   ALIGN_COMMA_ENABLE           = 10'b1111111111;
@@ -472,7 +471,7 @@ parameter   SHOW_REALIGN_COMMA           = "TRUE";
 parameter   RXSLIDE_MODE                 = "OFF";
 parameter   RXSLIDE_AUTO_WAIT            = 7;
 parameter   RX_SIG_VALID_DLY             = 10;
-parameter   COMMA_ALIGN_LATENCY          = 9'h14e;
+//parameter   COMMA_ALIGN_LATENCY          = 9'h14e;
 // RX 8B/10B Decoder Attributes, ug476 p.242
 parameter   RX_DISPERR_SEQ_MATCH         = "TRUE";
 parameter   DEC_MCOMMA_DETECT            = "TRUE";
@@ -608,10 +607,10 @@ GTXE2_CHANNEL #(
     .TXDLY_CFG                                                  (TXDLY_CFG),
     .TXDLY_LCFG                                                 (TXDLY_LCFG),
     .TXDLY_TAP_CFG                                              (TXDLY_TAP_CFG),
-    .TXSYNC_MULTILANE                                           (TXSYNC_MULTILANE),
+/*    .TXSYNC_MULTILANE                                           (TXSYNC_MULTILANE),
     .TXSYNC_SKIP_DA                                             (TXSYNC_SKIP_DA),
     .TXSYNC_OVRD                                                (TXSYNC_OVRD),
-    .LOOPBACK_CFG                                               (LOOPBACK_CFG),
+    .LOOPBACK_CFG                                               (LOOPBACK_CFG),*/
 // TX Pattern Generator, ug476 p.147
     .RXPRBS_ERR_LOOPBACK                                        (RXPRBS_ERR_LOOPBACK),
 // TX Fabric Clock Output Control Attributes, ug476 p. 153
@@ -714,7 +713,7 @@ GTXE2_CHANNEL #(
     .RX_INT_DATAWIDTH                                           (RX_INT_DATAWIDTH),
     .ES_PMA_CFG                                                 (ES_PMA_CFG),
 // Pattern Checker Attributes, ug476 p.226
-    .RX_PRBS_ERR_CNT                                            (RX_PRBS_ERR_CNT),
+    //.RX_PRBS_ERR_CNT                                            (RX_PRBS_ERR_CNT),
 // RX Byte and Word Alignment Attributes, ug476 p.235
     .ALIGN_COMMA_WORD                                           (ALIGN_COMMA_WORD),
     .ALIGN_COMMA_ENABLE                                         (ALIGN_COMMA_ENABLE),
@@ -727,7 +726,7 @@ GTXE2_CHANNEL #(
     .RXSLIDE_MODE                                               (RXSLIDE_MODE),
     .RXSLIDE_AUTO_WAIT                                          (RXSLIDE_AUTO_WAIT),
     .RX_SIG_VALID_DLY                                           (RX_SIG_VALID_DLY),
-    .COMMA_ALIGN_LATENCY                                        (COMMA_ALIGN_LATENCY),
+    //.COMMA_ALIGN_LATENCY                                        (COMMA_ALIGN_LATENCY),
 // RX 8B/10B Decoder Attributes, ug476 p.242
     .RX_DISPERR_SEQ_MATCH                                       (RX_DISPERR_SEQ_MATCH),
     .DEC_MCOMMA_DETECT                                          (DEC_MCOMMA_DETECT),