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Elphel
x393_sata
Commits
ec00bd28
Commit
ec00bd28
authored
Sep 09, 2015
by
Alexey Grebenkin
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Plain Diff
Fixed most of vdt warnings
parent
9d34d274
Changes
24
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24 changed files
with
1083 additions
and
316 deletions
+1083
-316
.editor_defines
.editor_defines
+4
-0
com.elphel.vdt.iverilog.prefs
.settings/com.elphel.vdt.iverilog.prefs
+0
-1
oob_dev.v
device/oob_dev.v
+2
-0
sata_phy_dev.v
device/sata_phy_dev.v
+11
-12
axi_regs.v
dma/axi_regs.v
+1
-12
dma_adapter.v
dma/dma_adapter.v
+9
-6
dma_control.v
dma/dma_control.v
+12
-11
dma_regs.v
dma/dma_regs.v
+31
-34
sata_top.v
dma/sata_top.v
+9
-22
top.v
dma/top.v
+11
-51
command.v
host/command.v
+3
-3
gtx_10x8dec.v
host/gtx_10x8dec.v
+1
-1
gtx_comma_align.v
host/gtx_comma_align.v
+1
-1
gtx_elastic.v
host/gtx_elastic.v
+6
-5
gtx_wrap.v
host/gtx_wrap.v
+32
-25
link.v
host/link.v
+21
-22
oob.v
host/oob.v
+2
-2
sata_host.v
host/sata_host.v
+1
-3
sata_phy.v
host/sata_phy.v
+9
-4
transport.v
host/transport.v
+14
-16
tb_top.v
tb/tb_top.v
+18
-16
tb_top.sav
tb_top.sav
+797
-0
GTXE2_GPL.v
wrapper/GTXE2_GPL.v
+78
-54
gtxe2_channel_wrapper.v
wrapper/gtxe2_channel_wrapper.v
+10
-15
No files found.
.editor_defines
0 → 100644
View file @
ec00bd28
`define SIMULATION 1
`define CHECKERS_ENABLED 1
`define OPEN_SOURCE_ONLY 1
`define PRELOAD_BRAMS
\ No newline at end of file
.settings/com.elphel.vdt.iverilog.prefs
View file @
ec00bd28
...
...
@@ -3,7 +3,6 @@ eclipse.preferences.version=1
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_122_IVerilogOther=-D OPEN_SOURCE_ONLY
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
...
...
device/oob_dev.v
View file @
ec00bd28
...
...
@@ -121,6 +121,8 @@ end
reg
[
9
:
0
]
txelecidle_cnt
;
wire
aligndet
;
wire
syncdet
;
assign
aligndet
=
~|
(
rxdata
^
{
8'b01111011
,
8'b01001010
,
8'b01001010
,
8'b10111100
}
)
&
~|
(
rxcharisk
^
4'h1
)
;
// {D27.3, D10.2, D10.2, K28.5}
assign
syncdet
=
~|
(
rxdata
^
{
8'b10110101
,
8'b10110101
,
8'b10010101
,
8'b01111100
}
)
&
~|
(
rxcharisk
^
4'h1
)
;
// {D21.5, D21.5, D21.4, K28.3}
...
...
device/sata_phy_dev.v
View file @
ec00bd28
...
...
@@ -52,9 +52,6 @@ module sata_phy_dev #(
input
wire
[
3
:
0
]
ll_charisk_in
)
;
parameter
CHIPSCOPE
=
"FALSE"
;
wire
txcomfinish
;
wire
[
31
:
0
]
txdata
;
wire
[
31
:
0
]
txdata_oob
;
wire
[
3
:
0
]
txcharisk
;
...
...
@@ -92,7 +89,7 @@ assign txdata = phy_ready ? ll_data_in : txdata_oob;
assign
txcharisk
=
phy_ready
?
ll_charisk_in
:
txcharisk_oob
;
assign
ll_err_out
=
4'h0
;
assign
ll_charisk_out
=
rxcharisk
[
3
:
0
]
;
assign
ll_data_out
=
rxdata
;
assign
ll_data_out
=
rxdata
[
31
:
0
]
;
oob_dev
oob_dev
(
...
...
@@ -164,7 +161,7 @@ localparam RXEYERESET_TIME = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + R
reg
[
6
:
0
]
rxeyereset_cnt
;
assign
rxeyereset_done
=
rxeyereset_cnt
==
RXEYERESET_TIME
;
always
@
(
posedge
gtrefclk
)
rxeyereset_cnt
<=
rxreset
?
3
'h0
:
rxeyereset_done
?
rxeyereset_cnt
:
rxeyereset_cnt
+
1'b1
;
rxeyereset_cnt
<=
rxreset
?
7
'h0
:
rxeyereset_done
?
rxeyereset_cnt
:
rxeyereset_cnt
+
1'b1
;
/*
* Resets
...
...
@@ -503,12 +500,12 @@ gtx_wrapper(
.
CPLLREFCLKLOST
()
,
.
CPLLREFCLKSEL
(
3'b001
)
,
.
CPLLRESET
(
cpllreset
)
,
.
GTRSVD
(
1'b0
)
,
.
PCSRSVDIN
(
1'b0
)
,
.
PCSRSVDIN2
(
1
'b0
)
,
.
PMARSVDIN
(
1
'b0
)
,
.
PMARSVDIN2
(
1
'b0
)
,
.
TSTIN
(
1
'b1
)
,
.
GTRSVD
(
1
6
'b0
)
,
.
PCSRSVDIN
(
1
6
'b0
)
,
.
PCSRSVDIN2
(
5
'b0
)
,
.
PMARSVDIN
(
5
'b0
)
,
.
PMARSVDIN2
(
5
'b0
)
,
.
TSTIN
(
20
'b1
)
,
.
TSTOUT
()
,
.
CLKRSVD
(
4'b0000
)
,
.
GTGREFCLK
(
1'b0
)
,
...
...
@@ -714,7 +711,7 @@ gtx_wrapper(
.
TXPCSRESET
(
txpcsreset
)
,
.
TXPMARESET
(
1'b0
)
,
.
TXRESETDONE
(
txresetdone
)
,
.
TXCOMFINISH
(
txcomfinish
)
,
.
TXCOMFINISH
()
,
.
TXCOMINIT
(
txcominit
)
,
.
TXCOMSAS
(
1'b0
)
,
.
TXCOMWAKE
(
txcomwake
)
,
...
...
@@ -740,6 +737,8 @@ assign rxchariscomma = twobytes_shift ? {rxchariscomma_gtx[7:4], rxchariscomm
assign
rxdisperr
=
twobytes_shift
?
{
rxdisperr_gtx
[
7
:
4
]
,
rxdisperr_gtx
[
1
:
0
]
,
rxdisperr_gtx
[
3
:
2
]
}
:
rxdisperr_gtx
;
assign
rxnotintable
=
twobytes_shift
?
{
rxnotintable_gtx
[
7
:
4
]
,
rxnotintable_gtx
[
1
:
0
]
,
rxnotintable_gtx
[
3
:
2
]
}
:
rxnotintable_gtx
;
assign
ll_err_out
=
rxdisperr
[
3
:
0
]
|
rxnotintable
[
3
:
0
]
;
/*
* Interfaces
*/
...
...
dma/axi_regs.v
View file @
ec00bd28
...
...
@@ -20,10 +20,7 @@
*******************************************************************************/
//`include "axibram_read.v"
//`include "axibram_write.v"
module
axi_regs
#(
parameter
REGISTERS_CNT
=
20
)
(
module
axi_regs
(
input
wire
ACLK
,
// AXI PS Master GP1 Clock , input
input
wire
ARESETN
,
// AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address
...
...
@@ -31,13 +28,9 @@ module axi_regs #(
input
wire
ARVALID
,
// AXI PS Master GP1 ARVALID, output
output
wire
ARREADY
,
// AXI PS Master GP1 ARREADY, input
input
wire
[
11
:
0
]
ARID
,
// AXI PS Master GP1 ARID[11:0], output
input
wire
[
1
:
0
]
ARLOCK
,
// AXI PS Master GP1 ARLOCK[1:0], output
input
wire
[
3
:
0
]
ARCACHE
,
// AXI PS Master GP1 ARCACHE[3:0], output
input
wire
[
2
:
0
]
ARPROT
,
// AXI PS Master GP1 ARPROT[2:0], output
input
wire
[
3
:
0
]
ARLEN
,
// AXI PS Master GP1 ARLEN[3:0], output
input
wire
[
1
:
0
]
ARSIZE
,
// AXI PS Master GP1 ARSIZE[1:0], output
input
wire
[
1
:
0
]
ARBURST
,
// AXI PS Master GP1 ARBURST[1:0], output
input
wire
[
3
:
0
]
ARQOS
,
// AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data
output
wire
[
31
:
0
]
RDATA
,
// AXI PS Master GP1 RDATA[31:0], input
output
wire
RVALID
,
// AXI PS Master GP1 RVALID, input
...
...
@@ -50,13 +43,9 @@ module axi_regs #(
input
wire
AWVALID
,
// AXI PS Master GP1 AWVALID, output
output
wire
AWREADY
,
// AXI PS Master GP1 AWREADY, input
input
wire
[
11
:
0
]
AWID
,
// AXI PS Master GP1 AWID[11:0], output
input
wire
[
1
:
0
]
AWLOCK
,
// AXI PS Master GP1 AWLOCK[1:0], output
input
wire
[
3
:
0
]
AWCACHE
,
// AXI PS Master GP1 AWCACHE[3:0], output
input
wire
[
2
:
0
]
AWPROT
,
// AXI PS Master GP1 AWPROT[2:0], output
input
wire
[
3
:
0
]
AWLEN
,
// AXI PS Master GP1 AWLEN[3:0], outpu:t
input
wire
[
1
:
0
]
AWSIZE
,
// AXI PS Master GP1 AWSIZE[1:0], output
input
wire
[
1
:
0
]
AWBURST
,
// AXI PS Master GP1 AWBURST[1:0], output
input
wire
[
3
:
0
]
AWQOS
,
// AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data
input
wire
[
31
:
0
]
WDATA
,
// AXI PS Master GP1 WDATA[31:0], output
input
wire
WVALID
,
// AXI PS Master GP1 WVALID, output
...
...
dma/dma_adapter.v
View file @
ec00bd28
...
...
@@ -96,7 +96,7 @@ assign rd_start = set_busy & ~cmd_type;
always
@
(
posedge
clk
)
begin
cmd_type_r
<=
rst
?
1'b0
:
set_busy
?
cmd_type
:
cmd_type_r
;
cmd_addr_r
<=
rst
?
1'b0
:
set_busy
?
cmd_addr
:
cmd_addr_r
;
cmd_addr_r
<=
rst
?
25'b0
:
set_busy
?
cmd_addr
[
31
:
7
]
:
cmd_addr_r
[
31
:
7
]
;
cmd_busy_r
<=
(
cmd_busy_r
|
set_busy
)
&
~
rst
&
~
clr_busy
;
end
...
...
@@ -126,18 +126,21 @@ reg [3:0] rdwr_state;
localparam
READ_IDLE
=
0
;
localparam
READ_WAIT_ADDR
=
3
;
localparam
READ_DATA
=
4
;
reg
rd_reset_page
;
wire
rd_reset_page
;
reg
rd_next_page
;
reg
rd_data
;
wire
[
63
:
0
]
rd_data
;
reg
[
6
:
0
]
rd_data_count
;
reg
rd_en
;
wire
rd_stop
;
wire
rd_cnt_to_pull
;
wire
[
6
:
0
]
rd_cnt_to_pull
;
assign
rd_cnt_to_pull
=
7'hf
;
assign
rd_stop
=
rd_ack_in
&
rd_data_count
==
rd_cnt_to_pull
;
assign
rd_reset_page
=
1'b0
;
assign
rd_data
=
buf_rdata
;
assign
rd_val_out
=
rd_en
;
assign
rd_data_out
=
rd_data
;
always
@
(
posedge
clk
)
...
...
@@ -296,7 +299,7 @@ localparam MEMBR_SIZE = 5;
localparam
MEMBR_LOADDR
=
6
;
localparam
MEMBR_CTRL
=
7
;
reg
[
3
2
:
0
]
membr_data
;
reg
[
3
1
:
0
]
membr_data
;
reg
[
15
:
0
]
membr_addr
;
reg
membr_start
;
reg
membr_done
;
...
...
@@ -374,7 +377,7 @@ always @ (posedge clk)
end
MEMBR_LOADDR:
begin
membr_data
<=
cmd_addr_r
;
membr_data
<=
{
7'h0
,
cmd_addr_r
[
31
:
7
]
}
;
membr_addr
<=
16'h202
;
membr_start
<=
membr_inprocess
?
1'b0
:
1'b1
;
membr_setup
<=
membr_inprocess
|
membr_setup
?
1'b0
:
1'b1
;
...
...
dma/dma_control.v
View file @
ec00bd28
...
...
@@ -96,7 +96,7 @@ always @ (posedge sclk)
// drive iface signals
assign
host_new_cmd
=
host_issued_set
;
assign
host_cmd_type
=
dma_type
;
assign
host_cmd_type
=
{
1'b0
,
dma_type
}
;
assign
host_sector_count
=
sector_cnt
;
assign
host_sector_addr
=
lba
;
...
...
@@ -134,6 +134,7 @@ begin
state_wait_done
<=
(
state_wait_done
|
set_wait_done
)
&
~
clr_wait_done
&
~
rst
;
end
assign
adp_val_sclk
=
set_wait_busy
;
// conrol signals resync
reg
adp_val_r
;
reg
adp_val_rr
;
...
...
@@ -143,7 +144,7 @@ begin
adp_val_rr
<=
adp_val_r
;
end
assign
adp_addr
=
current_addr
;
assign
adp_addr
=
current_addr
[
31
:
7
]
;
assign
adp_type
=
current_type
;
assign
adp_val
=
adp_val_rr
;
...
...
@@ -208,9 +209,9 @@ assign last_data = (sector_cnt == quarter_sector_cnt[33:2] + 1'b1) & (&quarter_
// calculate outgoing address
// increment every transaction to adapter
always
@
(
posedge
sclk
)
current_addr
<=
~
set_wait_busy
?
current_addr
:
state_idle
?
mem_address
:
// new dma request
current_addr
+
1'b1
;
// same dma request, next 128 bytes
current_addr
<=
~
set_wait_busy
?
current_addr
[
31
:
7
]
:
state_idle
?
mem_address
[
31
:
7
]
:
// new dma request
current_addr
[
31
:
7
]
+
1'b1
;
// same dma request, next 128 bytes
always
@
(
posedge
sclk
)
current_type
<=
~
set_wait_busy
?
current_type
:
...
...
@@ -262,13 +263,13 @@ end
// write address -> sclk (rd) domain to compare
always
@
(
posedge
sclk
)
begin
from_wr_addr_gr_r
<=
rst
?
9'h0
:
from_wr_addr
;
from_wr_addr_gr_r
<=
rst
?
9'h0
:
from_wr_addr
_gr
;
from_wr_addr_gr_rr
<=
rst
?
9'h0
:
from_wr_addr_gr_r
;
end
// read address -> hclk (wr) domain to compare
always
@
(
posedge
hclk
)
begin
from_rd_addr_gr_r
<=
rst
?
10'h0
:
from_rd_addr
;
from_rd_addr_gr_r
<=
rst
?
10'h0
:
from_rd_addr
_gr
;
from_rd_addr_gr_rr
<=
rst
?
10'h0
:
from_rd_addr_gr_r
;
end
// translate resynced write address into ordinary (non-gray) address
...
...
@@ -367,13 +368,13 @@ end
// write address -> hclk (rd) domain to compare
always
@
(
posedge
hclk
)
begin
to_wr_addr_gr_r
<=
rst
?
10'h0
:
to_wr_addr
;
to_wr_addr_gr_r
<=
rst
?
10'h0
:
to_wr_addr
_gr
;
to_wr_addr_gr_rr
<=
rst
?
10'h0
:
to_wr_addr_gr_r
;
end
// read address -> sclk (wr) domain to compare
always
@
(
posedge
sclk
)
begin
to_rd_addr_gr_r
<=
rst
?
9'h0
:
to_rd_addr
;
to_rd_addr_gr_r
<=
rst
?
9'h0
:
to_rd_addr
_gr
;
to_rd_addr_gr_rr
<=
rst
?
9'h0
:
to_rd_addr_gr_r
;
end
// translate resynced write address into ordinary (non-gray) address
...
...
@@ -400,8 +401,8 @@ endgenerate
// to_wr_addr_r - write address some hclk ticks ago
// => we can say if the fifo have the possibility to be empty
// since actual to_wr_addr could only be incremented
assign
to_full
=
{
to_wr_addr
,
1'b0
}
==
to_rd_addr_r
+
1'b1
;
assign
to_empty
=
{
to_wr_addr_r
,
1'b0
}
==
to_rd_addr
;
// overflows must never be achieved
assign
to_full
=
to_wr_addr
==
{
to_rd_addr_r
,
1'b0
}
+
1'b1
;
assign
to_empty
=
to_wr_addr_r
==
{
to_rd_addr
,
1'b0
}
;
// overflows must never be achieved
// calculate bus responses in order to fifo status:
assign
to_val
=
~
to_empty
;
assign
in_val
=
~
in_busy
&
~
to_full
;
...
...
dma/dma_regs.v
View file @
ec00bd28
...
...
@@ -18,10 +18,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
module
dma_regs
#(
parameter
REGISTERS_CNT
=
20
)
(
module
dma_regs
(
input
wire
rst
,
input
wire
ACLK
,
input
wire
sclk
,
...
...
@@ -190,27 +187,27 @@ assign sh_autoact_val = bram_wen & (bram_waddr[7:0] == 8'hc);
assign
sh_inter_val
=
bram_wen
&
(
bram_waddr
[
7
:
0
]
==
8'hd
)
;
assign
sh_dir_val
=
bram_wen
&
(
bram_waddr
[
7
:
0
]
==
8'he
)
;
assign
cmd_val_out
=
bram_wen
&
(
bram_waddr
[
7
:
0
]
==
8'hf
)
;
assign
sh_port
=
bram_wen
&
(
bram_waddr
[
7
:
0
]
==
8'h13
)
;
assign
sh_port
_val
=
bram_wen
&
(
bram_waddr
[
7
:
0
]
==
8'h13
)
;
assign
sh_dma_cnt_val
=
bram_wen
&
(
bram_waddr
[
7
:
0
]
==
8'h14
)
;
assign
sh_notif_val
=
bram_wen
&
(
bram_waddr
[
7
:
0
]
==
8'h15
)
;
assign
sh_data
=
wdata
;
assign
sh_feature
=
wdata
;
assign
sh_lba_lo
=
wdata
;
assign
sh_lba_hi
=
wdata
;
assign
sh_count
=
wdata
;
assign
sh_command
=
wdata
;
assign
sh_dev
=
wdata
;
assign
sh_control
=
wdata
;
assign
sh_feature
=
wdata
[
15
:
0
]
;
assign
sh_lba_lo
=
wdata
[
23
:
0
]
;
assign
sh_lba_hi
=
wdata
[
23
:
0
]
;
assign
sh_count
=
wdata
[
15
:
0
]
;
assign
sh_command
=
wdata
[
7
:
0
]
;
assign
sh_dev
=
wdata
[
7
:
0
]
;
assign
sh_control
=
wdata
[
7
:
0
]
;
assign
sh_dma_id_lo
=
wdata
;
assign
sh_dma_id_hi
=
wdata
;
assign
sh_buf_off
=
wdata
;
assign
sh_tran_cnt
=
wdata
;
assign
sh_autoact
=
wdata
;
assign
sh_inter
=
wdata
;
assign
sh_dir
=
wdata
;
assign
sh_port
=
wdata
;
assign
sh_notif
=
wdata
;
assign
sh_tran_cnt
=
wdata
[
15
:
0
]
;
assign
sh_autoact
=
wdata
[
0
]
;
assign
sh_inter
=
wdata
[
0
]
;
assign
sh_dir
=
wdata
[
0
]
;
assign
sh_port
=
wdata
[
3
:
0
]
;
assign
sh_notif
=
wdata
[
0
]
;
assign
sh_dma_cnt
=
wdata
;
assign
cmd_out
=
wdata
;
...
...
@@ -231,27 +228,27 @@ always @ (posedge ACLK) begin
bram_raddr_r
==
8'hf4
?
reg10
:
bram_raddr_r
==
8'hf5
?
reg14
:
bram_raddr_r
==
8'h00
?
sh_data_in
:
bram_raddr_r
==
8'h01
?
sh_feature_in
:
bram_raddr_r
==
8'h02
?
sh_lba_in
[
23
:
0
]
:
bram_raddr_r
==
8'h03
?
sh_lba_in
[
47
:
24
]
:
bram_raddr_r
==
8'h04
?
sh_count_in
:
bram_raddr_r
==
8'h05
?
sh_command_in
:
bram_raddr_r
==
8'h06
?
sh_dev_in
:
bram_raddr_r
==
8'h07
?
sh_control_in
:
bram_raddr_r
==
8'h01
?
{
16'h0
,
sh_feature_in
}
:
bram_raddr_r
==
8'h02
?
{
8'h0
,
sh_lba_in
[
23
:
0
]
}
:
bram_raddr_r
==
8'h03
?
{
8'h0
,
sh_lba_in
[
47
:
24
]
}
:
bram_raddr_r
==
8'h04
?
{
16'h0
,
sh_count_in
}
:
bram_raddr_r
==
8'h05
?
{
24'h0
,
sh_command_in
}
:
bram_raddr_r
==
8'h06
?
{
24'h0
,
sh_dev_in
}
:
bram_raddr_r
==
8'h07
?
{
24'h0
,
sh_control_in
}
:
bram_raddr_r
==
8'h08
?
sh_dma_id_in
[
31
:
0
]
:
bram_raddr_r
==
8'h09
?
sh_dma_id_in
[
63
:
32
]
:
bram_raddr_r
==
8'h0a
?
sh_dma_off_in
:
bram_raddr_r
==
8'h0b
?
sh_tran_cnt_in
:
// Transfer Count
bram_raddr_r
==
8'h0c
?
sh_autoact_in
:
bram_raddr_r
==
8'h0d
?
sh_inter_in
:
bram_raddr_r
==
8'h0e
?
sh_dir_in
:
bram_raddr_r
==
8'h0b
?
{
16'h0
,
sh_tran_cnt_in
}
:
// Transfer Count
bram_raddr_r
==
8'h0c
?
{
31'h0
,
sh_autoact_in
}
:
bram_raddr_r
==
8'h0d
?
{
31'h0
,
sh_inter_in
}
:
bram_raddr_r
==
8'h0e
?
{
31'h0
,
sh_dir_in
}
:
bram_raddr_r
==
8'h0f
?
cmd_in
:
bram_raddr_r
==
8'h10
?
sh_err_in
:
bram_raddr_r
==
8'h11
?
sh_status_in
:
bram_raddr_r
==
8'h12
?
sh_estatus_in
:
// E_Status
bram_raddr_r
==
8'h13
?
sh_port_in
:
bram_raddr_r
==
8'h10
?
{
24'h0
,
sh_err_in
}
:
bram_raddr_r
==
8'h11
?
{
24'h0
,
sh_status_in
}
:
bram_raddr_r
==
8'h12
?
{
24'h0
,
sh_estatus_in
}
:
// E_Status
bram_raddr_r
==
8'h13
?
{
28'h0
,
sh_port_in
}
:
bram_raddr_r
==
8'h14
?
sh_dma_cnt_in
:
bram_raddr_r
==
8'h15
?
sh_notif_in
:
bram_raddr_r
==
8'h15
?
{
31'h0
,
sh_notif_in
}
:
32'hd34db33f
;
end
assign
bram_rdata
=
bram_rdata_r
;
...
...
dma/sata_top.v
View file @
ec00bd28
...
...
@@ -42,13 +42,9 @@
input
wire
ARVALID
,
// AXI PS Master GP1 ARVALID, output
output
wire
ARREADY
,
// AXI PS Master GP1 ARREADY, input
input
wire
[
11
:
0
]
ARID
,
// AXI PS Master GP1 ARID[11:0], output
input
wire
[
1
:
0
]
ARLOCK
,
// AXI PS Master GP1 ARLOCK[1:0], output
input
wire
[
3
:
0
]
ARCACHE
,
// AXI PS Master GP1 ARCACHE[3:0], output
input
wire
[
2
:
0
]
ARPROT
,
// AXI PS Master GP1 ARPROT[2:0], output
input
wire
[
3
:
0
]
ARLEN
,
// AXI PS Master GP1 ARLEN[3:0], output
input
wire
[
1
:
0
]
ARSIZE
,
// AXI PS Master GP1 ARSIZE[1:0], output
input
wire
[
1
:
0
]
ARBURST
,
// AXI PS Master GP1 ARBURST[1:0], output
input
wire
[
3
:
0
]
ARQOS
,
// AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data
output
wire
[
31
:
0
]
RDATA
,
// AXI PS Master GP1 RDATA[31:0], input
output
wire
RVALID
,
// AXI PS Master GP1 RVALID, input
...
...
@@ -61,13 +57,9 @@
input
wire
AWVALID
,
// AXI PS Master GP1 AWVALID, output
output
wire
AWREADY
,
// AXI PS Master GP1 AWREADY, input
input
wire
[
11
:
0
]
AWID
,
// AXI PS Master GP1 AWID[11:0], output
input
wire
[
1
:
0
]
AWLOCK
,
// AXI PS Master GP1 AWLOCK[1:0], output
input
wire
[
3
:
0
]
AWCACHE
,
// AXI PS Master GP1 AWCACHE[3:0], output
input
wire
[
2
:
0
]
AWPROT
,
// AXI PS Master GP1 AWPROT[2:0], output
input
wire
[
3
:
0
]
AWLEN
,
// AXI PS Master GP1 AWLEN[3:0], outpu:t
input
wire
[
1
:
0
]
AWSIZE
,
// AXI PS Master GP1 AWSIZE[1:0], output
input
wire
[
1
:
0
]
AWBURST
,
// AXI PS Master GP1 AWBURST[1:0], output
input
wire
[
3
:
0
]
AWQOS
,
// AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data
input
wire
[
31
:
0
]
WDATA
,
// AXI PS Master GP1 WDATA[31:0], output
input
wire
WVALID
,
// AXI PS Master GP1 WVALID, output
...
...
@@ -141,8 +133,8 @@
*/
output
wire
TXN
,
output
wire
TXP
,
output
wire
RXN
,
output
wire
RXP
,
input
wire
RXN
,
input
wire
RXP
,
input
wire
EXTCLK_P
,
input
wire
EXTCLK_N
...
...
@@ -288,6 +280,9 @@ wire rdata_done; // = membridge.is_last_in_page & membridge.afi_rread
//assign rst = ARESETN;
// TODO
assign
hclk
=
ACLK
;
axi_regs
axi_regs
(
// axi iface
...
...
@@ -297,13 +292,9 @@ axi_regs axi_regs(
.
ARVALID
(
ARVALID
)
,
.
ARREADY
(
ARREADY
)
,
.
ARID
(
ARID
)
,
.
ARLOCK
(
ARLOCK
)
,
.
ARCACHE
(
ARCACHE
)
,
.
ARPROT
(
ARPROT
)
,
.
ARLEN
(
ARLEN
)
,
.
ARSIZE
(
ARSIZE
)
,
.
ARBURST
(
ARBURST
)
,
.
ARQOS
(
ARQOS
)
,
.
RDATA
(
RDATA
)
,
.
RVALID
(
RVALID
)
,
.
RREADY
(
RREADY
)
,
...
...
@@ -314,13 +305,9 @@ axi_regs axi_regs(
.
AWVALID
(
AWVALID
)
,
.
AWREADY
(
AWREADY
)
,
.
AWID
(
AWID
)
,
.
AWLOCK
(
AWLOCK
)
,
.
AWCACHE
(
AWCACHE
)
,
.
AWPROT
(
AWPROT
)
,
.
AWLEN
(
AWLEN
)
,
.
AWSIZE
(
AWSIZE
)
,
.
AWBURST
(
AWBURST
)
,
.
AWQOS
(
AWQOS
)
,
.
WDATA
(
WDATA
)
,
.
WVALID
(
WVALID
)
,
.
WREADY
(
WREADY
)
,
...
...
@@ -350,7 +337,7 @@ dma_regs dma_regs(
.
ACLK
(
ACLK
)
,
.
sclk
(
sclk
)
,
// control iface
.
mem_address
(
mem_address
)
,
.
mem_address
(
mem_address
[
31
:
7
]
)
,
.
lba
(
lba
)
,
.
sector_cnt
(
sector_cnt
)
,
.
dma_type
(
dma_type
)
,
...
...
@@ -441,7 +428,7 @@ dma_control dma_control(
.
rst
(
sata_rst
)
,
// registers iface
.
mem_address
(
mem_address
)
,
.
mem_address
(
mem_address
[
31
:
7
]
)
,
.
lba
(
lba
)
,
.
sector_cnt
(
sector_cnt
)
,
.
dma_type
(
dma_type
)
,
...
...
@@ -450,7 +437,7 @@ dma_control dma_control(
// adapter command iface
.
adp_busy
(
adp_busy
)
,
.
adp_addr
(
adp_addr
)
,
.
adp_addr
(
adp_addr
[
31
:
7
]
)
,
.
adp_type
(
adp_type
)
,
.
adp_val
(
adp_val
)
,
...
...
@@ -490,7 +477,7 @@ dma_adapter dma_adapter(
// command iface
.
cmd_type
(
adp_type
)
,
.
cmd_val
(
adp_val
)
,
.
cmd_addr
(
adp_addr
)
,
.
cmd_addr
(
adp_addr
[
31
:
7
]
)
,
.
cmd_busy
(
adp_busy
)
,
// data iface
.
wr_data_in
(
to_data
)
,
...
...
dma/top.v
View file @
ec00bd28
...
...
@@ -23,10 +23,10 @@
* to make the final integration easier - just to make an instance of
* what is called now 'axi_regs' and connect it
*/
`include
"system_defines.vh"
//
`include "system_defines.vh"
//`include "sata_top.v"
module
top
#(
`include
"includes/x393_parameters.vh"
`include
"includes/x393_parameters.vh"
// SuppressThisWarning VEditor - partially used
)
(
// sata serial data iface
...
...
@@ -38,10 +38,8 @@ module top #(
input
wire
EXTCLK_P
,
input
wire
EXTCLK_N
)
;
parameter
REGISTERS_CNT
=
20
;
wire
[
32
*
REGISTERS_CNT
-
1
:
0
]
outmem
;
wire
clrstart
;
wire
axi_aclk0
;
wire
sclk
;
wire
sata_rst
;
wire
extrst
;
...
...
@@ -55,13 +53,9 @@ wire [31:0] ARADDR;
wire
ARVALID
;
wire
ARREADY
;
wire
[
11
:
0
]
ARID
;
wire
[
1
:
0
]
ARLOCK
;
wire
[
3
:
0
]
ARCACHE
;
wire
[
2
:
0
]
ARPROT
;
wire
[
3
:
0
]
ARLEN
;
wire
[
1
:
0
]
ARSIZE
;
wire
[
1
:
0
]
ARBURST
;
wire
[
3
:
0
]
ARQOS
;
wire
[
31
:
0
]
RDATA
;
wire
RVALID
;
wire
RREADY
;
...
...
@@ -72,13 +66,9 @@ wire [31:0] AWADDR;
wire
AWVALID
;
wire
AWREADY
;
wire
[
11
:
0
]
AWID
;
wire
[
1
:
0
]
AWLOCK
;
wire
[
3
:
0
]
AWCACHE
;
wire
[
2
:
0
]
AWPROT
;
wire
[
3
:
0
]
AWLEN
;
wire
[
1
:
0
]
AWSIZE
;
wire
[
1
:
0
]
AWBURST
;
wire
[
3
:
0
]
AWQOS
;
wire
[
31
:
0
]
WDATA
;
wire
WVALID
;
wire
WREADY
;
...
...
@@ -137,28 +127,6 @@ wire [ 7:0] afi0_rcount; // input[7:0]
wire
[
2
:
0
]
afi0_racount
;
// input[2:0]
wire
afi0_rdissuecap1en
;
// output
// send_dma
wire
[
7
:
0
]
cmd_ad
;
wire
cmd_stb
;
wire
[
7
:
0
]
status_ad
;
wire
status_rq
;
wire
status_start
;
wire
frame_start_chn
;
wire
next_page_chn
;
wire
cmd_wrmem
;
wire
page_ready_chn
;
wire
frame_done_chn
;
wire
[
15
:
0
]
line_unfinished_chn1
;
wire
suspend_chn1
;
wire
xfer_reset_page_rd
;
wire
buf_wpage_nxt
;
wire
buf_wr
;
wire
[
63
:
0
]
buf_wdata
;
wire
xfer_reset_page_wr
;
wire
buf_rpage_nxt
;
wire
buf_rd
;
wire
[
63
:
0
]
buf_rdata
;
assign
comb_rst
=~
frst
[
0
]
|
frst
[
1
]
;
always
@
(
posedge
comb_rst
or
posedge
axi_aclk0
)
begin
if
(
comb_rst
)
axi_rst_pre
<=
1'b1
;
...
...
@@ -191,13 +159,9 @@ sata_top sata_top(
.
ARVALID
(
ARVALID
)
,
.
ARREADY
(
ARREADY
)
,
.
ARID
(
ARID
)
,
.
ARLOCK
(
ARLOCK
)
,
.
ARCACHE
(
ARCACHE
)
,
.
ARPROT
(
ARPROT
)
,
.
ARLEN
(
ARLEN
)
,
.
ARSIZE
(
ARSIZE
)
,
.
ARBURST
(
ARBURST
)
,
.
ARQOS
(
ARQOS
)
,
// AXI PS Master GP1: Read Data
.
RDATA
(
RDATA
)
,
.
RVALID
(
RVALID
)
,
...
...
@@ -210,13 +174,9 @@ sata_top sata_top(
.
AWVALID
(
AWVALID
)
,
.
AWREADY
(
AWREADY
)
,
.
AWID
(
AWID
)
,
.
AWLOCK
(
AWLOCK
)
,
.
AWCACHE
(
AWCACHE
)
,
.
AWPROT
(
AWPROT
)
,
.
AWLEN
(
AWLEN
)
,
.
AWSIZE
(
AWSIZE
)
,
.
AWBURST
(
AWBURST
)
,
.
AWQOS
(
AWQOS
)
,
// AXI PS Master GP1: Write Data
.
WDATA
(
WDATA
)
,
.
WVALID
(
WVALID
)
,
...
...
@@ -615,13 +575,13 @@ PS7 ps7_i (
.
MAXIGP1ARVALID
(
ARVALID
)
,
// AXI PS Master GP1 ARVALID, output
.
MAXIGP1ARREADY
(
ARREADY
)
,
// AXI PS Master GP1 ARREADY, input
.
MAXIGP1ARID
(
ARID
)
,
// AXI PS Master GP1 ARID[11:0], output
.
MAXIGP1ARLOCK
(
ARLOCK
)
,
// AXI PS Master GP1 ARLOCK[1:0], output
.
MAXIGP1ARCACHE
(
ARCACHE
)
,
// AXI PS Master GP1 ARCACHE[3:0], output
.
MAXIGP1ARPROT
(
ARPROT
)
,
// AXI PS Master GP1 ARPROT[2:0], output
.
MAXIGP1ARLOCK
()
,
// AXI PS Master GP1 ARLOCK[1:0], output
.
MAXIGP1ARCACHE
()
,
// AXI PS Master GP1 ARCACHE[3:0], output
.
MAXIGP1ARPROT
()
,
// AXI PS Master GP1 ARPROT[2:0], output
.
MAXIGP1ARLEN
(
ARLEN
)
,
// AXI PS Master GP1 ARLEN[3:0], output
.
MAXIGP1ARSIZE
(
ARSIZE
)
,
// AXI PS Master GP1 ARSIZE[1:0], output
.
MAXIGP1ARBURST
(
ARBURST
)
,
// AXI PS Master GP1 ARBURST[1:0], output
.
MAXIGP1ARQOS
(
ARQOS
)
,
// AXI PS Master GP1 ARQOS[3:0], output
.
MAXIGP1ARQOS
()
,
// AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data
.
MAXIGP1RDATA
(
RDATA
)
,
// AXI PS Master GP1 RDATA[31:0], input
.
MAXIGP1RVALID
(
RVALID
)
,
// AXI PS Master GP1 RVALID, input
...
...
@@ -634,13 +594,13 @@ PS7 ps7_i (
.
MAXIGP1AWVALID
(
AWVALID
)
,
// AXI PS Master GP1 AWVALID, output
.
MAXIGP1AWREADY
(
AWREADY
)
,
// AXI PS Master GP1 AWREADY, input
.
MAXIGP1AWID
(
AWID
)
,
// AXI PS Master GP1 AWID[11:0], output
.
MAXIGP1AWLOCK
(
AWLOCK
)
,
// AXI PS Master GP1 AWLOCK[1:0], output
.
MAXIGP1AWCACHE
(
AWCACHE
)
,
// AXI PS Master GP1 AWCACHE[3:0], output
.
MAXIGP1AWPROT
(
AWPROT
)
,
// AXI PS Master GP1 AWPROT[2:0], output
.
MAXIGP1AWLOCK
()
,
// AXI PS Master GP1 AWLOCK[1:0], output
.
MAXIGP1AWCACHE
()
,
// AXI PS Master GP1 AWCACHE[3:0], output
.
MAXIGP1AWPROT
()
,
// AXI PS Master GP1 AWPROT[2:0], output
.
MAXIGP1AWLEN
(
AWLEN
)
,
// AXI PS Master GP1 AWLEN[3:0], output
.
MAXIGP1AWSIZE
(
AWSIZE
)
,
// AXI PS Master GP1 AWSIZE[1:0], output
.
MAXIGP1AWBURST
(
AWBURST
)
,
// AXI PS Master GP1 AWBURST[1:0], output
.
MAXIGP1AWQOS
(
AWQOS
)
,
// AXI PS Master GP1 AWQOS[3:0], output
.
MAXIGP1AWQOS
()
,
// AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data
.
MAXIGP1WDATA
(
WDATA
)
,
// AXI PS Master GP1 WDATA[31:0], output
.
MAXIGP1WVALID
(
WVALID
)
,
// AXI PS Master GP1 WVALID, output
...
...
host/command.v
View file @
ec00bd28
...
...
@@ -185,7 +185,7 @@ begin
sh_inter
<=
rst
?
1'h0
:
al_sh_inter_val_in
?
al_sh_inter_in
:
tl_sh_inter_val_in
?
tl_sh_inter_in
:
sh_inter
;
sh_dir
<=
rst
?
1'h0
:
al_sh_dir_val_in
?
al_sh_dir_in
:
tl_sh_dir_val_in
?
tl_sh_dir_in
:
sh_dir
;
sh_dma_id
[
31
:
0
]
<=
rst
?
32'h0
:
al_sh_dma_id_lo_val_in
?
al_sh_dma_id_lo_in
:
tl_sh_dma_id_val_in
?
tl_sh_dma_id_in
[
31
:
0
]
:
sh_dma_id
[
31
:
0
]
;
sh_dma_id
[
63
:
32
]
<=
rst
?
32'h0
:
al_sh_dma_id_
lo
_val_in
?
al_sh_dma_id_hi_in
:
tl_sh_dma_id_val_in
?
tl_sh_dma_id_in
[
63
:
32
]
:
sh_dma_id
[
63
:
32
]
;
sh_dma_id
[
63
:
32
]
<=
rst
?
32'h0
:
al_sh_dma_id_
hi
_val_in
?
al_sh_dma_id_hi_in
:
tl_sh_dma_id_val_in
?
tl_sh_dma_id_in
[
63
:
32
]
:
sh_dma_id
[
63
:
32
]
;
sh_dma_off
<=
rst
?
32'h0
:
al_sh_buf_off_val_in
?
al_sh_buf_off_in
:
tl_sh_dma_off_val_in
?
tl_sh_dma_off_in
:
sh_dma_off
;
sh_dma_cnt
<=
rst
?
32'h0
:
al_sh_dma_cnt_val_in
?
al_sh_dma_cnt_in
:
tl_sh_dma_cnt_val_in
?
tl_sh_dma_cnt_in
:
sh_dma_cnt
;
sh_tran_cnt
<=
rst
?
16'h0
:
al_sh_tran_cnt_val_in
?
al_sh_tran_cnt_in
:
tl_sh_tran_cnt_val_in
?
tl_sh_tran_cnt_in
:
sh_tran_cnt
;
...
...
@@ -243,9 +243,9 @@ assign tl_data_last_out = 1'b0;
assign
tl_data_val_out
=
1'b0
;
always
@
(
posedge
clk
)
waddr
<=
rst
?
1'b0
:
~
tl_data_val_in
?
waddr
:
(
raddr
==
waddr
+
1'b1
)
?
waddr
:
waddr
+
1'b1
;
waddr
<=
rst
?
1
0
'b0
:
~
tl_data_val_in
?
waddr
:
(
raddr
==
waddr
+
1'b1
)
?
waddr
:
waddr
+
1'b1
;
always
@
(
posedge
clk
)
raddr
<=
rst
?
1'b0
:
al_sh_data_strobe_in
?
raddr
+
1'b1
:
raddr
;
raddr
<=
rst
?
1
0
'b0
:
al_sh_data_strobe_in
?
raddr
+
1'b1
:
raddr
;
ram_1kx32_1kx32
rbuf
(
.
rclk
(
clk
)
,
// clock for read port
...
...
host/gtx_10x8dec.v
View file @
ec00bd28
...
...
@@ -80,6 +80,7 @@ begin
end
// overall expected disparity when the table values would apper - disp0_r.
// disp1_rr shows expected after 0st byte would be considered
reg
correct_table_disp
;
wire
expected_disparity
;
wire
expected_disparity_interm
;
...
...
@@ -99,7 +100,6 @@ always @ (posedge clk)
disparity
<=
rst
?
1'b0
:
inv_disp1
^
inv_disp0
?
~
disparity
:
disparity
;
// to correct disparity if once an error occured
reg
correct_table_disp
;
always
@
(
posedge
clk
)
correct_table_disp
<=
rst
?
1'b0
:
disperror
[
1
]
?
~
correct_table_disp
:
correct_table_disp
;
...
...
host/gtx_comma_align.v
View file @
ec00bd28
...
...
@@ -71,7 +71,7 @@ reg [19:0] indata_r;
wire
[
38
:
0
]
window
;
always
@
(
posedge
clk
)
indata_r
<=
indata
;
assign
window
=
{
indata
,
indata_r
};
assign
window
=
{
indata
[
18
:
0
]
,
indata_r
};
// there is only 1 matched subwindow due to 20-bit comma's non-repetative pattern
wire
[
19
:
0
]
subwindow
[
19
:
0
]
;
...
...
host/gtx_elastic.v
View file @
ec00bd28
...
...
@@ -139,8 +139,8 @@ endgenerate
// wr_addr_r - write address some rclk ticks ago
// => we can say if the fifo have the possibility to be empty
// since actual wr_addr could only be incremented
assign
full
=
{
wr_addr
,
1'b0
}
==
rd_addr_r
+
1'b1
;
assign
empty
=
{
wr_addr_r
,
1'b0
}
==
rd_addr
;
assign
full
=
wr_addr
==
rd_addr_r
+
1'b1
;
assign
empty
=
wr_addr_r
==
rd_addr
;
assign
outram
=
ram
[
rd_addr
]
;
...
...
@@ -262,8 +262,6 @@ wire skip_write;
wire
rmv1_req_wclk
;
wire
rmv2_req_wclk
;
reg
next_prim_loaded
;
always
@
(
wclk
)
next_prim_loaded
<=
state_wait_next_p
;
wire
state_bypass_rmv
;
reg
state_wait1_align
;
...
...
@@ -285,6 +283,9 @@ wire clr_skip2_align;
wire
clr_wait_next_p
;
wire
clr_send_ack
;
always
@
(
wclk
)
next_prim_loaded
<=
state_wait_next_p
;
assign
state_bypass_rmv
=
~
state_wait1_align
&
~
state_skip1_align
&
~
state_wait2_align
&
~
state_skip2_align
&
~
state_wait_next_p
&
~
state_send_ack
;
assign
set_wait1_align
=
state_bypass_rmv
&
rmv1_req_wclk
&
~
rmv2_req_wclk
;
...
...
@@ -372,13 +373,13 @@ assign align_2nd = outram[15:0] == 16'h7B4A
&
outram
[
21
:
20
]
==
2'b00
;
// whole align primitive is the last thing we read from fifo
reg
read_align
;
wire
pause_read
;
always
@
(
posedge
rclk
)
read_align
<=
rst
?
1'b0
:
pause_read
|
align_1st
&
align_2nd
;
// just to alternate alignp's words, = 0 => 1st word, = 1 => 2nd word
reg
align_altern
;
wire
pause_read
;
// also pause when offset gets ok, but only 1st word of alignp is sent - need to send 2nd word
assign
pause_read
=
read_align
&
offset_less
&
fifo_stable
|
align_altern
;
...
...
host/gtx_wrap.v
View file @
ec00bd28
...
...
@@ -30,8 +30,7 @@ module gtx_wrap #(
parameter
RXCDRPHRESET_TIME
=
5'h1
,
parameter
RXCDRFREQRESET_TIME
=
5'h1
,
parameter
RXDFELPMRESET_TIME
=
7'hf
,
parameter
RXISCANRESET_TIME
=
5'h1
,
parameter
RXEYERESET_TIME
=
7'h25
parameter
RXISCANRESET_TIME
=
5'h1
)
(
output
wire
cplllock
,
...
...
@@ -74,7 +73,11 @@ module gtx_wrap #(
output
wire
[
DATA_BYTE_WIDTH
-
1
:
0
]
rxdisperr
)
;
// resets while PCS resets
wire
rxresetdone_gtx
;
wire
txresetdone_gtx
;
wire
wrap_rxreset_
;
wire
wrap_txreset_
;
// resets while PCS resets, active low
assign
wrap_rxreset_
=
rxuserrdy
&
rxresetdone_gtx
;
assign
wrap_txreset_
=
txuserrdy
&
txresetdone_gtx
;
...
...
@@ -149,6 +152,8 @@ if (DATA_BYTE_WIDTH == 4) begin
)
txdata_resynchro
(
.
rst
(
txreset
)
,