Fixed most of vdt warnings (ec00bd28) · Commits · Elphel / x393_sata

.editor_defines

0 → 100644

+4 −0

Original line number	Diff line number	Diff line
		`define SIMULATION 1
		`define CHECKERS_ENABLED 1
		`define OPEN_SOURCE_ONLY 1
		`define PRELOAD_BRAMS
		No newline at end of file

.settings/com.elphel.vdt.iverilog.prefs

+0 −1

Original line number	Diff line number	Diff line
		@@ -3,7 +3,6 @@ eclipse.preferences.version=1
		iverilog_101_TopModulesOther=glbl<-@\#\#@->
		iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
		iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
		iverilog_122_IVerilogOther=-D OPEN_SOURCE_ONLY
		iverilog_77_Param_Exe=/usr/local/bin/iverilog
		iverilog_78_VVP_Exe=/usr/local/bin/vvp
		iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave

device/oob_dev.v

+2 −0

Original line number	Diff line number	Diff line
		@@ -121,6 +121,8 @@ end

		reg [9:0] txelecidle_cnt;

		wire aligndet;
		wire syncdet;
		assign aligndet = ~\|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~\|(rxcharisk ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5}
		assign syncdet = ~\|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~\|(rxcharisk ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3}

device/sata_phy_dev.v

+11 −12

Original line number	Diff line number	Diff line
		@@ -52,9 +52,6 @@ module sata_phy_dev #(
		input wire [3:0] ll_charisk_in
		);

		parameter CHIPSCOPE = "FALSE";

		wire txcomfinish;
		wire [31:0] txdata;
		wire [31:0] txdata_oob;
		wire [3:0] txcharisk;
		@@ -92,7 +89,7 @@ assign txdata = phy_ready ? ll_data_in : txdata_oob;
		assign txcharisk = phy_ready ? ll_charisk_in : txcharisk_oob;
		assign ll_err_out = 4'h0;
		assign ll_charisk_out = rxcharisk[3:0];
		assign ll_data_out = rxdata;
		assign ll_data_out = rxdata[31:0];


		oob_dev oob_dev(
		@@ -164,7 +161,7 @@ localparam RXEYERESET_TIME = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + R
		reg [6:0] rxeyereset_cnt;
		assign rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME;
		always @ (posedge gtrefclk)
		rxeyereset_cnt <= rxreset ? 3'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1;
		rxeyereset_cnt <= rxreset ? 7'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1;

		/*
		* Resets
		@@ -503,12 +500,12 @@ gtx_wrapper(
		.CPLLREFCLKLOST (),
		.CPLLREFCLKSEL (3'b001),
		.CPLLRESET (cpllreset),
		.GTRSVD (1'b0),
		.PCSRSVDIN (1'b0),
		.PCSRSVDIN2 (1'b0),
		.PMARSVDIN (1'b0),
		.PMARSVDIN2 (1'b0),
		.TSTIN (1'b1),
		.GTRSVD (16'b0),
		.PCSRSVDIN (16'b0),
		.PCSRSVDIN2 (5'b0),
		.PMARSVDIN (5'b0),
		.PMARSVDIN2 (5'b0),
		.TSTIN (20'b1),
		.TSTOUT (),
		.CLKRSVD (4'b0000),
		.GTGREFCLK (1'b0),
		@@ -714,7 +711,7 @@ gtx_wrapper(
		.TXPCSRESET (txpcsreset),
		.TXPMARESET (1'b0),
		.TXRESETDONE (txresetdone),
		.TXCOMFINISH (txcomfinish),
		.TXCOMFINISH (),
		.TXCOMINIT (txcominit),
		.TXCOMSAS (1'b0),
		.TXCOMWAKE (txcomwake),
		@@ -740,6 +737,8 @@ assign rxchariscomma = twobytes_shift ? {rxchariscomma_gtx[7:4], rxchariscomm
		assign rxdisperr = twobytes_shift ? {rxdisperr_gtx[7:4] , rxdisperr_gtx[1:0] , rxdisperr_gtx[3:2] } : rxdisperr_gtx;
		assign rxnotintable = twobytes_shift ? {rxnotintable_gtx[7:4] , rxnotintable_gtx[1:0] , rxnotintable_gtx[3:2] } : rxnotintable_gtx;

		assign ll_err_out = rxdisperr[3:0] \| rxnotintable[3:0];

		/*
		* Interfaces
		*/

dma/axi_regs.v

+1 −12

Original line number	Diff line number	Diff line
		@@ -20,10 +20,7 @@
		*******************************************************************************/
		//`include "axibram_read.v"
		//`include "axibram_write.v"
		module axi_regs #(
		parameter REGISTERS_CNT = 20
		)
		(
		module axi_regs(
		input wire ACLK, // AXI PS Master GP1 Clock , input
		input wire ARESETN, // AXI PS Master GP1 Reset, output
		// AXI PS Master GP1: Read Address
		@@ -31,13 +28,9 @@ module axi_regs #(
		input wire ARVALID, // AXI PS Master GP1 ARVALID, output
		output wire ARREADY, // AXI PS Master GP1 ARREADY, input
		input wire [11:0] ARID, // AXI PS Master GP1 ARID[11:0], output
		input wire [1:0] ARLOCK, // AXI PS Master GP1 ARLOCK[1:0], output
		input wire [3:0] ARCACHE, // AXI PS Master GP1 ARCACHE[3:0], output
		input wire [2:0] ARPROT, // AXI PS Master GP1 ARPROT[2:0], output
		input wire [3:0] ARLEN, // AXI PS Master GP1 ARLEN[3:0], output
		input wire [1:0] ARSIZE, // AXI PS Master GP1 ARSIZE[1:0], output
		input wire [1:0] ARBURST, // AXI PS Master GP1 ARBURST[1:0], output
		input wire [3:0] ARQOS, // AXI PS Master GP1 ARQOS[3:0], output
		// AXI PS Master GP1: Read Data
		output wire [31:0] RDATA, // AXI PS Master GP1 RDATA[31:0], input
		output wire RVALID, // AXI PS Master GP1 RVALID, input
		@@ -50,13 +43,9 @@ module axi_regs #(
		input wire AWVALID, // AXI PS Master GP1 AWVALID, output
		output wire AWREADY, // AXI PS Master GP1 AWREADY, input
		input wire [11:0] AWID, // AXI PS Master GP1 AWID[11:0], output
		input wire [1:0] AWLOCK, // AXI PS Master GP1 AWLOCK[1:0], output
		input wire [3:0] AWCACHE, // AXI PS Master GP1 AWCACHE[3:0], output
		input wire [2:0] AWPROT, // AXI PS Master GP1 AWPROT[2:0], output
		input wire [3:0] AWLEN, // AXI PS Master GP1 AWLEN[3:0], outpu:t
		input wire [1:0] AWSIZE, // AXI PS Master GP1 AWSIZE[1:0], output
		input wire [1:0] AWBURST, // AXI PS Master GP1 AWBURST[1:0], output
		input wire [3:0] AWQOS, // AXI PS Master GP1 AWQOS[3:0], output
		// AXI PS Master GP1: Write Data
		input wire [31:0] WDATA, // AXI PS Master GP1 WDATA[31:0], output
		input wire WVALID, // AXI PS Master GP1 WVALID, output

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