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Andrey Filippov authored
chaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
1902d5ce
chaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
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.pydevproject | Loading commit data... | |
args | Loading commit data... | |
hargs | Loading commit data... | |
import_verilog_parameters.py | Loading commit data... | |
test_mcntrl.py | Loading commit data... | |
verilog_utils.py | Loading commit data... | |
vrlg.py | Loading commit data... | |
x393_axi_control_status.py | Loading commit data... | |
x393_mcntrl_adjust.py | Loading commit data... | |
x393_mcntrl_buffers.py | Loading commit data... | |
x393_mcntrl_tests.py | Loading commit data... | |
x393_mcntrl_timing.py | Loading commit data... | |
x393_mem.py | Loading commit data... | |
x393_pio_sequences.py | Loading commit data... | |
x393_utils.py | Loading commit data... |