Loading axi/cmprs_afi_mux.v +6 −6 Original line number Original line Diff line number Diff line Loading @@ -21,7 +21,7 @@ `timescale 1ns/1ps `timescale 1ns/1ps module cmprs_afi_mux#( module cmprs_afi_mux#( parameter CMPRS_AFIMUX_ADDR= 'h140, //TODO: assign valid adderss parameter CMPRS_AFIMUX_ADDR= 'h140, //TODO: assign valid address parameter CMPRS_AFIMUX_MASK= 'h3f0, parameter CMPRS_AFIMUX_MASK= 'h3f0, parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel) parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel) parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets Loading @@ -29,7 +29,7 @@ module cmprs_afi_mux#( parameter CMPRS_AFIMUX_STATUS_CNTRL= 'h4, // .. 'h7 parameter CMPRS_AFIMUX_STATUS_CNTRL= 'h4, // .. 'h7 parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid adderss parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid address parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26) parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26) parameter CMPRS_AFIMUX_CYCBITS = 3, parameter CMPRS_AFIMUX_CYCBITS = 3, parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used Loading @@ -45,7 +45,7 @@ module cmprs_afi_mux#( input status_start, // Acknowledge of the first status packet byte (address) input status_start, // Acknowledge of the first status packet byte (address) // compressor channel 0 // compressor channel 0 output fifo_rst0, // reset FIFO (set read adderss to write, reset count) output fifo_rst0, // reset FIFO (set read address to write, reset count) output fifo_ren0, output fifo_ren0, input [63:0] fifo_rdata0, input [63:0] fifo_rdata0, // input fifo_eof0, // single rclk pulse signalling EOF // input fifo_eof0, // single rclk pulse signalling EOF Loading @@ -54,7 +54,7 @@ module cmprs_afi_mux#( input [7:0] fifo_count0, // number of 32-byte chunks in FIFO input [7:0] fifo_count0, // number of 32-byte chunks in FIFO // compressor channel 1 // compressor channel 1 output fifo_rst1, // reset FIFO (set read adderss to write, reset count) output fifo_rst1, // reset FIFO (set read address to write, reset count) output fifo_ren1, output fifo_ren1, input [63:0] fifo_rdata1, input [63:0] fifo_rdata1, // input fifo_eof1, // single rclk pulse signalling EOF // input fifo_eof1, // single rclk pulse signalling EOF Loading @@ -63,7 +63,7 @@ module cmprs_afi_mux#( input [7:0] fifo_count1, // number of 32-byte chunks in FIFO input [7:0] fifo_count1, // number of 32-byte chunks in FIFO // compressor channel 2 // compressor channel 2 output fifo_rst2, // reset FIFO (set read adderss to write, reset count) output fifo_rst2, // reset FIFO (set read address to write, reset count) output fifo_ren2, output fifo_ren2, input [63:0] fifo_rdata2, input [63:0] fifo_rdata2, // input fifo_eof2, // single rclk pulse signalling EOF // input fifo_eof2, // single rclk pulse signalling EOF Loading @@ -72,7 +72,7 @@ module cmprs_afi_mux#( input [7:0] fifo_count2, // number of 32-byte chunks in FIFO input [7:0] fifo_count2, // number of 32-byte chunks in FIFO // compressor channel 3 // compressor channel 3 output fifo_rst3, // reset FIFO (set read adderss to write, reset count) output fifo_rst3, // reset FIFO (set read address to write, reset count) output fifo_ren3, output fifo_ren3, input [63:0] fifo_rdata3, input [63:0] fifo_rdata3, // input fifo_eof3, // single rclk pulse signalling EOF // input fifo_eof3, // single rclk pulse signalling EOF Loading axi/cmprs_afi_mux_ptr.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -99,7 +99,7 @@ module cmprs_afi_mux_ptr( (busy[2] && !busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value) (busy[2] && !busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value) if (busy[0] && !busy[1]) begin // first clock of busy if (busy[0] && !busy[1]) begin // first clock of busy // calculate full adderss for current AXI burst (valid 1 clk after busy) // calculate full address for current AXI burst (valid 1 clk after busy) chunk_addr <= ptr_ram[ptr_wa] + sa_len_ram[sa_len_ra]; chunk_addr <= ptr_ram[ptr_wa] + sa_len_ram[sa_len_ra]; chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; end end Loading axi/cmprs_afi_mux_status.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -25,7 +25,7 @@ `timescale 1ns/1ps `timescale 1ns/1ps module cmprs_afi_mux_status #( module cmprs_afi_mux_status #( parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid adderss parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid address parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26) parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26) parameter CMPRS_AFIMUX_CYCBITS = 3 parameter CMPRS_AFIMUX_CYCBITS = 3 ) ( ) ( Loading compressor_jp/cmprs_out_fifo.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -32,7 +32,7 @@ module cmprs_out_fifo( // rclk domain // rclk domain input rclk, input rclk, input rst_fifo, // reset FIFO (set read adderss to write, reset count) input rst_fifo, // reset FIFO (set read address to write, reset count) input ren, input ren, output [63:0] rdata, output [63:0] rdata, output eof, // single rclk pulse signalling EOF output eof, // single rclk pulse signalling EOF Loading compressor_jp/jp_channel.v +4 −4 Original line number Original line Diff line number Diff line Loading @@ -21,7 +21,7 @@ `timescale 1ns/1ps `timescale 1ns/1ps module jp_channel#( module jp_channel#( parameter CMPRS_ADDR= 'h120, //TODO: assign valid adderss parameter CMPRS_ADDR= 'h120, //TODO: assign valid address parameter CMPRS_MASK= 'h3f8, parameter CMPRS_MASK= 'h3f8, parameter CMPRS_CONTROL_REG= 0, parameter CMPRS_CONTROL_REG= 0, parameter CMPRS_STATUS_CNTRL= 1, parameter CMPRS_STATUS_CNTRL= 1, Loading @@ -29,7 +29,7 @@ module jp_channel#( parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_CORING_MODE= 4, parameter CMPRS_CORING_MODE= 4, parameter CMPRS_TABLES= 6, // 6..7 parameter CMPRS_TABLES= 6, // 6..7 parameter CMPRS_STATUS_REG_ADDR= 'h10, //TODO: assign valid adderss parameter CMPRS_STATUS_REG_ADDR= 'h10, //TODO: assign valid address parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over) parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over) Loading Loading @@ -147,7 +147,7 @@ module jp_channel#( // Output interface to the AFI mux // Output interface to the AFI mux input hclk, input hclk, input fifo_rst, // reset FIFO (set read adderss to write, reset count) input fifo_rst, // reset FIFO (set read address to write, reset count) input fifo_ren, input fifo_ren, output [63:0] fifo_rdata, output [63:0] fifo_rdata, output fifo_eof, // single rclk pulse signalling EOF output fifo_eof, // single rclk pulse signalling EOF Loading Loading @@ -876,7 +876,7 @@ module jp_channel#( .eof_written_wclk (eof_written_xclk2xn), // output - AFI had transferred frame data to the system memory .eof_written_wclk (eof_written_xclk2xn), // output - AFI had transferred frame data to the system memory .rclk (hclk), // input - AFI clock .rclk (hclk), // input - AFI clock // AFI clock domain // AFI clock domain .rst_fifo (fifo_rst), // input - reset FIFO (set read adderss to write, reset count) .rst_fifo (fifo_rst), // input - reset FIFO (set read address to write, reset count) .ren (fifo_ren), // input - fifo read from AFI channel mux .ren (fifo_ren), // input - fifo read from AFI channel mux .rdata (fifo_rdata), // output[63:0] - data to AFI channel mux (latency == 2 from fifo_ren) .rdata (fifo_rdata), // output[63:0] - data to AFI channel mux (latency == 2 from fifo_ren) .eof (fifo_eof), // output single hclk pulse signalling EOF .eof (fifo_eof), // output single hclk pulse signalling EOF Loading Loading
axi/cmprs_afi_mux.v +6 −6 Original line number Original line Diff line number Diff line Loading @@ -21,7 +21,7 @@ `timescale 1ns/1ps `timescale 1ns/1ps module cmprs_afi_mux#( module cmprs_afi_mux#( parameter CMPRS_AFIMUX_ADDR= 'h140, //TODO: assign valid adderss parameter CMPRS_AFIMUX_ADDR= 'h140, //TODO: assign valid address parameter CMPRS_AFIMUX_MASK= 'h3f0, parameter CMPRS_AFIMUX_MASK= 'h3f0, parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel) parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel) parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets Loading @@ -29,7 +29,7 @@ module cmprs_afi_mux#( parameter CMPRS_AFIMUX_STATUS_CNTRL= 'h4, // .. 'h7 parameter CMPRS_AFIMUX_STATUS_CNTRL= 'h4, // .. 'h7 parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid adderss parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid address parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26) parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26) parameter CMPRS_AFIMUX_CYCBITS = 3, parameter CMPRS_AFIMUX_CYCBITS = 3, parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used Loading @@ -45,7 +45,7 @@ module cmprs_afi_mux#( input status_start, // Acknowledge of the first status packet byte (address) input status_start, // Acknowledge of the first status packet byte (address) // compressor channel 0 // compressor channel 0 output fifo_rst0, // reset FIFO (set read adderss to write, reset count) output fifo_rst0, // reset FIFO (set read address to write, reset count) output fifo_ren0, output fifo_ren0, input [63:0] fifo_rdata0, input [63:0] fifo_rdata0, // input fifo_eof0, // single rclk pulse signalling EOF // input fifo_eof0, // single rclk pulse signalling EOF Loading @@ -54,7 +54,7 @@ module cmprs_afi_mux#( input [7:0] fifo_count0, // number of 32-byte chunks in FIFO input [7:0] fifo_count0, // number of 32-byte chunks in FIFO // compressor channel 1 // compressor channel 1 output fifo_rst1, // reset FIFO (set read adderss to write, reset count) output fifo_rst1, // reset FIFO (set read address to write, reset count) output fifo_ren1, output fifo_ren1, input [63:0] fifo_rdata1, input [63:0] fifo_rdata1, // input fifo_eof1, // single rclk pulse signalling EOF // input fifo_eof1, // single rclk pulse signalling EOF Loading @@ -63,7 +63,7 @@ module cmprs_afi_mux#( input [7:0] fifo_count1, // number of 32-byte chunks in FIFO input [7:0] fifo_count1, // number of 32-byte chunks in FIFO // compressor channel 2 // compressor channel 2 output fifo_rst2, // reset FIFO (set read adderss to write, reset count) output fifo_rst2, // reset FIFO (set read address to write, reset count) output fifo_ren2, output fifo_ren2, input [63:0] fifo_rdata2, input [63:0] fifo_rdata2, // input fifo_eof2, // single rclk pulse signalling EOF // input fifo_eof2, // single rclk pulse signalling EOF Loading @@ -72,7 +72,7 @@ module cmprs_afi_mux#( input [7:0] fifo_count2, // number of 32-byte chunks in FIFO input [7:0] fifo_count2, // number of 32-byte chunks in FIFO // compressor channel 3 // compressor channel 3 output fifo_rst3, // reset FIFO (set read adderss to write, reset count) output fifo_rst3, // reset FIFO (set read address to write, reset count) output fifo_ren3, output fifo_ren3, input [63:0] fifo_rdata3, input [63:0] fifo_rdata3, // input fifo_eof3, // single rclk pulse signalling EOF // input fifo_eof3, // single rclk pulse signalling EOF Loading
axi/cmprs_afi_mux_ptr.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -99,7 +99,7 @@ module cmprs_afi_mux_ptr( (busy[2] && !busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value) (busy[2] && !busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value) if (busy[0] && !busy[1]) begin // first clock of busy if (busy[0] && !busy[1]) begin // first clock of busy // calculate full adderss for current AXI burst (valid 1 clk after busy) // calculate full address for current AXI burst (valid 1 clk after busy) chunk_addr <= ptr_ram[ptr_wa] + sa_len_ram[sa_len_ra]; chunk_addr <= ptr_ram[ptr_wa] + sa_len_ram[sa_len_ra]; chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; end end Loading
axi/cmprs_afi_mux_status.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -25,7 +25,7 @@ `timescale 1ns/1ps `timescale 1ns/1ps module cmprs_afi_mux_status #( module cmprs_afi_mux_status #( parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid adderss parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid address parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26) parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26) parameter CMPRS_AFIMUX_CYCBITS = 3 parameter CMPRS_AFIMUX_CYCBITS = 3 ) ( ) ( Loading
compressor_jp/cmprs_out_fifo.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -32,7 +32,7 @@ module cmprs_out_fifo( // rclk domain // rclk domain input rclk, input rclk, input rst_fifo, // reset FIFO (set read adderss to write, reset count) input rst_fifo, // reset FIFO (set read address to write, reset count) input ren, input ren, output [63:0] rdata, output [63:0] rdata, output eof, // single rclk pulse signalling EOF output eof, // single rclk pulse signalling EOF Loading
compressor_jp/jp_channel.v +4 −4 Original line number Original line Diff line number Diff line Loading @@ -21,7 +21,7 @@ `timescale 1ns/1ps `timescale 1ns/1ps module jp_channel#( module jp_channel#( parameter CMPRS_ADDR= 'h120, //TODO: assign valid adderss parameter CMPRS_ADDR= 'h120, //TODO: assign valid address parameter CMPRS_MASK= 'h3f8, parameter CMPRS_MASK= 'h3f8, parameter CMPRS_CONTROL_REG= 0, parameter CMPRS_CONTROL_REG= 0, parameter CMPRS_STATUS_CNTRL= 1, parameter CMPRS_STATUS_CNTRL= 1, Loading @@ -29,7 +29,7 @@ module jp_channel#( parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_CORING_MODE= 4, parameter CMPRS_CORING_MODE= 4, parameter CMPRS_TABLES= 6, // 6..7 parameter CMPRS_TABLES= 6, // 6..7 parameter CMPRS_STATUS_REG_ADDR= 'h10, //TODO: assign valid adderss parameter CMPRS_STATUS_REG_ADDR= 'h10, //TODO: assign valid address parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over) parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over) Loading Loading @@ -147,7 +147,7 @@ module jp_channel#( // Output interface to the AFI mux // Output interface to the AFI mux input hclk, input hclk, input fifo_rst, // reset FIFO (set read adderss to write, reset count) input fifo_rst, // reset FIFO (set read address to write, reset count) input fifo_ren, input fifo_ren, output [63:0] fifo_rdata, output [63:0] fifo_rdata, output fifo_eof, // single rclk pulse signalling EOF output fifo_eof, // single rclk pulse signalling EOF Loading Loading @@ -876,7 +876,7 @@ module jp_channel#( .eof_written_wclk (eof_written_xclk2xn), // output - AFI had transferred frame data to the system memory .eof_written_wclk (eof_written_xclk2xn), // output - AFI had transferred frame data to the system memory .rclk (hclk), // input - AFI clock .rclk (hclk), // input - AFI clock // AFI clock domain // AFI clock domain .rst_fifo (fifo_rst), // input - reset FIFO (set read adderss to write, reset count) .rst_fifo (fifo_rst), // input - reset FIFO (set read address to write, reset count) .ren (fifo_ren), // input - fifo read from AFI channel mux .ren (fifo_ren), // input - fifo read from AFI channel mux .rdata (fifo_rdata), // output[63:0] - data to AFI channel mux (latency == 2 from fifo_ren) .rdata (fifo_rdata), // output[63:0] - data to AFI channel mux (latency == 2 from fifo_ren) .eof (fifo_eof), // output single hclk pulse signalling EOF .eof (fifo_eof), // output single hclk pulse signalling EOF Loading
