ported camsync393.v from camsync.v that sends/receives timestamp over the sync cable

timing/timestamp_snapshot.v

+/*******************************************************************************
+ * Module: timestamp_snapshot
+ * Date:2015-07-03  
+ * Author: andrey     
+ * Description: Take timestamp snapshot and send the ts message over the 8-bit bus
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * timestamp_snapshot.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  timestamp_snapshot.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  timestamp_snapshot(
+    input                rst,
+    input                tclk, // clock that drives time counters
+    input         [31:0] sec,  // @tclk: current time seconds
+    input         [19:0] usec, // @tclk: current time microseconds
+    // snapshot destination clock domain
+    input                sclk,
+    input                snap,
+    output               pre_stb, // one clock pulse before sending TS data
+    output reg     [7:0] ts_data  // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
+);
+    wire         snap_tclk;
+    reg   [51:0] sec_usec_snap;
+    wire         pulse_busy;
+    reg          pulse_busy_r;
+    reg    [2:0] cntr;
+    reg          snd;
+
+    assign pre_stb = !pulse_busy && pulse_busy_r;
+    
+    always @ (posedge tclk) begin
+        if (snap_tclk) sec_usec_snap <= {usec,sec};
+    end
+    
+    always @(posedge rst or posedge sclk) begin
+        pulse_busy_r <= pulse_busy;
+        if      (rst)                          snd <= 0;
+        else if (!pulse_busy && pulse_busy_r)  snd <= 1;
+        else if ((&cntr) || snap)              snd <= 0;
+        
+        if (!snd) cntr <= 0;
+        else      cntr <=  cntr + 1;
+        
+        if (snd) case (cntr)
+            3'h0: ts_data <= sec_usec_snap[ 7: 0];
+            3'h1: ts_data <= sec_usec_snap[15: 8];
+            3'h2: ts_data <= sec_usec_snap[23:16];
+            3'h3: ts_data <= sec_usec_snap[31:24];
+            3'h4: ts_data <= sec_usec_snap[39:32];
+            3'h5: ts_data <= sec_usec_snap[47:40];
+            3'h6: ts_data <= {4'b0,sec_usec_snap[51:48]};
+            3'h7: ts_data <= 8'b0;
+        endcase
+        
+        
+    end
+    
+    pulse_cross_clock #(
+        .EXTRA_DLY (1)
+    ) snap_tclk_i (
+        .rst       (rst), // input
+        .src_clk   (sclk), // input
+        .dst_clk   (tclk), // input
+        .in_pulse  (snap), // input
+        .out_pulse (snap_tclk), // output
+        .busy      (pulse_busy) // output
+    );
+    
+
+endmodule
+

timing/timestamp_to_parallel.v

+/*******************************************************************************
+ * Module: timestamp_to_parallel
+ * Date:2015-07-04  
+ * Author: andrey     
+ * Description: convert byte-parallel timestamp message to parallel sec, usec
+ * compatible to the x353 code (for NC353 camera)
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * timestamp_to_parallel.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  timestamp_to_parallel.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  timestamp_to_parallel(
+    input                clk, // clock that drives time counters
+    input                pre_stb, // just before receiving sequence of 7 bytes
+    input          [7:0] tdata,   // byte-parallel timestamp data
+    output reg    [31:0] sec,     // time seconds
+    output reg    [19:0] usec,    // time microseconds
+    output               done     // got serial timetamp message, output is valid (1-cycle pulse)
+);
+    reg [6:0] seq;
+    assign done = seq[6];
+    always @ (posedge clk) begin
+        seq <= {seq[5:0],pre_stb};
+        if (seq[0])  sec[ 7: 0] <= tdata;
+        if (seq[1])  sec[15: 8] <= tdata;
+        if (seq[2])  sec[23:16] <= tdata;
+        if (seq[3])  sec[31:24] <= tdata;
+        if (seq[4]) usec[ 7: 0] <= tdata;
+        if (seq[5]) usec[15: 8] <= tdata;
+        if (seq[6]) usec[19:16] <= tdata[3:0];
+    end
+endmodule
+

timing/timestamp_to_serial.v

+/*******************************************************************************
+ * Module: timestamp_to_serial
+ * Date:2015-07-04  
+ * Author: andrey     
+ * Description: convert legacy parallel timestamp data to a byte-parallel message
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * timestamp_to_serial.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  timestamp_to_serial.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  timestamp_to_serial(
+    input                clk, // clock that drives time counters
+    input                stb, // serialize and send timestamp message
+    input         [31:0] sec,     // time seconds
+    input         [19:0] usec,    // time microseconds
+    output reg    [7:0] tdata    // byte-parallel timestamp data sent right after stb input
+);
+    reg  [2:0] cntr;
+    reg        busy = 0;
+    wire [2:0] cntr_w;
+    assign cntr_w= stb? 3'b0 : cntr;
+    always @ (posedge clk) begin
+        if      (stb)          busy <= 1;
+        else if (&cntr_w[2:1]) busy <= 0;
+        if      (stb)   cntr <= 1;
+        else if (busy)  cntr <= cntr + 1;
+        
+        case (cntr_w)
+            3'h0:tdata <=  sec[ 7: 0];
+            3'h1:tdata <=  sec[15: 8];
+            3'h2:tdata <=  sec[23:16];
+            3'h3:tdata <=  sec[31:24];
+            3'h4:tdata <= usec[ 7: 0];
+            3'h5:tdata <= usec[15: 8];
+            3'h6:tdata <= {4'h0,usec[19:16]};
+            3'h7:tdata <= 8'h0;
+        endcase
+    end
+
+endmodule
+

util_modules/pulse_cross_clock.v

@@ -42,7 +42,7 @@ module  pulse_cross_clock#(
         if   (rst) in_reg <= 0;
         else       in_reg <= in_pulse || (in_reg && !out_reg[EXTRA_DLY_SAFE]);
         if   (rst) busy_r <= 0;
-        else       busy_r <= in_pulse || in_reg || (busy_r && out_reg[EXTRA_DLY_SAFE]);
+        else       busy_r <= in_pulse || in_reg || (busy_r && (|out_reg[EXTRA_DLY_SAFE:0]));
     end
     always @(posedge dst_clk or posedge rst) begin
         if   (rst) out_reg <= 0;