Skip to content

X
x393
Commit ea56e79d authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

Implemented global switching between old/new histograms

parent 12f27fa3
Hide whitespace changes
Inline Side-by-side
Showing with 411 additions and 401 deletions
sensor/sensor_channel.v
View file @ ea56e79d
......@@ -259,8 +259,9 @@ module sensor_channel#(
// TODO: get rid of pclk2x in histograms by doubling memories (making 1 write port and 2 read ones)
// How to erase?
// Alternative: copy/erase to a separate buffer in the beginning/end of a frame?
`ifdef USE_PCLK2X
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
`endif
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
......@@ -323,9 +324,11 @@ module sensor_channel#(
assign debug_ring[DEBUG_RING_LENGTH] = debug_di;
`endif
localparam HIST_MONOCHROME = 1'b0; // TODO:make it configurable (at expense of extra hardware)
`ifdef USE_PCLK2X
localparam HIST_MONOCHROME = 1'b0; // TODO:make it configurable (at expense of extra hardware).
// No, will not use it - monochrome is rare, can combine
// 4 (color) histograms by the software.
`endif
localparam SENSOR_BASE_ADDR = (SENSOR_GROUP_ADDR + SENSOR_NUMBER * SENSOR_BASE_INC);
localparam SENSI2C_STATUS_REG = (SENSI2C_STATUS_REG_BASE + SENSOR_NUMBER * SENSI2C_STATUS_REG_INC + SENSI2C_STATUS_REG_REL);
......@@ -993,57 +996,22 @@ module sensor_channel#(
.bayer_out (gamma_bayer) // output [1:0]
);
// Debugging - adding a parallel to 0:0 module
wire hist_rq_debug;
wire [31:0] hist_do_debug;
wire hist_dv_debug;
sens_histogram_snglclk #(
.HISTOGRAM_RAM_MODE ("BUF32"),
// .HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR0),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_snglclk_chn0_0_i (
.mrst (mrst), // input
.prst (prsts), // input
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
.hist_en (hist_en[0]), // input
.hist_rst (!hist_nrst[0]), // input
.hist_rq (hist_rq_debug), // output
.hist_grant (hist_gr[0]), // input
.hist_do (hist_do_debug), // output[31:0]
.hist_dv (hist_dv_debug), // output reg
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
);
// TODO: Use generate to generate 1-4 histogram modules
generate
if (HISTOGRAM_ADDR0 >=0)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR0),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
.mrst (mrst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
`endif
) sens_histogram_0_i (
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -1061,42 +1029,87 @@ module sensor_channel#(
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
// ,.debug_mclk(debug_hist_mclk[0])
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[1]) // input
`endif
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
sens_histogram_dummy sens_histogram_0_i (
.hist_rq (hist_rq[0]), // output
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]) // output
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_di (debug_ring[1]) // input
`endif
`endif
);
// `ifdef USE_PCLK2X
`else
sens_histogram_snglclk #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR0),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_0_i (
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
.hist_en (hist_en[0]), // input
.hist_rst (!hist_nrst[0]), // input
.hist_rq (hist_rq[0]), // output
.hist_grant (hist_gr[0]), // input
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[1]) // input
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_0_i (
.hist_rq (hist_rq[0]), // output
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_di (debug_ring[1]) // input
`endif
);
// `ifdef USE_PCLK2X
`endif
endgenerate
generate
if (HISTOGRAM_ADDR1 >=0)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR1),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
`endif
) sens_histogram_1_i (
.mrst (mrst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
......@@ -1114,30 +1127,73 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
// ,.debug_mclk(debug_hist_mclk[1])
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[2]) // input
`endif
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
sens_histogram_dummy sens_histogram_1_i (
.hist_rq (hist_rq[1]), // output
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_di (debug_ring[2]) // input
`endif
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[1] = debug_ring[2]; // just bypass
//`endif
// `ifdef USE_PCLK2X
`else
sens_histogram_snglclk #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR1),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_1_i (
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
.hist_en (hist_en[1]), // input
.hist_rst (!hist_nrst[1]), // input
.hist_rq (hist_rq[1]), // output
.hist_grant (hist_gr[1]), // input
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[2]) // input
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_1_i (
.hist_rq (hist_rq[1]), // output
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_di (debug_ring[2]) // input
`endif
);
// `ifdef USE_PCLK2X
`endif
endgenerate
generate
if (HISTOGRAM_ADDR2 >=0)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR2),
......@@ -1147,10 +1203,8 @@ module sensor_channel#(
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
) sens_histogram_2_i (
.mrst (mrst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
......@@ -1168,7 +1222,6 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
// ,.debug_mclk(debug_hist_mclk[2])
`ifdef DEBUG_RING
,.debug_do (debug_ring[2]), // output
.debug_sl (debug_sl), // input
......@@ -1176,7 +1229,7 @@ module sensor_channel#(
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
sens_histogram_dummy sens_histogram_2_i (
.hist_rq(hist_rq[2]), // output
.hist_do(hist_do2), // output[31:0]
.hist_dv(hist_dv[2]) // output
......@@ -1185,25 +1238,68 @@ module sensor_channel#(
.debug_di (debug_ring[3]) // input
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[2] = debug_ring[3]; // just bypass
//`endif
// `ifdef USE_PCLK2X
`else
sens_histogram_snglclk #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR2),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_2_i (
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
.hist_en (hist_en[2]), // input
.hist_rst (!hist_nrst[2]), // input
.hist_rq (hist_rq[2]), // output
.hist_grant (hist_gr[2]), // input
.hist_do (hist_do2), // output[31:0]
.hist_dv (hist_dv[2]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
`ifdef DEBUG_RING
,.debug_do (debug_ring[2]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[3]) // input
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_2_i (
.hist_rq(hist_rq[2]), // output
.hist_do(hist_do2), // output[31:0]
.hist_dv(hist_dv[2]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[2]), // output
.debug_di (debug_ring[3]) // input
`endif
);
// `ifdef USE_PCLK2X
`endif
endgenerate
generate
if (HISTOGRAM_ADDR3 >=0)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR3),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
`endif
) sens_histogram_3_i (
.mrst (mrst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
......@@ -1221,26 +1317,68 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
// ,.debug_mclk(debug_hist_mclk[3])
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[4]) // input
`endif
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
sens_histogram_dummy sens_histogram_3_i (
.hist_rq(hist_rq[3]), // output
.hist_do(hist_do3), // output[31:0]
.hist_dv(hist_dv[3]) // output
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_di (debug_ring[4]) // input
`endif
`endif
);
// `ifdef USE_PCLK2X
`else
// `ifdef USE_PCLK2X
sens_histogram_snglclk #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR3),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_3_i (
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
.hist_en (hist_en[3]), // input
.hist_rst (!hist_nrst[3]), // input
.hist_rq (hist_rq[3]), // output
.hist_grant (hist_gr[3]), // input
.hist_do (hist_do3), // output[31:0]
.hist_dv (hist_dv[3]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[4]) // input
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[3] = debug_ring[4]; // just bypass
//`endif
else
sens_histogram_snglclk_dummy sens_histogram_3_i (
.hist_rq(hist_rq[3]), // output
.hist_do(hist_do3), // output[31:0]
.hist_dv(hist_dv[3]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_di (debug_ring[4]) // input
`endif
);
`endif
endgenerate
sens_histogram_mux sens_histogram_mux_i (
......
sensor/sensors393.v
View file @ ea56e79d
......@@ -283,7 +283,9 @@ module sensors393 #(
// input rst,
// will generate it here
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
`ifdef USE_PCLK2X
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
`endif
input ref_clk, // IODELAY calibration
input dly_rst,
input mrst, // @posedge mclk, sync reset
......@@ -592,7 +594,9 @@ module sensors393 #(
`endif
) sensor_channel_i (
.pclk (pclk), // input
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // input
`endif
.mrst (mrst), // input
.prst (prst), // input
......
system_defines.vh
View file @ ea56e79d
......@@ -4,6 +4,8 @@
`define PRELOAD_BRAMS
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI
// `define USE_PCLK2X
// `define DEBUG_RING 1
`define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
......
util_modules/clocks393.v
View file @ ea56e79d
......@@ -40,11 +40,12 @@ module clocks393#(
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter BUF_CLK1X_PCLK = "BUFG",
`ifdef USE_PCLK2X
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
`endif
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
......@@ -101,7 +102,9 @@ module clocks393#(
output aclk, // global clock 50 MHz (used for maxi0)
output hclk, // global clock 150MHz (used for afi*, saxi*)
output pclk, // global clock for sensors (now 96MHz), based on external clock generator
`ifdef USE_PCLK2X
output pclk2x, // global clock for sennors, 2x frequency (now 192MHz)
`endif
output xclk, // global clock for compressor (now 100MHz)
output xclk2x, // global clock for compressor, 2x frequency (now 200MHz)
output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
......@@ -203,16 +206,24 @@ module clocks393#(
.DIVCLK_DIVIDE (DIVCLK_DIVIDE_PCLK),
.CLKFBOUT_MULT (CLKFBOUT_MULT_PCLK),
.CLKOUT_DIV_CLK1X (CLKOUT_DIV_PCLK),
.CLKOUT_DIV_CLK2X (CLKOUT_DIV_PCLK2X),
.BUF_CLK1X (BUF_CLK1X_PCLK)
`ifdef USE_PCLK2X
,.CLKOUT_DIV_CLK2X (CLKOUT_DIV_PCLK2X),
.PHASE_CLK2X (PHASE_CLK2X_PCLK),
.BUF_CLK1X (BUF_CLK1X_PCLK),
.BUF_CLK2X (BUF_CLK1X_PCLK2X)
`else
,.BUF_CLK2X ("NONE")
`endif
) dual_clock_pclk_i (
.rst (async_rst || reset_clk[1]), // input
.clk_in (ffclk0), // input
.pwrdwn (pwrdwn_clk[1]), // input
.clk1x (pclk), // output
`ifdef USE_PCLK2X
.clk2x (pclk2x), // output
`else
.clk2x (), // output not connected
`endif
.locked (locked[1]) // output
);
......
x393.v
View file @ ea56e79d
......@@ -196,8 +196,9 @@ module x393 #(
//TODO: Create missing clocks
wire pclk; // global clock, sensor pixel rate (96 MHz)
`ifdef USE_PCLK2X
wire pclk2x; // global clock, sensor double pixel rate (192 MHz)
`endif
// compressor pixel rate can be adjusted independently
wire xclk; // global clock, compressor pixel rate (100 MHz)?
wire xclk2x; // global clock, compressor double pixel rate (200 MHz)
......@@ -413,6 +414,7 @@ module x393 #(
wire [3:0] sens_buf_rd; // (), // input
wire [255:0] sens_buf_dout; // (), // output[63:0]
wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer
// TODO: Add counter(s) to count sens_xfer_skipped pulses
wire [3:0] sens_xfer_skipped; // single mclk pulse on every skipped (not written) block to record error statistics
wire trigger_mode; // (), // input
wire [3:0] trig_in; // input[3:0]
......@@ -1597,7 +1599,9 @@ assign axi_grst = axi_rst_pre;
) sensors393_i (
// .rst (axi_rst), // input
.pclk (pclk), // input
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // input
`endif
.ref_clk (ref_clk), // input
.dly_rst (idelay_ctrl_reset), // input
.mrst (mrst), // input
......@@ -2164,10 +2168,12 @@ assign axi_grst = axi_rst_pre;
.DIVCLK_DIVIDE_PCLK (DIVCLK_DIVIDE_PCLK),
.CLKFBOUT_MULT_PCLK (CLKFBOUT_MULT_PCLK),
.CLKOUT_DIV_PCLK (CLKOUT_DIV_PCLK),
.BUF_CLK1X_PCLK (BUF_CLK1X_PCLK),
`ifdef USE_PCLK2X
.CLKOUT_DIV_PCLK2X (CLKOUT_DIV_PCLK2X),
.PHASE_CLK2X_PCLK (PHASE_CLK2X_PCLK),
.BUF_CLK1X_PCLK (BUF_CLK1X_PCLK),
.BUF_CLK1X_PCLK2X (BUF_CLK1X_PCLK2X),
`endif
.CLKIN_PERIOD_XCLK (CLKIN_PERIOD_XCLK),
.DIVCLK_DIVIDE_XCLK (DIVCLK_DIVIDE_XCLK),
.CLKFBOUT_MULT_XCLK (CLKFBOUT_MULT_XCLK),
......@@ -2218,7 +2224,9 @@ assign axi_grst = axi_rst_pre;
.aclk (axi_aclk), // output
.hclk (hclk), // output
.pclk (pclk), // output
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // output
`endif
.xclk (xclk), // output
.xclk2x (xclk2x), // output
.sync_clk (camsync_clk), // output
......
x393_testbench03.sav
View file @ ea56e79d
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Thu Oct 22 19:01:31 2015
[*] Thu Oct 22 21:56:23 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151022091046904.fst"
[dumpfile_mtime] "Thu Oct 22 15:49:46 2015"
[dumpfile_size] 277840396
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151022145451521.fst"
[dumpfile_mtime] "Thu Oct 22 21:32:59 2015"
[dumpfile_size] 274609443
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 31840000
[size] 1823 1180
[pos] 1917 0
*-24.043108 75747300 178682388 184032388 75106570 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 0
[size] 1920 1180
[pos] 0 0
*-25.223515 83887388 178682388 184032388 75106570 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
......@@ -28,8 +28,10 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.
......@@ -40,19 +42,20 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 441
[signals_width] 322
[sst_width] 346
[signals_width] 362
[sst_expanded] 1
[sst_vpaned_height] 670
@820
......@@ -629,7 +632,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-
@1000200
-sens_10398
@c00200
@800200
-sensor_channel_0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.mclk
......@@ -712,31 +715,16 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hi
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_dvalid
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_data[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@200
-hist_debug
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en_rq_start
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@1401200
-group_end
@800200
-channels_1_3
@c00028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@1000200
-channels_1_3
@28
......@@ -908,7 +896,6 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
-
@1000200
-mcntr_linear_rw_sensor0
@1401200
-sensor_channel_0
@800200
-DDR3
......@@ -977,7 +964,7 @@ x393_testbench03.simul_sensor12bits_2_i.stopped
x393_testbench03.simul_sensor12bits_2_i.stoppedd
@1401200
-simul_sensor_0
@800200
@c00200
-PX1
@28
x393_testbench03.PX1_MCLK_PRE
......@@ -1011,9 +998,9 @@ x393_testbench03.PX1_MRST
x393_testbench03.PX1_OFST
x393_testbench03.PX1_SHUTTER
x393_testbench03.PX1_VACT
@1000200
@1401200
-PX1
@c00200
@800200
-par_hispi_sel
@28
x393_testbench03.par12_hispi_psp4l0_i.pclk
......@@ -1073,8 +1060,9 @@ x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.clk_out
x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.en
@1401200
-clk_mult_div
@1000200
-par_hispi_sel
@c00200
@800200
-par_hspi_0
@28
x393_testbench03.par12_hispi_psp4l0_i.clk_n
......@@ -1182,7 +1170,7 @@ x393_testbench03.par12_hispi_psp4l0_i.sdata_dly[3:0]
x393_testbench03.par12_hispi_psp4l0_i.sof_sol_sent
x393_testbench03.par12_hispi_psp4l0_i.vact
x393_testbench03.par12_hispi_psp4l0_i.vact_d
@1401200
@1000200
-par_hspi_0
@800200
-scheduler16
......@@ -1582,315 +1570,174 @@ x393_testbench03.x393_i.membridge_i.start_mclk
@1000200
-membridge
-mcntr_linear_rw_chn1
@200
-
@800200