Implemented global switching between old/new histograms (ea56e79d) · Commits · Elphel / x393

sensor/sensor_channel.v

+225 −87

Original line number	Diff line number	Diff line
		@@ -259,8 +259,9 @@ module sensor_channel#(
		// TODO: get rid of pclk2x in histograms by doubling memories (making 1 write port and 2 read ones)
		// How to erase?
		// Alternative: copy/erase to a separate buffer in the beginning/end of a frame?
		`ifdef USE_PCLK2X
		input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)

		`endif
		input mrst, // @posedge mclk, sync reset
		input prst, // @posedge pclk, sync reset

		@@ -323,9 +324,11 @@ module sensor_channel#(
		assign debug_ring[DEBUG_RING_LENGTH] = debug_di;
		`endif


		localparam HIST_MONOCHROME = 1'b0; // TODO:make it configurable (at expense of extra hardware)

		`ifdef USE_PCLK2X
		localparam HIST_MONOCHROME = 1'b0; // TODO:make it configurable (at expense of extra hardware).
		// No, will not use it - monochrome is rare, can combine
		// 4 (color) histograms by the software.
		`endif

		localparam SENSOR_BASE_ADDR = (SENSOR_GROUP_ADDR + SENSOR_NUMBER * SENSOR_BASE_INC);
		localparam SENSI2C_STATUS_REG = (SENSI2C_STATUS_REG_BASE + SENSOR_NUMBER * SENSI2C_STATUS_REG_INC + SENSI2C_STATUS_REG_REL);
		@@ -993,14 +996,12 @@ module sensor_channel#(
		.bayer_out (gamma_bayer) // output [1:0]
		);

		// Debugging - adding a parallel to 0:0 module
		wire hist_rq_debug;
		wire [31:0] hist_do_debug;
		wire hist_dv_debug;

		sens_histogram_snglclk #(
		.HISTOGRAM_RAM_MODE ("BUF32"),
		// .HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
		// TODO: Use generate to generate 1-4 histogram modules
		generate
		if (HISTOGRAM_ADDR0 >=0)
		`ifdef USE_PCLK2X
		sens_histogram #(
		.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
		.HISTOGRAM_ADDR (HISTOGRAM_ADDR0),
		.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
		.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
		@@ -1008,10 +1009,11 @@ module sensor_channel#(
		`ifdef DEBUG_RING
		,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
		`endif
		) sens_histogram_snglclk_chn0_0_i (
		) sens_histogram_0_i (
		.mrst (mrst), // input
		.prst (prsts), // input
		.prst (prsts), // input extended to include sensor reset and rst_mmcm
		.pclk (pclk), // input
		.pclk2x (pclk2x), // input
		.sof (gamma_sof_out), // input
		.eof (gamma_eof_out), // input
		.hact (gamma_hact_out), // input
		@@ -1019,18 +1021,34 @@ module sensor_channel#(
		.mclk (mclk), // input
		.hist_en (hist_en[0]), // input
		.hist_rst (!hist_nrst[0]), // input
		.hist_rq (hist_rq_debug), // output
		.hist_rq (hist_rq[0]), // output
		.hist_grant (hist_gr[0]), // input
		.hist_do (hist_do_debug), // output[31:0]
		.hist_dv (hist_dv_debug), // output reg
		.hist_do (hist_do0), // output[31:0]
		.hist_dv (hist_dv[0]), // output
		.cmd_ad (cmd_ad), // input[7:0]
		.cmd_stb (cmd_stb) // input
		);
		.cmd_stb (cmd_stb), // input
		.monochrome (HIST_MONOCHROME) // input
		// ,.debug_mclk(debug_hist_mclk[0])
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[0]), // output
		.debug_sl (debug_sl), // input
		.debug_di (debug_ring[1]) // input
		`endif

		// TODO: Use generate to generate 1-4 histogram modules
		generate
		if (HISTOGRAM_ADDR0 >=0)
		sens_histogram #(
		);
		else
		sens_histogram_dummy sens_histogram_0_i (
		.hist_rq (hist_rq[0]), // output
		.hist_do (hist_do0), // output[31:0]
		.hist_dv (hist_dv[0]) // output
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[0]), // output
		.debug_di (debug_ring[1]) // input
		`endif
		);
		// `ifdef USE_PCLK2X
		`else
		sens_histogram_snglclk #(
		.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
		.HISTOGRAM_ADDR (HISTOGRAM_ADDR0),
		.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
		@@ -1039,13 +1057,10 @@ module sensor_channel#(
		`ifdef DEBUG_RING
		,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
		`endif
		) sens_histogram_i (
		// .rst (rst), // input
		) sens_histogram_0_i (
		.mrst (mrst), // input
		// .prst (prst), // input
		.prst (prsts), // input extended to include sensor reset and rst_mmcm
		.pclk (pclk), // input
		.pclk2x (pclk2x), // input
		.sof (gamma_sof_out), // input
		.eof (gamma_eof_out), // input
		.hact (gamma_hact_out), // input
		@@ -1058,9 +1073,7 @@ module sensor_channel#(
		.hist_do (hist_do0), // output[31:0]
		.hist_dv (hist_dv[0]), // output
		.cmd_ad (cmd_ad), // input[7:0]
		.cmd_stb (cmd_stb), // input
		.monochrome (HIST_MONOCHROME) // input
		// ,.debug_mclk(debug_hist_mclk[0])
		.cmd_stb (cmd_stb) // input
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[0]), // output
		.debug_sl (debug_sl), // input
		@@ -1069,7 +1082,7 @@ module sensor_channel#(

		);
		else
		sens_histogram_dummy sens_histogram_dummy_i (
		sens_histogram_snglclk_dummy sens_histogram_0_i (
		.hist_rq (hist_rq[0]), // output
		.hist_do (hist_do0), // output[31:0]
		.hist_dv (hist_dv[0]) // output
		@@ -1078,12 +1091,14 @@ module sensor_channel#(
		.debug_di (debug_ring[1]) // input
		`endif
		);

		// `ifdef USE_PCLK2X
		`endif
		endgenerate


		generate
		if (HISTOGRAM_ADDR1 >=0)
		`ifdef USE_PCLK2X
		sens_histogram #(
		.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
		.HISTOGRAM_ADDR (HISTOGRAM_ADDR1),
		@@ -1093,10 +1108,8 @@ module sensor_channel#(
		`ifdef DEBUG_RING
		,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
		`endif
		) sens_histogram_i (
		// .rst (rst), // input
		) sens_histogram_1_i (
		.mrst (mrst), // input
		// .prst (prst), // input
		.prst (prsts), // input extended to include sensor reset and rst_mmcm
		.pclk (pclk), // input
		.pclk2x (pclk2x), // input
		@@ -1114,7 +1127,6 @@ module sensor_channel#(
		.cmd_ad (cmd_ad), // input[7:0]
		.cmd_stb (cmd_stb), // input
		.monochrome (HIST_MONOCHROME) // input
		// ,.debug_mclk(debug_hist_mclk[1])
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[1]), // output
		.debug_sl (debug_sl), // input
		@@ -1122,7 +1134,7 @@ module sensor_channel#(
		`endif
		);
		else
		sens_histogram_dummy sens_histogram_dummy_i (
		sens_histogram_dummy sens_histogram_1_i (
		.hist_rq (hist_rq[1]), // output
		.hist_do (hist_do1), // output[31:0]
		.hist_dv (hist_dv[1]) // output
		@@ -1131,13 +1143,57 @@ module sensor_channel#(
		.debug_di (debug_ring[2]) // input
		`endif
		);
		//`ifdef DEBUG_RING
		// assign debug_ring[1] = debug_ring[2]; // just bypass
		//`endif

		// `ifdef USE_PCLK2X
		`else
		sens_histogram_snglclk #(
		.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
		.HISTOGRAM_ADDR (HISTOGRAM_ADDR1),
		.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
		.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
		.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
		`ifdef DEBUG_RING
		,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
		`endif
		) sens_histogram_1_i (
		.mrst (mrst), // input
		.prst (prsts), // input extended to include sensor reset and rst_mmcm
		.pclk (pclk), // input
		.sof (gamma_sof_out), // input
		.eof (gamma_eof_out), // input
		.hact (gamma_hact_out), // input
		.hist_di (gamma_pxd_out), // input[7:0]
		.mclk (mclk), // input
		.hist_en (hist_en[1]), // input
		.hist_rst (!hist_nrst[1]), // input
		.hist_rq (hist_rq[1]), // output
		.hist_grant (hist_gr[1]), // input
		.hist_do (hist_do1), // output[31:0]
		.hist_dv (hist_dv[1]), // output
		.cmd_ad (cmd_ad), // input[7:0]
		.cmd_stb (cmd_stb) // input
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[1]), // output
		.debug_sl (debug_sl), // input
		.debug_di (debug_ring[2]) // input
		`endif
		);
		else
		sens_histogram_snglclk_dummy sens_histogram_1_i (
		.hist_rq (hist_rq[1]), // output
		.hist_do (hist_do1), // output[31:0]
		.hist_dv (hist_dv[1]) // output
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[1]), // output
		.debug_di (debug_ring[2]) // input
		`endif
		);
		// `ifdef USE_PCLK2X
		`endif
		endgenerate

		generate
		if (HISTOGRAM_ADDR2 >=0)
		`ifdef USE_PCLK2X
		sens_histogram #(
		.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
		.HISTOGRAM_ADDR (HISTOGRAM_ADDR2),
		@@ -1147,10 +1203,8 @@ module sensor_channel#(
		`ifdef DEBUG_RING
		,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
		`endif
		) sens_histogram_i (
		// .rst (rst), // input
		) sens_histogram_2_i (
		.mrst (mrst), // input
		// .prst (prst), // input
		.prst (prsts), // input extended to include sensor reset and rst_mmcm
		.pclk (pclk), // input
		.pclk2x (pclk2x), // input
		@@ -1168,7 +1222,6 @@ module sensor_channel#(
		.cmd_ad (cmd_ad), // input[7:0]
		.cmd_stb (cmd_stb), // input
		.monochrome (HIST_MONOCHROME) // input
		// ,.debug_mclk(debug_hist_mclk[2])
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[2]), // output
		.debug_sl (debug_sl), // input
		@@ -1176,7 +1229,51 @@ module sensor_channel#(
		`endif
		);
		else
		sens_histogram_dummy sens_histogram_dummy_i (
		sens_histogram_dummy sens_histogram_2_i (
		.hist_rq(hist_rq[2]), // output
		.hist_do(hist_do2), // output[31:0]
		.hist_dv(hist_dv[2]) // output
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[2]), // output
		.debug_di (debug_ring[3]) // input
		`endif
		);
		// `ifdef USE_PCLK2X
		`else
		sens_histogram_snglclk #(
		.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
		.HISTOGRAM_ADDR (HISTOGRAM_ADDR2),
		.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
		.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
		.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
		`ifdef DEBUG_RING
		,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
		`endif
		) sens_histogram_2_i (
		.mrst (mrst), // input
		.prst (prsts), // input extended to include sensor reset and rst_mmcm
		.pclk (pclk), // input
		.sof (gamma_sof_out), // input
		.eof (gamma_eof_out), // input
		.hact (gamma_hact_out), // input
		.hist_di (gamma_pxd_out), // input[7:0]
		.mclk (mclk), // input
		.hist_en (hist_en[2]), // input
		.hist_rst (!hist_nrst[2]), // input
		.hist_rq (hist_rq[2]), // output
		.hist_grant (hist_gr[2]), // input
		.hist_do (hist_do2), // output[31:0]
		.hist_dv (hist_dv[2]), // output
		.cmd_ad (cmd_ad), // input[7:0]
		.cmd_stb (cmd_stb) // input
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[2]), // output
		.debug_sl (debug_sl), // input
		.debug_di (debug_ring[3]) // input
		`endif
		);
		else
		sens_histogram_snglclk_dummy sens_histogram_2_i (
		.hist_rq(hist_rq[2]), // output
		.hist_do(hist_do2), // output[31:0]
		.hist_dv(hist_dv[2]) // output
		@@ -1185,12 +1282,13 @@ module sensor_channel#(
		.debug_di (debug_ring[3]) // input
		`endif
		);
		//`ifdef DEBUG_RING
		// assign debug_ring[2] = debug_ring[3]; // just bypass
		//`endif
		// `ifdef USE_PCLK2X
		`endif
		endgenerate

		generate
		if (HISTOGRAM_ADDR3 >=0)
		`ifdef USE_PCLK2X
		sens_histogram #(
		.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
		.HISTOGRAM_ADDR (HISTOGRAM_ADDR3),
		@@ -1200,10 +1298,8 @@ module sensor_channel#(
		`ifdef DEBUG_RING
		,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
		`endif
		) sens_histogram_i (
		// .rst (rst), // input
		) sens_histogram_3_i (
		.mrst (mrst), // input
		// .prst (prst), // input
		.prst (prsts), // input extended to include sensor reset and rst_mmcm
		.pclk (pclk), // input
		.pclk2x (pclk2x), // input
		@@ -1221,7 +1317,6 @@ module sensor_channel#(
		.cmd_ad (cmd_ad), // input[7:0]
		.cmd_stb (cmd_stb), // input
		.monochrome (HIST_MONOCHROME) // input
		// ,.debug_mclk(debug_hist_mclk[3])
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[3]), // output
		.debug_sl (debug_sl), // input
		@@ -1229,7 +1324,52 @@ module sensor_channel#(
		`endif
		);
		else
		sens_histogram_dummy sens_histogram_dummy_i (
		sens_histogram_dummy sens_histogram_3_i (
		.hist_rq(hist_rq[3]), // output
		.hist_do(hist_do3), // output[31:0]
		.hist_dv(hist_dv[3]) // output
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[3]), // output
		.debug_di (debug_ring[4]) // input
		`endif
		);
		// `ifdef USE_PCLK2X
		`else
		// `ifdef USE_PCLK2X
		sens_histogram_snglclk #(
		.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
		.HISTOGRAM_ADDR (HISTOGRAM_ADDR3),
		.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
		.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
		.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
		`ifdef DEBUG_RING
		,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
		`endif
		) sens_histogram_3_i (
		.mrst (mrst), // input
		.prst (prsts), // input extended to include sensor reset and rst_mmcm
		.pclk (pclk), // input
		.sof (gamma_sof_out), // input
		.eof (gamma_eof_out), // input
		.hact (gamma_hact_out), // input
		.hist_di (gamma_pxd_out), // input[7:0]
		.mclk (mclk), // input
		.hist_en (hist_en[3]), // input
		.hist_rst (!hist_nrst[3]), // input
		.hist_rq (hist_rq[3]), // output
		.hist_grant (hist_gr[3]), // input
		.hist_do (hist_do3), // output[31:0]
		.hist_dv (hist_dv[3]), // output
		.cmd_ad (cmd_ad), // input[7:0]
		.cmd_stb (cmd_stb) // input
		`ifdef DEBUG_RING
		,.debug_do (debug_ring[3]), // output
		.debug_sl (debug_sl), // input
		.debug_di (debug_ring[4]) // input
		`endif
		);
		else
		sens_histogram_snglclk_dummy sens_histogram_3_i (
		.hist_rq(hist_rq[3]), // output
		.hist_do(hist_do3), // output[31:0]
		.hist_dv(hist_dv[3]) // output
		@@ -1238,9 +1378,7 @@ module sensor_channel#(
		.debug_di (debug_ring[4]) // input
		`endif
		);
		//`ifdef DEBUG_RING
		// assign debug_ring[3] = debug_ring[4]; // just bypass
		//`endif
		`endif
		endgenerate

		sens_histogram_mux sens_histogram_mux_i (

sensor/sensors393.v

+4 −0

Original line number	Diff line number	Diff line
		@@ -283,7 +283,9 @@ module sensors393 #(
		// input rst,
		// will generate it here
		input pclk, // global clock input, pixel rate (96MHz for MT9P006)
		`ifdef USE_PCLK2X
		input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
		`endif
		input ref_clk, // IODELAY calibration
		input dly_rst,
		input mrst, // @posedge mclk, sync reset
		@@ -592,7 +594,9 @@ module sensors393 #(
		`endif
		) sensor_channel_i (
		.pclk (pclk), // input
		`ifdef USE_PCLK2X
		.pclk2x (pclk2x), // input
		`endif
		.mrst (mrst), // input
		.prst (prst), // input

system_defines.vh

+2 −0

Original line number	Diff line number	Diff line
		@@ -4,6 +4,8 @@
		`define PRELOAD_BRAMS
		// if HISPI is not defined, parallel sensor interface is used for all channels
		`define HISPI

		// `define USE_PCLK2X
		// `define DEBUG_RING 1
		`define MEMBRIDGE_DEBUG_WRITE 1
		// Enviroment-dependent options

util_modules/clocks393.v

+15 −4

Original line number	Diff line number	Diff line
		@@ -40,11 +40,12 @@ module clocks393#(
		parameter DIVCLK_DIVIDE_PCLK = 1,
		parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
		parameter CLKOUT_DIV_PCLK = 10, // 96MHz
		parameter BUF_CLK1X_PCLK = "BUFG",
		`ifdef USE_PCLK2X
		parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
		parameter PHASE_CLK2X_PCLK = 0.000,
		parameter BUF_CLK1X_PCLK = "BUFG",
		parameter BUF_CLK1X_PCLK2X = "BUFG",

		`endif
		parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
		parameter DIVCLK_DIVIDE_XCLK = 1,
		parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
		@@ -101,7 +102,9 @@ module clocks393#(
		output aclk, // global clock 50 MHz (used for maxi0)
		output hclk, // global clock 150MHz (used for afi, saxi)
		output pclk, // global clock for sensors (now 96MHz), based on external clock generator
		`ifdef USE_PCLK2X
		output pclk2x, // global clock for sennors, 2x frequency (now 192MHz)
		`endif
		output xclk, // global clock for compressor (now 100MHz)
		output xclk2x, // global clock for compressor, 2x frequency (now 200MHz)
		output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
		@@ -203,16 +206,24 @@ module clocks393#(
		.DIVCLK_DIVIDE (DIVCLK_DIVIDE_PCLK),
		.CLKFBOUT_MULT (CLKFBOUT_MULT_PCLK),
		.CLKOUT_DIV_CLK1X (CLKOUT_DIV_PCLK),
		.CLKOUT_DIV_CLK2X (CLKOUT_DIV_PCLK2X),
		.BUF_CLK1X (BUF_CLK1X_PCLK)
		`ifdef USE_PCLK2X
		,.CLKOUT_DIV_CLK2X (CLKOUT_DIV_PCLK2X),
		.PHASE_CLK2X (PHASE_CLK2X_PCLK),
		.BUF_CLK1X (BUF_CLK1X_PCLK),
		.BUF_CLK2X (BUF_CLK1X_PCLK2X)
		`else
		,.BUF_CLK2X ("NONE")
		`endif
		) dual_clock_pclk_i (
		.rst (async_rst \|\| reset_clk[1]), // input
		.clk_in (ffclk0), // input
		.pwrdwn (pwrdwn_clk[1]), // input
		.clk1x (pclk), // output
		`ifdef USE_PCLK2X
		.clk2x (pclk2x), // output
		`else
		.clk2x (), // output not connected
		`endif
		.locked (locked[1]) // output
		);

x393.v

+10 −2

Original line number	Diff line number	Diff line
		@@ -196,8 +196,9 @@ module x393 #(
		//TODO: Create missing clocks

		wire pclk; // global clock, sensor pixel rate (96 MHz)
		`ifdef USE_PCLK2X
		wire pclk2x; // global clock, sensor double pixel rate (192 MHz)

		`endif
		// compressor pixel rate can be adjusted independently
		wire xclk; // global clock, compressor pixel rate (100 MHz)?
		wire xclk2x; // global clock, compressor double pixel rate (200 MHz)
		@@ -413,6 +414,7 @@ module x393 #(
		wire [3:0] sens_buf_rd; // (), // input
		wire [255:0] sens_buf_dout; // (), // output[63:0]
		wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer
		// TODO: Add counter(s) to count sens_xfer_skipped pulses
		wire [3:0] sens_xfer_skipped; // single mclk pulse on every skipped (not written) block to record error statistics
		wire trigger_mode; // (), // input
		wire [3:0] trig_in; // input[3:0]
		@@ -1597,7 +1599,9 @@ assign axi_grst = axi_rst_pre;
		) sensors393_i (
		// .rst (axi_rst), // input
		.pclk (pclk), // input
		`ifdef USE_PCLK2X
		.pclk2x (pclk2x), // input
		`endif
		.ref_clk (ref_clk), // input
		.dly_rst (idelay_ctrl_reset), // input
		.mrst (mrst), // input
		@@ -2164,10 +2168,12 @@ assign axi_grst = axi_rst_pre;
		.DIVCLK_DIVIDE_PCLK (DIVCLK_DIVIDE_PCLK),
		.CLKFBOUT_MULT_PCLK (CLKFBOUT_MULT_PCLK),
		.CLKOUT_DIV_PCLK (CLKOUT_DIV_PCLK),
		.BUF_CLK1X_PCLK (BUF_CLK1X_PCLK),
		`ifdef USE_PCLK2X
		.CLKOUT_DIV_PCLK2X (CLKOUT_DIV_PCLK2X),
		.PHASE_CLK2X_PCLK (PHASE_CLK2X_PCLK),
		.BUF_CLK1X_PCLK (BUF_CLK1X_PCLK),
		.BUF_CLK1X_PCLK2X (BUF_CLK1X_PCLK2X),
		`endif
		.CLKIN_PERIOD_XCLK (CLKIN_PERIOD_XCLK),
		.DIVCLK_DIVIDE_XCLK (DIVCLK_DIVIDE_XCLK),
		.CLKFBOUT_MULT_XCLK (CLKFBOUT_MULT_XCLK),
		@@ -2218,7 +2224,9 @@ assign axi_grst = axi_rst_pre;
		.aclk (axi_aclk), // output
		.hclk (hclk), // output
		.pclk (pclk), // output
		`ifdef USE_PCLK2X
		.pclk2x (pclk2x), // output
		`endif
		.xclk (xclk), // output
		.xclk2x (xclk2x), // output
		.sync_clk (camsync_clk), // output

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