testing and simulating, improving timing

db53f38f · Andrey Filippov · 4ca48f7b · db53f38f · db53f38f · db53f38f
Commit db53f38f authored Nov 03, 2015 by Andrey Filippov
33 changed files
--- a/.gitignore
+++ b/.gitignore
@@ -10,6 +10,8 @@ x393.prj
 *DEBUG_VDT*
 *.kate-swp
 *.old
+*.new
+*.bad
 *.pyc
 *.pickle
 py393/dbg*

--- a/.project
+++ b/.project
@@ -62,42 +62,42 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151031232335810.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
@@ -107,7 +107,7 @@
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150904164653967.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20151101221627109.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

--- a/.settings/com.elphel.vdt.VivadoRoute.prefs
+++ b/.settings/com.elphel.vdt.VivadoRoute.prefs
 VivadoRoute_122_SkipSnapshotRoute=true
 VivadoRoute_123_SkipSnapshotRoute=true
-com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->
+VivadoRoute_125_directive_route=MoreGlobalIterations
+com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->VivadoRoute_125_directive_route<-@\#\#@->
 eclipse.preferences.version=1
--- a/compressor_jp/csconvert18a.v
+++ b/compressor_jp/csconvert18a.v
@@ -249,7 +249,7 @@ module csconvert18a(
  wire        ystrt,nxtline;
  reg	[7:0] yaddr_r; // address for the external buffer memory to write 16x16x8bit Y data
-  reg         ywe_r;	 // wrire enable of Y data
+  reg         ywe_r;	 // write enable of Y data
  reg   [6:0] caddr_r; // address for the external buffer memory 2x8x8x8bit Cb+Cr data (MSB=0 - Cb, 1 - Cr)
  reg         cwe_r;	 // write enable for CbCr data 
  reg         odd_pix;  // odd pixel (assumes even number of pixels in a line
@@ -267,10 +267,10 @@ module csconvert18a(
  assign n000 =     n000_r;
  assign n255 =     n255_r;
  assign signed_y = signed_y_r;     //  - now signed char, -128(black) to +127 (white)
-  assign yaddr =    yaddr_r;
+  assign yaddr =    yaddr_r2;
-  assign ywe =      ywe_r;
+  assign ywe =      ywe_r2;
-  assign caddr =    caddr_r;
+  assign caddr =    caddr_r2;
-  assign cwe =      cwe_r;
+  assign cwe =      cwe_r2;
    dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(pre_first_in), .dout(strt_dly[0]));
    dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(strt_dly[0]),  .dout(strt_dly[1]));
@@ -532,20 +532,28 @@ Y[1,1]=(0x96*P[1,1]+   0x1d*((P[1,0]+P[1,2])/2 +                 0x4d*((P[0,1] +
  reg   [7:0] y;
 //  reg   [7:0] y0;	// bypass in monochrome mode
-  wire  [7:0] y0 = pdc;
+//  wire  [7:0] y0 = pdc;
+  reg  [7:0] y0_r;
 //  wire   [7:0] y0;	// bypass in monochrome mode
-  reg   [15:0] y1,y2,y3; 
+  reg   [15:0] y1,y2,y3;
-  wire	[15:0] y_sum =y1+y2+y3;
+// TODO: insert register to ease mm1..3 -> y (OK to delay all outputs). Or is it not using DSP at all?   
+//  wire	[15:0] y_sum =y1+y2+y3;
+  reg   [15:0] y_sum_r;
 //  always @ (posedge CLK) y0 <= pd1_dly; // m1; // equivalent
-  always @ (posedge CLK) y1 <= mm1;
+//  wire   [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);
-  always @ (posedge CLK) y2 <= mm2;
+  wire   [7:0] pre_y= mono ? y0_r : (y_sum_r[15:8]+y_sum_r[7]);
-  always @ (posedge CLK) y3 <= mm3;
 // making y output signed -128..+127
-  wire   [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);
-  always @ (posedge CLK) y[7:0] <= pre_y[7:0];
-  always @ (posedge CLK) signed_y_r[7:0] <= {~pre_y[7], pre_y[6:0]};
+  always @ (posedge CLK) begin
+      y1 <= mm1;
+      y2 <= mm2;
+      y3 <= mm3;
+      y0_r <= pdc;
+      y_sum_r <= y1+y2+y3;
+      y[7:0] <= pre_y[7:0];
+      signed_y_r[7:0] <= {~pre_y[7], pre_y[6:0]};
+  end
 // Try easier and hope better algorithm of color extractions that should perform better on gradients.
@@ -574,13 +582,22 @@ reg         use_cr;        // in this line cr is calculated. Valid during ywe_r
 reg         sub_y;         // output accumulator/subtractor. 0 - load new data, 1 - subtract. Walid 2 cycles after ywe_r
 wire        cwe0;          // preliminary cwe_r (to be modulated by odd/even pixels)
 reg         cstrt;         //ystrt dealyed by 1
-reg         cnxt;          // nxtline delayed by 1 
+reg         cnxt;          // nxtline delayed by 1
+reg         pre_sel_cbcrmult1;
+// delaying, for now uing "old" ywe,cwe, yaddr,caddr - registering them on the output
 always @ (posedge CLK) begin
-  if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
+//  if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
-  else      sel_cbcrmult1 <= ~sel_cbcrmult1;
+//  else      sel_cbcrmult1 <= ~sel_cbcrmult1;
+  if (~(ywe_r || ystrt || nxtline)) pre_sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
+  else      pre_sel_cbcrmult1 <= ~pre_sel_cbcrmult1;
+  sel_cbcrmult1 <=pre_sel_cbcrmult1;
  sub_y <= ~sel_cbcrmult1;
-  cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
+//  cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
-  cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
+  cbcrmult1 <= sel_cbcrmult1?y[7:0]:y0_r[7:0]; // delayed by 1 clock
  if (~ywe_r) use_cr <= ~(bayer_phase[1] ^ odd_line);
 end
 assign      cbcrmult2 = use_cr?m_cr:m_cb;  // maybe will need a register? (use_cr will still be good as it is valid early)
@@ -601,23 +618,38 @@ end
 dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(ywe_r), .dout(cwe0));
 //SRL16 i_cwe0    (.D(ywe_r ),  .Q(cwe0), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLK)); // dly=2=1+1
-always @ (posedge CLK) begin
-      cstrt <= ystrt;
-      cnxt  <= nxtline;
+    always @ (posedge CLK) begin
-      cwe_r <= cwe0 && sub_y; 
+        cstrt <= ystrt;
-      caddr_r[2:0]<= cwe0?(caddr_r[2:0]+cwe_r):3'b0;
+        cnxt  <= nxtline;
-      if (cstrt)     caddr_r[6] <= ~bayer_phase[1];
+//        cwe_r <= cwe0 && sub_y;
-      else if (cnxt) caddr_r[6] <= ~caddr_r[6];
+        cwe_r <= cwe0 && !sel_cbcrmult1;
-      if (cstrt)     caddr_r[5:3] <=3'b0;
+        caddr_r[2:0]<= cwe0?(caddr_r[2:0]+cwe_r):3'b0;
-      else if (cnxt) caddr_r[5:3] <=(bayer_phase[1]^caddr_r[6])? caddr_r[5:3]:(caddr_r[5:3]+1);
+        if (cstrt)     caddr_r[6] <= ~bayer_phase[1];
-end
+        else if (cnxt) caddr_r[6] <= ~caddr_r[6];
+        if (cstrt)     caddr_r[5:3] <=3'b0;
+        else if (cnxt) caddr_r[5:3] <=(bayer_phase[1]^caddr_r[6])? caddr_r[5:3]:(caddr_r[5:3]+1);
+    end
+// extra signals delayed by 1 clock
+    reg ywe_r2, cwe_r2;
+    reg [6:0] caddr_r2;
+    reg [7:0] yaddr_r2;
+    always @ (posedge CLK) begin
+        ywe_r2 <= ywe_r;
+        cwe_r2 <= cwe_r;
+        yaddr_r2 <= yaddr_r;
+        caddr_r2 <= caddr_r;
+    end
  always @ (posedge CLK) begin
-    y_eq_0   <= (y0[7:0] == 8'h0);
+    y_eq_0   <= (y0_r[7:0] == 8'h0);
-    y_eq_255 <= (y0[7:0] == 8'hff);
+    y_eq_255 <= (y0_r[7:0] == 8'hff);
    if (strt) n000_r[7:0] <= 8'h0;
-    else if ((n000_r[7:0]!=8'hff) && y_eq_0 && ywe_r) n000_r[7:0] <= n000_r[7:0]+1;
+    else if ((n000_r[7:0]!=8'hff) && y_eq_0 && ywe_r2) n000_r[7:0] <= n000_r[7:0]+1;
    if (strt) n255_r[7:0] <= 8'h0;
-    else if ((n255_r[7:0]!=8'hff) && y_eq_255 && ywe_r) n255_r[7:0] <= n255_r[7:0]+1;
+    else if ((n255_r[7:0]!=8'hff) && y_eq_255 && ywe_r2) n255_r[7:0] <= n255_r[7:0]+1;
  end

--- a/ddr3/ddr3.v
+++ b/ddr3/ddr3.v
@@ -85,7 +85,7 @@
 * 1.69  SPH      03/19/13    Update tZQCS, tZQinit, tZQoper timing parameters
 * 1.70  SPH      04/08/14    Update tRFC to PRECARGE check
 *****************************************************************************************/
-`define den4096Mb 1
+`include "system_defines.vh" 
 // DO NOT CHANGE THE TIMESCALE
 // MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
 `timescale 1ps / 1ps
@@ -121,6 +121,19 @@ module ddr3 (
    //       to select the correct component density before continuing
    ERROR: You must specify component density with +define+den____Mb.
 `endif
+    initial begin
+        $display ("TCK_MIN = %d", TCK_MIN);
+`ifdef sg15E
+        $display ("sg15E = `sg15E");
+`endif  
+`ifdef sg093                              // sg093  is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin
+        $display ("sg093");
+`elsif sg15E
+        $display ("sg15E");
+`endif          
+    end
    parameter check_strict_mrbits = 1;
    parameter check_strict_timing = 1;
    parameter feature_pasr = 1;

--- a/fpga_version.vh
+++ b/fpga_version.vh
-      parameter FPGA_VERSION =          32'h0393005c; // 250MHz ???
+      parameter FPGA_VERSION =          32'h03930065; // (same rev) all met,  using "old" (non-inverted) phase - OK (full phase range)
+//      parameter FPGA_VERSION =          32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
+//      parameter FPGA_VERSION =          32'h03930064; // switch mcomtr_sequencer.v  (xclk not met) - wrong!
+//      parameter FPGA_VERSION =          32'h03930063; // switch mcntrl_linear_rw.v (met) good, worse mem valid phases 
+//      parameter FPGA_VERSION =          32'h03930062; // (met)debugging - what was broken (using older versions of some files) - mostly OK (some glitches)
+//      parameter FPGA_VERSION =          32'h03930061; // restored bufr instead of bufio for memory high speed clock
+//      parameter FPGA_VERSION =          32'h03930060; // moving CLK1..3 in memory controller MMCM, keeping CLK0 and FB. Stuck at memory calib 
+//      parameter FPGA_VERSION =          32'h0393005f; // restored mclk back to 200KHz, registers added to csconvert18a
+//      parameter FPGA_VERSION =          32'h0393005e; // trying mclk = 225 MHz (was 200MHz) define MCLK_VCO_MULT 18
+//      parameter FPGA_VERSION =          32'h0393005d; // trying mclk = 250 MHz (was 200MHz) define MCLK_VCO_MULT 20
+//      parameter FPGA_VERSION =          32'h0393005c; // 250MHz OK, no timing violations
 //    parameter FPGA_VERSION =          32'h0393005b; // 250MHz Not tested, timing violation in bit_stuffer_escape: xclk -0.808 -142.047 515
 //    parameter FPGA_VERSION =          32'h0393005a; // Trying xclk = 250MHz - timing viloations in xdct393, but particular hardware works
 //    parameter FPGA_VERSION =          32'h03930059; // 'new' (no pclk2x, no xclk2x  clocks) sensor/converter w/o debug - OK

--- a/includes/x393_parameters.vh
+++ b/includes/x393_parameters.vh
@@ -138,7 +138,11 @@
    parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
    parameter HIGH_PERFORMANCE_MODE = "FALSE",
    parameter CLKIN_PERIOD =        20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to             | 6.667
+`ifdef MCLK_VCO_MULT    
+    parameter CLKFBOUT_MULT =       `MCLK_VCO_MULT ,
+`else    
    parameter CLKFBOUT_MULT =       16,   // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE  | 16
+`endif    
    parameter CLKFBOUT_MULT_REF =   16,   // 18,   // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE  | 6
    parameter CLKFBOUT_DIV_REF =    4, // 200Mhz 3, // To get 300MHz for the reference clock
 `else
@@ -150,11 +154,12 @@
    parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
 `endif    
    parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS= 0, //1, // 0 - old, 1 - new 
    parameter CLKFBOUT_PHASE =      0.000,
    parameter SDCLK_PHASE =         0.000,
-    parameter CLK_PHASE =           0.000,
+    parameter CLK_PHASE =           0.000, //11.25, /// 0.000,
    parameter CLK_DIV_PHASE =       0.000,
-    parameter MCLK_PHASE =          90.000,
+    parameter MCLK_PHASE =          90.000, //78.75, // 90.000,
    parameter REF_JITTER1 =         0.010,
    parameter SS_EN =              "FALSE",
    parameter SS_MODE =      "CENTER_HIGH",

--- a/includes/x393_tasks_mcntrl_timing.vh
+++ b/includes/x393_tasks_mcntrl_timing.vh
@@ -193,11 +193,19 @@
    task axi_set_phase;
        input [PHASE_WIDTH-1:0] phase;
+        reg   [PHASE_WIDTH-1:0] inverted_phase;
        begin
-            $display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
+            if (CLKFBOUT_USE_FINE_PS) begin
-            write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
+                inverted_phase = -phase;
+                $display("SET CLOCK INVERTED PHASE (0x%x) to 0x%x @ %t",phase,inverted_phase,$time);
+                write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},inverted_phase}); // control regiter address
+                target_phase <= inverted_phase;
+            end else begin
+                $display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
+                write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
+                target_phase <= phase;
+            end
            write_contol_register(DLY_SET,0);
-            target_phase <= phase;
        end
    endtask

--- a/memctrl/mcntrl393.v
+++ b/memctrl/mcntrl393.v
@@ -153,6 +153,7 @@ module  mcntrl393 #(
    parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
 `endif    
    parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new 
    parameter CLKFBOUT_PHASE =      0.000,
    parameter SDCLK_PHASE =         0.000,
    parameter CLK_PHASE =           0.000,
@@ -1816,6 +1817,7 @@ module  mcntrl393 #(
        .CLKFBOUT_MULT_REF     (CLKFBOUT_MULT_REF),
        .CLKFBOUT_DIV_REF      (CLKFBOUT_DIV_REF),
        .DIVCLK_DIVIDE         (DIVCLK_DIVIDE),
+        .CLKFBOUT_USE_FINE_PS  (CLKFBOUT_USE_FINE_PS),
        .CLKFBOUT_PHASE        (CLKFBOUT_PHASE),
        .SDCLK_PHASE           (SDCLK_PHASE),
        .CLK_PHASE             (CLK_PHASE),

--- a/memctrl/mcntrl_linear_rw.v
+++ b/memctrl/mcntrl_linear_rw.v
@@ -177,6 +177,7 @@ module  mcntrl_linear_rw #(
    reg   [FRAME_HEIGHT_BITS-1:0] line_unfinished_r;
    wire                          pre_want;
+    reg                           pre_want_r1;
    wire                    [1:0] status_data;
    wire                    [3:0] cmd_a; 
    wire                   [31:0] cmd_data; 
@@ -324,8 +325,9 @@ module  mcntrl_linear_rw #(
    assign frame_done=  frame_done_r;
    assign frame_finished=  frame_finished_r;
-//    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !frame_start_r[0];
+//    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r);
-    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r);
+    // accelerating pre_want:
+    assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend ;
    assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
    assign last_row_w=  next_y==window_height;
@@ -407,9 +409,9 @@ module  mcntrl_linear_rw #(
        else if (chn_rst || xfer_grant || start_skip_r)   need_r <= 0;
        else if ((pre_want  || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
-        if (mrst)                                                want_r <= 0;
+        if (mrst)                                                  want_r <= 0;
-        else if (chn_rst || xfer_grant || start_skip_r)          want_r <= 0;
+        else if (chn_rst || xfer_grant || start_skip_r)            want_r <= 0;
-        else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
+        else if (pre_want && (page_cntr > {1'b0,cmd_extra_pages})) want_r <= 1;
    end    
@@ -469,6 +471,9 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
 // now have row start address, bank and row_left ;
 // calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page    
    always @(posedge mclk) begin
+        // acceletaring pre_want
+        pre_want_r1 <= chn_en &&  !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]) && !last_block;
        if      (mrst)                par_mod_r<=0;
        else if (pgm_param_w ||
                 xfer_start_r[0] ||

--- a/memctrl/memctrl16.v
+++ b/memctrl/memctrl16.v
@@ -126,6 +126,7 @@ module  memctrl16 #(
    parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
 `endif    
    parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new 
    parameter CLKFBOUT_PHASE =      0.000,
    parameter SDCLK_PHASE =         0.000,
    parameter CLK_PHASE =           0.000,
@@ -905,6 +906,7 @@ end
        .CLKFBOUT_MULT_REF             (CLKFBOUT_MULT_REF),
        .CLKFBOUT_DIV_REF              (CLKFBOUT_DIV_REF),
        .DIVCLK_DIVIDE                 (DIVCLK_DIVIDE),
+        .CLKFBOUT_USE_FINE_PS          (CLKFBOUT_USE_FINE_PS),
        .CLKFBOUT_PHASE                (CLKFBOUT_PHASE),
        .SDCLK_PHASE                   (SDCLK_PHASE),
        .CLK_PHASE                     (CLK_PHASE),

--- a/memctrl/phy/byte_lane.v
+++ b/memctrl/phy/byte_lane.v
@@ -78,7 +78,27 @@ reg        set_r=0;
 reg  dci_disable_dqs_r, dci_disable_dq_r;
 reg  [7:0] ld_odly=8'b0, ld_idly=8'b0;
 reg        ld_odly_dqs,ld_idly_dqs,ld_odly_dm;
-BUFR                          iclk_i    (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
+BUFR  iclk_i    (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
+/*
+wire iclk_int;
+//BUFR     iclk_int_i (.O(iclk_int), .I(dqs_read), .CLR(1'b0),.CE(1'b1));
+    assign iclk_int = dqs_read && !rst;
+BUFIO    iclk_i     (.O(iclk),     .I(iclk_int));
+CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance
+mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_M at N7 (IOB_X1Y120
+since it belongs to a shape containing instance mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i.
+The shape requires relative placement between 
+mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_M and
+mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i that cannnot be honored because it would result in
+an invalid location for mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i. [x393.xdc:193]
+----------
+ERROR: [DRC 23-20] Rule violation (RTSTAT-1) Unrouted net - 2 net(s) are unrouted. The problem bus(es) and/or net(s) are 
+mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/iclk_int,
+mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_int.
+*/
 wire [9:0] decode_sel={
    (dly_addr[3:0]==9)?1'b1:1'b0,
    (dly_addr[3:0]==8)?1'b1:1'b0,

--- a/memctrl/phy/mcontr_sequencer.v
+++ b/memctrl/phy/mcontr_sequencer.v
@@ -80,6 +80,7 @@ module  mcontr_sequencer   #(
    parameter CLKFBOUT_MULT_REF =   9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
    parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
    parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new 
    parameter CLKFBOUT_PHASE =      0.000,
    parameter SDCLK_PHASE =         0.000,
    parameter CLK_PHASE =           0.000,
@@ -551,9 +552,9 @@ module  mcontr_sequencer   #(
        .CLKFBOUT_MULT_REF     (CLKFBOUT_MULT_REF),
        .CLKFBOUT_DIV_REF      (CLKFBOUT_DIV_REF),
        .DIVCLK_DIVIDE         (DIVCLK_DIVIDE),
+        .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
        .CLKFBOUT_PHASE        (CLKFBOUT_PHASE),
        .SDCLK_PHASE           (SDCLK_PHASE), /// debugging
        .CLK_PHASE             (CLK_PHASE),
        .CLK_DIV_PHASE         (CLK_DIV_PHASE),
        .MCLK_PHASE            (MCLK_PHASE),

--- a/memctrl/phy/phy_cmd.v
+++ b/memctrl/phy/phy_cmd.v
@@ -36,8 +36,9 @@ module  phy_cmd#(
    parameter CLKFBOUT_MULT_REF =   9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
    parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
    parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new 
    parameter CLKFBOUT_PHASE =      0.000,
-    parameter SDCLK_PHASE =          0.000,
+    parameter SDCLK_PHASE =         0.000,
    parameter CLK_PHASE =           0.000,
    parameter CLK_DIV_PHASE =       0.000,
    parameter MCLK_PHASE =          90.000,
@@ -379,6 +380,7 @@ module  phy_cmd#(
        .CLKFBOUT_MULT_REF(CLKFBOUT_MULT_REF),
        .CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
        .DIVCLK_DIVIDE    (DIVCLK_DIVIDE),
+        .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
        .CLKFBOUT_PHASE   (CLKFBOUT_PHASE),
        .SDCLK_PHASE      (SDCLK_PHASE),
        .CLK_PHASE        (CLK_PHASE),

--- a/memctrl/phy/phy_top.v
+++ b/memctrl/phy/phy_top.v
@@ -43,8 +43,9 @@ module  phy_top #(
    parameter CLKFBOUT_MULT_REF =   9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
    parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
    parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS =1, // if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same)
    parameter CLKFBOUT_PHASE =      0.000,
-    parameter SDCLK_PHASE =          0.000,
+    parameter SDCLK_PHASE =         0.000,
    parameter CLK_PHASE =           0.000,
    parameter CLK_DIV_PHASE =       0.000,
    parameter MCLK_PHASE =          90.000,  
@@ -312,6 +313,7 @@ wire sdclk; // BUFIO
 // So shifting phase dynamically by plus/- 113 moves SDCLK by a full period (2.5ns) forward and backward (113= 0x71)
 wire clk_pre, clk_div_pre, sdclk_pre, mclk_pre, clk_fb;
 BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre));
+//BUFIO clk_buf_i (.O(clk), .I(clk_pre));
 BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre));
 BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) );
 //BUFIO clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
@@ -325,19 +327,21 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
        .BANDWIDTH           (BANDWIDTH),
        .CLKFBOUT_MULT_F     (CLKFBOUT_MULT),
        .DIVCLK_DIVIDE       (DIVCLK_DIVIDE),
-        .CLKFBOUT_PHASE      (CLKFBOUT_PHASE),
+        .CLKFBOUT_PHASE      (CLKFBOUT_USE_FINE_PS? 0.0 :           CLKFBOUT_PHASE),
-        .CLKOUT0_PHASE       (SDCLK_PHASE),
+        .CLKOUT0_PHASE       (CLKFBOUT_USE_FINE_PS? 0.0 :           SDCLK_PHASE),
-        .CLKOUT1_PHASE       (CLK_PHASE),
+        .CLKOUT1_PHASE       (CLKFBOUT_USE_FINE_PS? CLK_PHASE :     0.0),
-        .CLKOUT2_PHASE       (CLK_DIV_PHASE),
+        .CLKOUT2_PHASE       (CLKFBOUT_USE_FINE_PS? CLK_DIV_PHASE : 0.0),
-        .CLKOUT3_PHASE       (MCLK_PHASE),
+        .CLKOUT3_PHASE       (CLKFBOUT_USE_FINE_PS? MCLK_PHASE :   90.000), // (78.75), // (MCLK_PHASE), // should be multiple of 11.25 (90.000/8)
+//ERROR: [DRC 23-20] Rule violation (AVAL-139) Phase shift check - The MMCME2_ADV cell mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i has a fractional CLKOUT3_PHASE value (75.000)  with CLKOUT3_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKOUT3_DIVIDE] = [45 / 4] = 11.250.
 //        .CLKOUT4_PHASE          (0.000),
 //        .CLKOUT5_PHASE          (0.000),
 //        .CLKOUT6_PHASE          (0.000),
-        .CLKFBOUT_USE_FINE_PS     ("FALSE"),
+        .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "TRUE" : "FALSE"),
-        .CLKOUT0_USE_FINE_PS      ("FALSE"),
+        .CLKOUT0_USE_FINE_PS  (CLKFBOUT_USE_FINE_PS? "TRUE" : "FALSE"),
-        .CLKOUT1_USE_FINE_PS ("TRUE"),
+        .CLKOUT1_USE_FINE_PS  (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
-        .CLKOUT2_USE_FINE_PS ("TRUE"),
+        .CLKOUT2_USE_FINE_PS  (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
-        .CLKOUT3_USE_FINE_PS ("TRUE"),
+        .CLKOUT3_USE_FINE_PS  (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
 //        .CLKOUT4_USE_FINE_PS("FALSE"),
 //        .CLKOUT5_USE_FINE_PS("FALSE"),
 //        .CLKOUT6_USE_FINE_PS("FALSE"),

--- a/py393/dbg/x393_mcntrl.pickle
+++ b/py393/dbg/x393_mcntrl.pickle
--- a/py393/import_verilog_parameters.py
+++ b/py393/import_verilog_parameters.py
@@ -393,6 +393,11 @@ class ImportVerilogParameters(object):
        # Try binary operation 
        # repeat until end of line or ')'
            while True:
+                try:
+                    opStart=skipWS(operand1[2])
+                except:
+                    print("line=\n",line)
+                    print("defines=\n",self.defines)
                opStart=skipWS(operand1[2])
                if (opStart == len(line)) : # or (line[opStart] == ')'): # just primary
                    return operand1
@@ -485,7 +490,7 @@ class ImportVerilogParameters(object):
 # Macro substitution excluding the very first character
            if "`" in line [1:]:
                for define in self.defines:
-                    line.replace("`"+define,self.defines[define])
+                    line = line.replace("`"+define,self.defines[define])
            if line[0]== "`":
                tokens=line[1:].replace("\t"," ").split(" ",1) #second tokens
                for i in (1,2): 

--- a/py393/vrlg.py
+++ b/py393/vrlg.py
@@ -144,12 +144,13 @@ CMPRS_CBIT_CMODE_MONO6__RAW = str
 MCONTR_PHY_0BIT_DCI_RST = int
 SENSOR_FIFO_2DEPTH = int
 HIGH_PERFORMANCE_MODE__TYPE = str
+PXD_CAPACITANCE__RAW = str
 AFI_LO_ADDR64__TYPE = str
 CAMSYNC_TRIG_DELAY2 = int
 AFI_SIZE64 = int
 LOGGER_CONF_IMU_BITS = int
 SENS_JTAG_TCK__RAW = str
-MCNTRL_SCANLINE_MASK__TYPE = str
+HISPI_DIFF_TERM = str
 MCONTR_PHY_0BIT_SDRST_ACT = int
 SENSI2C_IBUF_LOW_PWR = str
 CLKOUT_DIV_PCLK2X__RAW = str
@@ -176,6 +177,7 @@ CLKFBOUT_PHASE_SENSOR = float
 DFLT_REFRESH_PERIOD = int
 MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
 NUM_CYCLES_20__TYPE = str
+CMPRS_CSAT_CB__RAW = str
 SENS_JTAG_PGMEN = int
 NUM_CYCLES_03__TYPE = str
 CMPRS_CBIT_RUN_BITS__TYPE = str
@@ -243,6 +245,7 @@ SENSI2C_CMD_RUN_PBITS__TYPE = str
 LOGGER_CONF_SYN_BITS__TYPE = str
 GPIO_ADDR__TYPE = str
 CAMSYNC_TRIG_SRC = int
+SENS_CTRL_GP1__RAW = str
 CLKOUT_DIV_PCLK__TYPE = str
 LOGGER_PAGE_IMU = int
 MEMCLK_IOSTANDARD__RAW = str
@@ -297,6 +300,7 @@ MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
 SENS_CTRL_RST_MMCM = int
 LOGGER_CONF_EN_BITS__TYPE = str
 CLKIN_PERIOD_PCLK__RAW = str
+MAX_TILE_WIDTH__TYPE = str
 SENS_LENS_POST_SCALE_MASK = int
 BUF_IPCLK2X_SENS1__RAW = str
 SENSOR_MODE_WIDTH__RAW = str
@@ -309,6 +313,7 @@ CMPRS_CBIT_CMODE_JP4DIFF__RAW = str
 CMPRS_AFIMUX_MASK__TYPE = str
 MCONTR_SENS_INC = int
 CAMSYNC_TRIG_PERIOD__TYPE = str
+CMPRS_STATUS_REG_BASE__RAW = str
 DFLT_DQS_PATTERN = int
 SENS_GAMMA_ADDR_DATA__RAW = str
 DLY_LANE1_IDELAY__RAW = str
@@ -335,7 +340,7 @@ DFLT_WBUF_DELAY__RAW = str
 CAMSYNC_POST_MAGIC__RAW = str
 MCNTRL_TEST01_CHN2_MODE__TYPE = str
 NUM_CYCLES_24__RAW = str
-NUM_CYCLES_13__RAW = str
+SENS_REFCLK_FREQUENCY__TYPE = str
 LOGGER_CONF_MSG__RAW = str
 MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
 LAST_FRAME_BITS__RAW = str
@@ -367,6 +372,7 @@ MCONTR_CMPRS_STATUS_BASE = int
 BUFFER_DEPTH32 = int
 SENS_CTRL_QUADRANTS__TYPE = str
 SENS_LENS_BY_MASK__RAW = str
+SENS_CTRL_GP0__TYPE = str
 DFLT_REFRESH_ADDR = int
 SENS_LENS_BX_MASK__TYPE = str
 TEST01_SUSPEND__RAW = str
@@ -374,6 +380,7 @@ SENS_GAMMA_HEIGHT01__TYPE = str
 CMPRS_HIFREQ_REG_INC = int
 STATUS_ADDR_MASK__TYPE = str
 MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
+NUM_CYCLES_13__RAW = str
 TEST01_START_FRAME = int
 RTC_SET_USEC__RAW = str
 LOGGER_CONF_SYN_BITS__RAW = str
@@ -402,6 +409,7 @@ NUM_CYCLES_21 = int
 FRAME_FULL_WIDTH__TYPE = str
 CAMSYNC_TRIG_DELAY2__TYPE = str
 CMDFRAMESEQ_REL__TYPE = str
+MAX_TILE_WIDTH__RAW = str
 PICKLE = str
 AFI_SIZE64__TYPE = str
 NUM_CYCLES_LOW_BIT__TYPE = str
@@ -421,9 +429,10 @@ CMPRS_CBIT_DCSUB_BITS__TYPE = str
 AXI_RD_ADDR_BITS__TYPE = str
 CAMSYNC_CHN_EN_BIT__TYPE = str
 CMDFRAMESEQ_ADDR_BASE__RAW = str
+MCONTR_LINTILE_SKIP_LATE__TYPE = str
 DEBUG_ADDR__RAW = str
 CONTROL_ADDR__RAW = str
-SENSI2C_CMD_RESET = int
+TILED_STARTY__RAW = str
 CMPRS_FRMT_MBCM1_BITS__TYPE = str
 SENS_CTRL_QUADRANTS_EN__RAW = str
 NUM_CYCLES_14__TYPE = str
@@ -519,6 +528,7 @@ MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
 HISTOGRAM_RADDR0__TYPE = str
 LOGGER_CONF_SYN_BITS = int
 NUM_CYCLES_19 = int
+SENS_CTRL_GP1__TYPE = str
 MCNTRL_TEST01_MASK__TYPE = str
 SENS_CTRL_QUADRANTS_WIDTH__RAW = str
 SENSOR_FIFO_DELAY__RAW = str
@@ -540,6 +550,7 @@ BUF_IPCLK_SENS1__TYPE = str
 FFCLK0_IFD_DELAY_VALUE__TYPE = str
 MCONTR_TOP_16BIT_ADDR = int
 CMPRS_TIMEOUT = int
+HISPI_IOSTANDARD__TYPE = str
 CMPRS_AFIMUX_RST = int
 NUM_CYCLES_18 = int
 SENS_LENS_POST_SCALE_MASK__RAW = str
@@ -555,10 +566,11 @@ CMPRS_CBIT_BAYER = int
 GPIO_PORTEN__RAW = str
 SLEW_CLK__TYPE = str
 MCONTR_PHY_0BIT_DLY_SET = int
-CLKFBOUT_DIV_REF__RAW = str
+HISPI_DIFF_TERM__TYPE = str
+SENSI2C_CMD_ACIVE_EARLY0 = int
 CMD_PAUSE_BITS = int
 CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
-SENSIO_STATUS_REG_REL = int
+HISPI_IOSTANDARD__RAW = str
 SENSI2C_TBL_SA__TYPE = str
 BUF_IPCLK_SENS3__TYPE = str
 MCNTRL_TILED_MODE = int
@@ -589,6 +601,7 @@ SENSIO_RADDR__TYPE = str
 CLKFBOUT_MULT_PCLK__TYPE = str
 CLK_ADDR__TYPE = str
 CMPRS_FORMAT = int
+SENSIO_STATUS_REG_REL = int
 FFCLK1_CAPACITANCE = str
 CMPRS_CBIT_CMODE_BITS__RAW = str
 CMPRS_TABLES = int
@@ -597,7 +610,7 @@ CMPRS_AFIMUX_RADDR0__RAW = str
 CAMSYNC_EN_BIT = int
 MCONTR_PHY_16BIT_PATTERNS__RAW = str
 HISTOGRAM_RAM_MODE = str
-SENS_REFCLK_FREQUENCY__TYPE = str
+FFCLK1_DQS_BIAS__TYPE = str
 SENS_GAMMA_MODE_EN__RAW = str
 SENSI2C_TBL_SA_BITS__TYPE = str
 DEBUG_ADDR = int
@@ -669,7 +682,7 @@ SENS_LENS_FAT0_OUT_MASK__TYPE = str
 SENSI2C_ABS_RADDR__TYPE = str
 MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
 WBUF_DLY_WLV__TYPE = str
-MEMBRIDGE_WIDTH64__TYPE = str
+HISPI_MSB_FIRST__TYPE = str
 MCONTR_TOP_16BIT_CHN_EN = int
 BUF_IPCLK2X_SENS1__TYPE = str
 DEFAULT_STATUS_MODE = int
@@ -722,6 +735,7 @@ AXI_RD_ADDR_BITS__RAW = str
 RTC_BITC_PREDIV = int
 SENS_SS_MOD_PERIOD__TYPE = str
 BUF_CLK1X_SYNC__RAW = str
+MCONTR_LINTILE_SKIP_LATE__RAW = str
 SENS_JTAG_PGMEN__TYPE = str
 MEMBRIDGE_LEN64__RAW = str
 MCONTR_LINTILE_EN = int
@@ -729,16 +743,19 @@ DFLT_REFRESH_ADDR__RAW = str
 GPIO_N = int
 MCONTR_ARBIT_ADDR_MASK__TYPE = str
 SENS_CTRL_MRST__TYPE = str
+SENS_CTRL_GP0 = int
+SENS_CTRL_GP1 = int
 FFCLK0_IBUF_LOW_PWR__TYPE = str
-FFCLK1_DQS_BIAS__TYPE = str
 SENS_GAMMA_RADDR = int
 NUM_CYCLES_14__RAW = str
-CMPRS_AFIMUX_MASK__RAW = str
+NUM_CYCLES_28__RAW = str
+CLKIN_PERIOD_SENSOR__RAW = str
 PHASE_WIDTH__TYPE = str
 CMPRS_JP4__RAW = str
 CMPRS_HIFREQ_REG_BASE__RAW = str
 SS_MOD_PERIOD = int
 MCONTR_CMPRS_BASE__TYPE = str
+HISPI_CAPACITANCE__TYPE = str
 TEST01_SUSPEND__TYPE = str
 SENS_LENS_POST_SCALE = int
 LOGGER_STATUS_REG_ADDR__TYPE = str
@@ -758,11 +775,13 @@ PHASE_WIDTH = int
 DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
 MCNTRL_SCANLINE_MASK = int
 CLKOUT_DIV_XCLK2X = int
+MCNTRL_TILED_TILE_WHS__TYPE = str
 MULT_SAXI_BSLOG3__TYPE = str
 CLKFBOUT_MULT__RAW = str
 CMPRS_STATUS_REG_INC__RAW = str
 HISTOGRAM_RADDR0__RAW = str
 STATUS_ADDR_MASK = int
+PXD_CAPACITANCE = str
 SENS_LENS_AY = int
 CMPRS_CBIT_CMODE_MONO6__TYPE = str
 HISTOGRAM_RAM_MODE__RAW = str
@@ -778,6 +797,7 @@ NEWPAR__TYPE = str
 CMPRS_AFIMUX_STATUS_CNTRL__TYPE = str
 LOGGER_CONFIG__RAW = str
 LD_DLY_LANE0_ODELAY__RAW = str
+PXD_CLK_DIV_BITS__RAW = str
 CMPRS_FRMT_LMARG_BITS = int
 CMDSEQMUX_ADDR = int
 CLKOUT_DIV_AXIHP = int
@@ -828,6 +848,7 @@ SENSIO_CTRL__TYPE = str
 SENSIO_WIDTH__RAW = str
 CMPRS_MASK__TYPE = str
 MEMBRIDGE_SIZE64__RAW = str
+HISPI_IFD_DELAY_VALUE__RAW = str
 MCNTRL_PS_STATUS_CNTRL = int
 CLKOUT_DIV_SYNC = int
 SS_MODE__TYPE = str
@@ -835,7 +856,9 @@ SENSI2C_STATUS__RAW = str
 CMPRS_MASK = int
 SENSI2C_CMD_ACIVE_EARLY0__RAW = str
 T_RFC__TYPE = str
+HISPI_IBUF_DELAY_VALUE__RAW = str
 MCONTR_LINTILE_NRESET__TYPE = str
+PXD_CLK_DIV__RAW = str
 SENS_NUM_SUBCHN__RAW = str
 CMPRS_CBIT_RUN_ENABLE__RAW = str
 BUF_IPCLK_SENS3__RAW = str
@@ -843,15 +866,16 @@ CLK_STATUS__RAW = str
 FRAME_WIDTH_BITS = int
 READ_PATTERN_OFFSET__TYPE = str
 MCONTR_BUF3_RD_ADDR__TYPE = str
-MAX_TILE_WIDTH__TYPE = str
+HISPI_DQS_BIAS__TYPE = str
 MCONTR_CMD_WR_ADDR = int
 SENSI2C_TBL_DLY_BITS__RAW = str
-REF_JITTER1 = float
+CMPRS_CSAT_CB__TYPE = str
 CMDSEQMUX_STATUS = int
 TILE_WIDTH = int
 GPIO_MASK = int
 DLY_LANE0_ODELAY = long
 NUM_XFER_BITS = int
+HISPI_NUMLANES__RAW = str
 MCNTRL_TEST01_STATUS_REG_CHN2_ADDR = int
 DLY_DQS_ODELAY__TYPE = str
 DLY_LANE0_ODELAY__RAW = str
@@ -874,6 +898,7 @@ TEST_INITIAL_BURST__TYPE = str
 NUM_CYCLES_19__RAW = str
 MCNTRL_PS_MASK__RAW = str
 CMPRS_CBIT_CMODE_JPEG20__TYPE = str
+HISPI_IBUF_LOW_PWR__TYPE = str
 CMPRS_TIMEOUT_BITS__RAW = str
 MEMBRIDGE_LO_ADDR64__RAW = str
 MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
@@ -904,7 +929,7 @@ LOGGER_MASK = int
 MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
 WINDOW_Y0 = int
 CAMSYNC_PRE_MAGIC__RAW = str
-MCNTRL_TILED_TILE_WHS__TYPE = str
+PXD_CLK_DIV_BITS = int
 SENSOR_CHN_EN_BIT = int
 LD_DLY_LANE0_ODELAY = int
 FFCLK1_IBUF_DELAY_VALUE__RAW = str
@@ -939,7 +964,7 @@ MCNTRL_TILED_WINDOW_WH = int
 CMDFRAMESEQ_MASK = int
 CLK_ADDR = int
 MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
-SENS_CTRL_EXT_CLK__TYPE = str
+NUM_XFER_BITS__RAW = str
 MCNTRL_TILED_WINDOW_STARTXY__RAW = str
 CMPRS_CSAT_CB_BITS__RAW = str
 CMPRS_CBIT_RUN__RAW = str
@@ -960,7 +985,7 @@ CMPRS_FRMT_MBRM1_BITS__TYPE = str
 MCNTRL_TILED_TILE_WHS__RAW = str
 SENS_REFCLK_FREQUENCY = float
 CMD_PAUSE_BITS__TYPE = str
-NUM_XFER_BITS__RAW = str
+SENS_CTRL_EXT_CLK__TYPE = str
 SENS_LENS_BY = int
 SENS_LENS_BX = int
 NUM_CYCLES_02__TYPE = str
@@ -1005,11 +1030,14 @@ MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
 CAMSYNC_EXTERNAL_BIT__RAW = str
 BUF_CLK1X_XCLK2X__RAW = str
 MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
+HISPI_IBUF_LOW_PWR__RAW = str
 SENSI2C_TBL_NBRD__TYPE = str
 SENSI2C_CMD_ACIVE_SDA = int
 MCONTR_PHY_0BIT_ADDR__TYPE = str
+PXD_CLK_DIV_BITS__TYPE = str
 MCONTR_CMPRS_INC__RAW = str
 CMPRS_HIFREQ_REG_INC__RAW = str
+PXD_CLK_DIV__TYPE = str
 SENSOR_DATA_WIDTH__RAW = str
 SENSI2C_TBL_DLY_BITS__TYPE = str
 MEMBRIDGE_MASK = int
@@ -1034,6 +1062,7 @@ ADDRESS_NUMBER__TYPE = str
 WSEL__TYPE = str
 FFCLK1_IBUF_DELAY_VALUE = str
 CMPRS_AFIMUX_CYCBITS__RAW = str
+MAX_TILE_WIDTH = int
 NUM_CYCLES_09__TYPE = str
 LD_DLY_LANE0_IDELAY__RAW = str
 FRAME_WIDTH_BITS__TYPE = str
@@ -1052,6 +1081,7 @@ MCNTRL_TILED_WINDOW_X0Y0 = int
 MCONTR_TOP_16BIT_REFRESH_PERIOD__RAW = str
 MULT_SAXI_WLOG__TYPE = str
 STATUS_2LSB_SHFT = int
+HISPI_IFD_DELAY_VALUE = str
 CMPRS_CBIT_CMODE_JP4DC = int
 NUM_CYCLES_08__TYPE = str
 NUM_CYCLES_LOW_BIT__RAW = str
@@ -1077,7 +1107,7 @@ LOGGER_PAGE_GPS__RAW = str
 SENS_PHASE_WIDTH__TYPE = str
 CMPRS_COLOR18__TYPE = str
 CMPRS_HIFREQ_REG_INC__TYPE = str
-MCNTRL_TILED_CHN2_ADDR = int
+PXD_CLK_DIV = int
 MCNTRL_TILED_STATUS_CNTRL = int
 NUM_CYCLES_29__RAW = str
 GPIO_SET_STATUS__TYPE = str
@@ -1104,9 +1134,10 @@ TILED_KEEP_OPEN__TYPE = str
 CMPRS_CBIT_RUN_RST__TYPE = str
 LOGGER_CONF_GPS_BITS__RAW = str
 CLK_STATUS_REG_ADDR = int
-SENS_PCLK_PERIOD__RAW = str
+CLK_DIV_PHASE__TYPE = str
 MULT_SAXI_BSLOG0__RAW = str
 PXD_DRIVE__RAW = str
+CLKFBOUT_USE_FINE_PS__RAW = str
 GPIO_SET_PINS = int
 SENSOR_CHN_EN_BIT__TYPE = str
 LOGGER_BIT_DURATION = int
@@ -1120,11 +1151,13 @@ SENSI2C_CTRL_RADDR__TYPE = str
 SENSIO_ADDR_MASK__RAW = str
 LOGGER_CONF_EN_BITS = int
 NUM_CYCLES_22__RAW = str
+PXD_CAPACITANCE__TYPE = str
 CAMSYNC_POST_MAGIC = int
 PXD_IBUF_LOW_PWR__RAW = str
 PXD_DRIVE = int
 MULT_SAXI_BSLOG2__RAW = str
 CLK_CNTRL__TYPE = str
+HISPI_NUMLANES__TYPE = str
 GPIO_MASK__RAW = str
 DFLT_REFRESH_ADDR__TYPE = str
 SENS_GAMMA_MODE_REPET__TYPE = str
@@ -1136,12 +1169,14 @@ LOGGER_PERIOD__TYPE = str
 WSEL = int
 SENS_REFCLK_FREQUENCY__RAW = str
 LOGGER_STATUS_MASK__TYPE = str
+HISPI_IOSTANDARD = str
 LOGGER_CONF_IMU__RAW = str
 CMPRS_CBIT_CMODE_JP4DC__RAW = str
 MCNTRL_TEST01_CHN3_MODE__RAW = str
 MCNTRL_TEST01_CHN1_MODE__TYPE = str
 SENS_SYNC_FBITS__TYPE = str
 MCONTR_TOP_0BIT_ADDR_MASK = int
+HISPI_IBUF_DELAY_VALUE__TYPE = str
 CMDFRAMESEQ_REL = int
 CAMSYNC_POST_MAGIC__TYPE = str
 NUM_CYCLES_29__TYPE = str
@@ -1194,11 +1229,13 @@ CMPRS_CORING_BITS__TYPE = str
 STATUS_DEPTH__TYPE = str
 SENSI2C_TBL_RAH__TYPE = str
 CMPRS_AFIMUX_CYCBITS__TYPE = str
+HISPI_MSB_FIRST = int
 SENS_SS_EN__RAW = str
 SENS_LENS_ADDR_MASK = int
 SENSOR_CTRL_RADDR__TYPE = str
 CMPRS_CBIT_FRAMES_SINGLE__RAW = str
 CLKOUT_DIV_PCLK = int
+MCNTRL_SCANLINE_MASK__TYPE = str
 MCONTR_PHY_0BIT_DLY_SET__TYPE = str
 PXD_IOSTANDARD__TYPE = str
 MCONTR_PHY_STATUS_REG_ADDR = int
@@ -1261,6 +1298,7 @@ HISTOGRAM_RADDR2 = int
 HISTOGRAM_RADDR3 = int
 MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
 SENS_LENS_AY_MASK__TYPE = str
+SENS_CTRL_IGNORE_EMBED__RAW = str
 READ_BLOCK_OFFSET__TYPE = str
 CONTROL_ADDR_MASK__RAW = str
 LD_DLY_CMDA__RAW = str
@@ -1270,6 +1308,7 @@ MCNTRL_TEST01_CHN2_MODE = int
 MCNTRL_TILED_WINDOW_WH__TYPE = str
 SS_MOD_PERIOD__RAW = str
 CMPRS_NUM_AFI_CHN__RAW = str
+MEMBRIDGE_WIDTH64__TYPE = str
 MULT_SAXI_ADV_RD = int
 MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
 DLY_PHASE__TYPE = str
@@ -1303,7 +1342,7 @@ CMPRS_COLOR_SATURATION__RAW = str
 AXI_RD_ADDR_BITS = int
 LD_DLY_LANE1_ODELAY__TYPE = str
 CMPRS_STATUS_CNTRL__RAW = str
-TEST01_START_FRAME__TYPE = str
+MCONTR_LINTILE_SKIP_LATE = int
 SENS_CTRL_ARO = int
 LOGGER_CONF_DBG_BITS__TYPE = str
 RTC_SEC_USEC_ADDR__TYPE = str
@@ -1322,6 +1361,7 @@ TABLE_QUANTIZATION_INDEX = int
 NUM_CYCLES_04__TYPE = str
 WSEL__RAW = str
 CLKOUT_DIV_XCLK__TYPE = str
+SENS_CTRL_IGNORE_EMBED = int
 RTC_MASK__TYPE = str
 MCNTRL_TILED_PENDING_CNTR_BITS = int
 NUM_CYCLES_00__TYPE = str
@@ -1334,6 +1374,7 @@ HIGH_PERFORMANCE_MODE = str
 DQTRI_LAST__RAW = str
 MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
 DFLT_DQM_PATTERN = int
+HISPI_NUMLANES = int
 SENSI2C_CMD_RUN = int
 CLKOUT_DIV_AXIHP__TYPE = str
 CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
@@ -1361,6 +1402,7 @@ MCONTR_WR_MASK = int
 CMPRS_FRMT_MBCM1 = int
 MEMBRIDGE_STATUS_CNTRL__TYPE = str
 GPIO_IOSTANDARD__TYPE = str
+CLKFBOUT_USE_FINE_PS__TYPE = str
 CMPRS_FRMT_LMARG = int
 FFCLK0_IBUF_DELAY_VALUE__TYPE = str
 CMPRS_TIMEOUT__RAW = str
@@ -1382,7 +1424,6 @@ SENSIO_CTRL = int
 MULT_SAXI_MASK__TYPE = str
 SENSI2C_CMD_ACIVE_SDA__TYPE = str
 CLKIN_PERIOD_SYNC__RAW = str
-SENS_PCLK_PERIOD = float
 SCANLINE_STARTY__RAW = str
 GPIO_ADDR = int
 SENS_SYNC_MINBITS__RAW = str
@@ -1390,7 +1431,7 @@ SENS_SS_MOD_PERIOD__RAW = str
 COLADDR_NUMBER__TYPE = str
 CAMSYNC_CHN_EN_BIT__RAW = str
 LOGGER_PAGE_MSG = int
-MCONTR_LINTILE_WRITE__TYPE = str
+SENS_HIGH_PERFORMANCE_MODE = str
 WINDOW_X0 = int
 INITIALIZE_OFFSET__TYPE = str
 SENSOR_FIFO_DELAY__TYPE = str
@@ -1484,7 +1525,7 @@ SENSI2C_TBL_NBRD = int
 CMPRS_CBIT_BAYER_BITS = int
 PXD_SLEW__RAW = str
 MULT_SAXI_STATUS_REG = int
-CMPRS_STATUS_REG_BASE__RAW = str
+CLKIN_PERIOD_SENSOR__TYPE = str
 MEMCLK_IFD_DELAY_VALUE__RAW = str
 SENS_LENS_BY__RAW = str
 MCNTRL_PS_CMD__TYPE = str
@@ -1531,11 +1572,11 @@ CLK_STATUS__TYPE = str
 CMPRS_COLOR20__TYPE = str
 T_REFI__TYPE = str
 MCONTR_CMD_WR_ADDR__TYPE = str
-RTC_MASK = int
 CLKFBOUT_MULT_SENSOR__RAW = str
 CMPRS_CSAT_CR_BITS = int
 HIST_SAXI_ADDR_REL__TYPE = str
 LOGGER_CONFIG__TYPE = str
+MCNTRL_TEST01_MASK = int
 TEST01_NEXT_PAGE__RAW = str
 HIST_SAXI_MODE_ADDR_MASK__RAW = str
 CMPRS_AFIMUX_EN__RAW = str
@@ -1576,7 +1617,7 @@ CLKFBOUT_MULT_REF__RAW = str
 DLY_LD_MASK__RAW = str
 CMDFRAMESEQ_RST_BIT__TYPE = str
 LD_DLY_LANE1_ODELAY = int
-NUM_CYCLES_28__RAW = str
+CMPRS_AFIMUX_MASK__RAW = str
 MCNTRL_TILED_WINDOW_X0Y0__RAW = str
 SENS_GAMMA_MODE_PAGE__TYPE = str
 CMPRS_COLOR_SATURATION__TYPE = str
@@ -1585,6 +1626,7 @@ CLKFBOUT_DIV_REF = int
 CMPRS_AFIMUX_SA_LEN = int
 SENS_CTRL_QUADRANTS_EN__TYPE = str
 MCNTRL_PS_EN_RST__RAW = str
+HISPI_IFD_DELAY_VALUE__TYPE = str
 CMPRS_CBIT_BAYER_BITS__RAW = str
 GPIO_IOSTANDARD__RAW = str
 MEMBRIDGE_MASK__RAW = str
@@ -1600,7 +1642,7 @@ MCONTR_PHY_0BIT_CMDA_EN = int
 CMPRS_AFIMUX_WIDTH__RAW = str
 BUF_CLK1X_PCLK2X = str
 MCNTRL_TEST01_CHN4_MODE = int
-MAX_TILE_WIDTH = int
+HISPI_DQS_BIAS = str
 TABLE_FOCUS_INDEX = int
 CMPRS_CBIT_RUN_STANDALONE__RAW = str
 CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = int
@@ -1608,7 +1650,6 @@ DFLT_DQ_TRI_OFF_PATTERN__RAW = str
 CMPRS_CBIT_DCSUB = int
 CMPRS_CBIT_CMODE_JP4DIFF = int
 MULT_SAXI_CNTRL_MASK__TYPE = str
-SENS_PCLK_PERIOD__TYPE = str
 INITIALIZE_OFFSET__RAW = str
 CMD_DONE_BIT__RAW = str
 DEBUG_STATUS_REG_ADDR__RAW = str
@@ -1698,6 +1739,7 @@ DEBUG_CMD_LATENCY__RAW = str
 CMPRS_CBIT_CMODE__TYPE = str
 LOGGER_STATUS_MASK = int
 DFLT_DQ_TRI_ON_PATTERN__RAW = str
+HISPI_CAPACITANCE = str
 CONTROL_ADDR_MASK = int
 LOGGER_PERIOD = int
 MCONTR_BUF0_WR_ADDR = int
@@ -1709,6 +1751,7 @@ CMDFRAMESEQ_RUN_BIT__TYPE = str
 MCNTRL_TILED_STATUS_CNTRL__TYPE = str
 SENSI2C_CTRL__RAW = str
 MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
+SENS_CTRL_GP0__RAW = str
 MCONTR_BUF2_WR_ADDR__RAW = str
 MULT_SAXI_BSLOG0 = int
 MULT_SAXI_BSLOG1 = int
@@ -1727,6 +1770,7 @@ MCNTRL_PS_MASK = int
 SENSI2C_STATUS__TYPE = str
 CMPRS_CSAT_CB_BITS = int
 SENSI2C_TBL_NBRD__RAW = str
+HISPI_IBUF_DELAY_VALUE = str
 SENSI2C_IOSTANDARD = str
 GPIO_IOSTANDARD = str
 MCNTRL_SCANLINE_WINDOW_X0Y0__RAW = str
@@ -1734,7 +1778,7 @@ SENS_SYNC_MINPER__TYPE = str
 SENSI2C_CTRL_RADDR__RAW = str
 SENS_SYNC_LATE_DFLT__RAW = str
 MCONTR_LINTILE_DIS_NEED__RAW = str
-SENS_HIGH_PERFORMANCE_MODE = str
+MCONTR_LINTILE_WRITE__TYPE = str
 CAMSYNC_MASTER_BIT__RAW = str
 MEMBRIDGE_STATUS_CNTRL = int
 MCNTRL_TEST01_STATUS_REG_CHN3_ADDR = int
@@ -1773,6 +1817,7 @@ SENS_GAMMA_HEIGHT01 = int
 RTC_SET_SEC__RAW = str
 MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
 SS_MODE__RAW = str
+SENS_CTRL_IGNORE_EMBED__TYPE = str
 MCNTRL_SCANLINE_CHN3_ADDR = int
 NUM_CYCLES_26__RAW = str
 DEFAULT_STATUS_MODE__RAW = str
@@ -1836,7 +1881,7 @@ DFLT_REFRESH_PERIOD__RAW = str
 SENS_REF_JITTER1__TYPE = str
 SENS_LENS_RADDR__RAW = str
 MCONTR_PHY_0BIT_DCI_RST__TYPE = str
-MAX_TILE_WIDTH__RAW = str
+HISPI_DQS_BIAS__RAW = str
 FFCLK1_DQS_BIAS = str
 MCONTR_LINTILE_WRITE = int
 TILE_VSTEP__TYPE = str
@@ -1844,7 +1889,7 @@ MCONTR_PHY_STATUS_CNTRL__RAW = str
 DLY_LANE0_DQS_WLV_IDELAY = long
 MCNTRL_SCANLINE_STATUS_CNTRL = int
 CMDSEQMUX_MASK__TYPE = str
-TILED_STARTY__RAW = str
+SENSI2C_CMD_RESET = int
 SENSI2C_TBL_NABRD__TYPE = str
 NUM_CYCLES_01__RAW = str
 WINDOW_HEIGHT__RAW = str
@@ -1854,6 +1899,7 @@ SENSI2C_CTRL_MASK = int
 PHASE_CLK2X_PCLK__RAW = str
 MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__TYPE = str
 MCONTR_TOP_0BIT_ADDR__RAW = str
+HISPI_IBUF_LOW_PWR = str
 LOGGER_CONF_DBG__TYPE = str
 AFI_SIZE64__RAW = str
 SENSI2C_TBL_RNWREG = int
@@ -1861,7 +1907,7 @@ STATUS_PSHIFTER_RDY_MASK = int
 SENSI2C_CMD_FIFO_RD__TYPE = str
 SENS_LENS_C_MASK__TYPE = str
 MCNTRL_SCANLINE_FRAME_LAST__RAW = str
-CMPRS_CSAT_CB__RAW = str
+CLKFBOUT_DIV_REF__RAW = str
 SENS_PHASE_WIDTH__RAW = str
 SENS_REF_JITTER2__TYPE = str
 FFCLK0_IBUF_LOW_PWR = str
@@ -1870,6 +1916,7 @@ CMPRS_AFIMUX_MODE__TYPE = str
 DQTRI_FIRST__TYPE = str
 MCNTRL_SCANLINE_FRAME_SIZE__RAW = str
 CMPRS_CBIT_CMODE_BITS = int
+TEST01_START_FRAME__TYPE = str
 MULT_SAXI_CNTRL_ADDR__RAW = str
 FFCLK1_IOSTANDARD__TYPE = str
 CAMSYNC_TRIG_DELAY2__RAW = str
@@ -1896,6 +1943,7 @@ SENS_HIGH_PERFORMANCE_MODE__TYPE = str
 MCONTR_LINTILE_KEEP_OPEN__TYPE = str
 NUM_CYCLES_15__RAW = str
 DLY_DQ_IDELAY = long
+CLKFBOUT_USE_FINE_PS = int
 MCNTRL_TEST01_ADDR__TYPE = str
 CMPRS_STATUS_REG_BASE = int
 MCONTR_LINTILE_NRESET = int
@@ -1912,7 +1960,7 @@ MCONTR_LINTILE_SINGLE__TYPE = str
 DLY_DQ_IDELAY__RAW = str
 SENSOR_CTRL_RADDR__RAW = str
 CMPRS_MONO16 = int
-CMPRS_CSAT_CB__TYPE = str
+REF_JITTER1 = float
 SENSI2C_TBL_DLY = int
 SENSIO_STATUS__RAW = str
 CLKIN_PERIOD_AXIHP__RAW = str
@@ -1933,7 +1981,9 @@ SENS_GAMMA_MODE_EN = int
 MCONTR_BUF3_RD_ADDR = int
 NUM_CYCLES_28__TYPE = str
 NUM_CYCLES_31__TYPE = str
+HISPI_CAPACITANCE__RAW = str
 CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
+HISPI_DIFF_TERM__RAW = str
 BUF_IPCLK_SENS2__TYPE = str
 SENS_GAMMA_BUFFER = int
 CMDFRAMESEQ_ABS__TYPE = str
@@ -2015,7 +2065,6 @@ LOGGER_ADDR__TYPE = str
 NUM_CYCLES_15__TYPE = str
 MCNTRL_TILED_MODE__RAW = str
 CLKOUT_DIV_AXIHP__RAW = str
-CLK_DIV_PHASE__TYPE = str
 NUM_CYCLES_23__TYPE = str
 MCNTRL_TILED_MODE__TYPE = str
 MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
@@ -2041,8 +2090,8 @@ MCONTR_SENS_INC__RAW = str
 MULT_SAXI_WLOG__RAW = str
 TILE_WIDTH__RAW = str
 CMPRS_FORMAT__RAW = str
-SENSI2C_CMD_ACIVE_EARLY0 = int
+RTC_MASK = int
-MCNTRL_TEST01_MASK = int
+CLKIN_PERIOD_SENSOR = float
 MEMCLK_IBUF_DELAY_VALUE__TYPE = str
 SENS_GAMMA_CTRL__TYPE = str
 HIST_CONFIRM_WRITE__RAW = str
@@ -2068,6 +2117,7 @@ SENS_GAMMA_MODE_EN__TYPE = str
 FRAME_START_ADDRESS__TYPE = str
 CLK_MASK = int
 MCONTR_BUF4_WR_ADDR__TYPE = str
+MCNTRL_TILED_CHN2_ADDR = int
 CAMSYNC_MASK = int
 COLADDR_NUMBER__RAW = str
 STATUS_SEQ_SHFT = int
@@ -2109,6 +2159,7 @@ MCONTR_ARBIT_ADDR__RAW = str
 MCONTR_LINTILE_EN__TYPE = str
 SENSI2C_REL_RADDR__TYPE = str
 GPIO_DRIVE = int
+HISPI_MSB_FIRST__RAW = str
 SENS_LENS_SCALES = int
 CONTROL_ADDR_MASK__TYPE = str
 MCONTR_PHY_STATUS_REG_ADDR__RAW = str

--- a/py393/x393_mcntrl_adjust.py
+++ b/py393/x393_mcntrl_adjust.py
@@ -1361,6 +1361,8 @@ class X393McntrlAdjust(object):
            y=a*phase+b
            y0=y
            #find the lowest approximate solution to consider
+            if (quiet <2):
+                print("phase= %d, y=%f, variantStep=%f"%(phase,y,variantStep))
            if y0 > (-max_dly_err):
                while (y0 >= (variantStep-max_dly_err)):
                    y0 -= variantStep
@@ -1369,6 +1371,8 @@ class X393McntrlAdjust(object):
                while (y0<(-max_dly_err)):
                    y0 += variantStep
                    periods += 1
+            if (quiet <2):
+                print("y0=%f"%(y0))
            dly_min= max(0,int(y0-4.5))
            dly_max= min(max_lin_dly,int(y0+5.5))
            dly_to_try=[]

--- a/py393/x393_mcntrl_timing.py
+++ b/py393/x393_mcntrl_timing.py
@@ -88,9 +88,15 @@ class X393McntrlTiming(object):
        if phase is None:
            phase= vrlg.get_default("DLY_PHASE") 
        vrlg.DLY_PHASE=phase & ((1<<vrlg.PHASE_WIDTH)-1)
-        if quiet<2:
+        if vrlg.CLKFBOUT_USE_FINE_PS:
-            print("SET CLOCK PHASE=0x%x"%(vrlg.DLY_PHASE))
+            phase_value = (-vrlg.DLY_PHASE) & ((1<<vrlg.PHASE_WIDTH)-1)
-        self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE,vrlg.DLY_PHASE) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address
+            if quiet<2:
+                print("SET INVERTED CLOCK PHASE=0x%x (actual value is 0x%x)"%(vrlg.DLY_PHASE, phase_value))
+            self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE, phase_value) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address
+        else:    
+            if quiet<2:
+                print("SET CLOCK PHASE=0x%x"%(vrlg.DLY_PHASE))
+            self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE,vrlg.DLY_PHASE) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address
        self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0)
 #        self.target_phase = phase
        if wait_phase_en:
@@ -106,7 +112,10 @@ class X393McntrlTiming(object):
        <wait_seq> read and re-send status request to make sure status reflects new data (just for testing, too fast for Python)
        Returns 1 if success, 0 if timeout
        """
-        patt = 0x3000000 | vrlg.DLY_PHASE
+        if vrlg.CLKFBOUT_USE_FINE_PS:
+            patt = 0x3000000 | ((-vrlg.DLY_PHASE) & 0xff)
+        else:    
+            patt = 0x3000000 | vrlg.DLY_PHASE
        mask = 0x3000100
        if check_phase_value:
            mask |= 0xff
@@ -452,6 +461,9 @@ class X393McntrlTiming(object):
        Wait until clock phase shifter is ready
        """
        data=self.x393_axi_tasks.read_status(vrlg.MCONTR_PHY_STATUS_REG_ADDR)
+        expected_phase = vrlg.DLY_PHASE
+        if (vrlg.CLKFBOUT_USE_FINE_PS):
+            expected_phase = (-expected_phase) & 0xff;
        while (((data & vrlg.STATUS_PSHIFTER_RDY_MASK) == 0) or (((data ^ vrlg.DLY_PHASE) & 0xff) != 0)):
            data=self.x393_axi_tasks.read_status(vrlg.MCONTR_PHY_STATUS_REG_ADDR)
            if self.DRY_MODE: break

--- a/system_defines.vh
+++ b/system_defines.vh
@@ -9,7 +9,17 @@
 //  `define USE_PCLK2X
 //  `define USE_XCLK2X
 //  `define DEBUG_RING 1
+//  `define MCLK_VCO_MULT 16
+// DDR3 memory speed grade and density
+    `define sg25 1
+//  `define sg15E  1
+//  `define sg187E  1
+  `define den4096Mb 1  
+  `define MCLK_VCO_MULT 16
+//  `define MCLK_VCO_MULT 18
+//  `define MCLK_VCO_MULT 20
  `define MEMBRIDGE_DEBUG_WRITE 1
 // Enviroment-dependent options
  `ifdef IVERILOG

--- a/util_modules/fifo_1cycle.v
+++ b/util_modules/fifo_1cycle.v
@@ -30,7 +30,7 @@ module fifo_1cycle
    (
  input                   rst,      // reset, active high
  input                   clk,      // clock - positive edge
-  input                   srst,     // sync reset
+  input                   sync_rst, // sync reset
  input                   we,       // write enable
  input                   re,       // read enable
  input  [DATA_WIDTH-1:0] data_in,  // input data
@@ -60,22 +60,22 @@ module fifo_1cycle
    assign next_fill = fill[DATA_DEPTH-1:0]+((we && ~re)?1:((~we && re)?-1:0));
    always @ (posedge  clk or posedge  rst) begin
-      if      (rst)  fill <= 0;
+      if      (rst)      fill <= 0;
-      else if (srst) fill <= 0;
+      else if (sync_rst) fill <= 0;
-      else           fill <= next_fill;
+      else               fill <= next_fill;
-      if      (rst)  wa <= 0;
+      if      (rst)      wa <= 0;
-      else if (srst) wa <= 0;
+      else if (sync_rst) wa <= 0;
-      else if (we)   wa <= wa+1;
+      else if (we)       wa <= wa+1;
-      if      (rst)  ra <=  0;
+      if      (rst)      ra <=  0;
-      else if (srst) ra <=  0;
+      else if (sync_rst) ra <=  0;
-      else if (re)   ra <= ra+1;
+      else if (re)       ra <= ra+1;
-      else if (fill==0) ra <= wa; // Just recover from bit errors
+      else if (fill==0)  ra <= wa; // Just recover from bit errors
-      if      (rst)  nempty <= 0;
+      if      (rst)      nempty <= 0;
-      else if (srst) nempty <= 0;
+      else if (sync_rst) nempty <= 0;
-      else           nempty <= (next_fill!=0);
+      else               nempty <= (next_fill!=0);
 `ifdef DEBUG_FIFO

--- a/util_modules/fifo_same_clock.v
+++ b/util_modules/fifo_same_clock.v
@@ -55,7 +55,7 @@ module fifo_same_clock
    reg  [DATA_WIDTH-1:0] outreg;
    reg  [DATA_DEPTH-1:0] ra;
    reg  [DATA_DEPTH-1:0] wa;
-    wire [DATA_DEPTH-1:0] next_fill;
+//    wire [DATA_DEPTH-1:0] next_fill;
    reg  wem;
    wire rem;
    reg  out_full=0; //output register full
@@ -63,7 +63,7 @@ module fifo_same_clock
    reg  ram_nempty;
-    assign next_fill = fill[DATA_DEPTH-1:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
+//    assign next_fill = fill[DATA_DEPTH-1:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
    assign rem= ram_nempty && (re || !out_full); 
    assign data_out=outreg;
    assign nempty=out_full;
@@ -73,9 +73,11 @@ module fifo_same_clock
 `endif
    always @ (posedge  clk or posedge  rst) begin
-      if      (rst)      fill <= 0;
+      if      (rst)          fill <= 0;
-      else if (sync_rst) fill <= 0;
+      else if (sync_rst)     fill <= 0;
-      else               fill <= next_fill;
+//      else               fill <= next_fill;
+      else if ( wem && ~rem) fill <= fill + 1;
+      else if (~wem &&  rem) fill <= fill - 1;
      if (rst)           wem <= 0;
      else if (sync_rst) wem <= 0;
@@ -83,7 +85,9 @@ module fifo_same_clock
      if   (rst)         ram_nempty <= 0;
      else if (sync_rst) ram_nempty <= 0;
-      else               ram_nempty <= (next_fill != 0);
+//      else               ram_nempty <= (next_fill != 0);
+//      else               ram_nempty <= wem || (|fill[DATA_DEPTH-1:1]) || (fill[0] && !rem);
+      else               ram_nempty <= (|fill[DATA_DEPTH-1:1]) || (fill[0] && wem) || ((fill[0] || wem) && !rem) ;
      if (rst)           wa <= 0;
      else if (sync_rst) wa <= 0;

--- a/util_modules/status_router16.v
+++ b/util_modules/status_router16.v
@@ -84,7 +84,9 @@ module  status_router16(
    wire   [1:0] rq_int;
    wire   [1:0] start_int;  // only for the first cycle, combinatorial
-    status_router2 status_router2_top_i (
+    status_router2 #(
+        .FIFO_TYPE ("TWO_CYCLE") //= "ONE_CYCLE" // higher latency, but easier timing - use on some levels (others - default "ONE_CYCLE")
+    ) status_router2_top_i (
        .rst       (rst), // input
        .clk       (clk), // input
        .srst      (srst), // input

--- a/util_modules/status_router2.v
+++ b/util_modules/status_router2.v
@@ -22,7 +22,9 @@
 `timescale 1ns/1ps
 `include "system_defines.vh" 
 //`define DEBUG_FIFO 1
-module  status_router2 (
+module  status_router2 #(
+    parameter FIFO_TYPE = "ONE_CYCLE" // "TWO_CYCLE"
+)(
    input        rst,
    input        clk,
    input        srst,      // sync reset
@@ -99,50 +101,98 @@ module  status_router2 (
    end
 /* fifo_same_clock has currently latency of 2 cycles, use smth. faster here? - fifo_1cycle (but it has unregistered data output) */
-    fifo_1cycle #(
+    generate
-        .DATA_WIDTH(9),
+        if (FIFO_TYPE == "ONE_CYCLE") begin
-        .DATA_DEPTH(4) // 16
+            fifo_1cycle #(
-    ) fifo_in0_i (
+                .DATA_WIDTH(9),
-        .rst       (1'b0), // rst), // input
+                .DATA_DEPTH(4) // 16
-        .clk       (clk), // input
+            ) fifo_in0_i (
-        .srst      (srst), // input
+                .rst       (1'b0),                                // rst), // input
-        .we        (start_rcv[0] || rcv_rest_r[0]), // input
+                .clk       (clk),                                 // input
-        .re        (fifo_re[0]), // input
+                .sync_rst  (srst),                                // input
-        .data_in   ({rcv_rest_r[0] & ~rq_in[0], db_in0}), // input[8:0] MSB marks last byte
+                .we        (start_rcv[0] || rcv_rest_r[0]),       // input
-        .data_out  ({fifo_last_byte[0],fifo0_out}), // output[8:0]
+                .re        (fifo_re[0]),                          // input
-        .nempty    (fifo_nempty_pre[0]), // output
+                .data_in   ({rcv_rest_r[0] & ~rq_in[0], db_in0}), // input[8:0] MSB marks last byte
-        .half_full (fifo_half_full[0]) // output reg 
+                .data_out  ({fifo_last_byte[0],fifo0_out}),       // output[8:0]
-`ifdef DEBUG_FIFO
+                .nempty    (fifo_nempty_pre[0]),                  // output reg
-        ,.under(), // output reg 
+                .half_full (fifo_half_full[0])                    // output reg 
-        .over(), // output reg 
+        `ifdef DEBUG_FIFO
-        .wcount(), // output[3:0] reg 
+                ,.under(),     // output reg 
-        .rcount(), // output[3:0] reg 
+                .over(),       // output reg 
-        .num_in_fifo() // output[3:0]
+                .wcount(),     // output[3:0] reg 
-`endif         
+                .rcount(),     // output[3:0] reg 
-    );
+                .num_in_fifo() // output[3:0]
+        `endif         
-    fifo_1cycle #(
+            );
-        .DATA_WIDTH(9),
-        .DATA_DEPTH(4) // 16
+            fifo_1cycle #(
-    ) fifo_in1_i (
+                .DATA_WIDTH(9),
-        .rst       (1'b0), // rst), // input
+                .DATA_DEPTH(4) // 16
-        .clk       (clk), // input
+            ) fifo_in1_i (
-        .srst      (srst), // input
+                .rst       (1'b0),                                // rst), // input
-        .we        (start_rcv[1] || rcv_rest_r[1]), // input
+                .clk       (clk),                                 // input
-        .re        (fifo_re[1]), // input
+                .sync_rst  (srst),                                // input
-        .data_in   ({rcv_rest_r[1] & ~rq_in[1], db_in1}), // input[8:0] MSB marks last byte
+                .we        (start_rcv[1] || rcv_rest_r[1]),       // input
-        .data_out  ({fifo_last_byte[1],fifo1_out}), // output[8:0]
+                .re        (fifo_re[1]),                          // input
-        .nempty    (fifo_nempty_pre[1]), // output
+                .data_in   ({rcv_rest_r[1] & ~rq_in[1], db_in1}), // input[8:0] MSB marks last byte
-        .half_full (fifo_half_full[1]) // output reg 
+                .data_out  ({fifo_last_byte[1],fifo1_out}),       // output[8:0]
-`ifdef DEBUG_FIFO
+                .nempty    (fifo_nempty_pre[1]),                  // output reg
-        ,.under(), // output reg 
+                .half_full (fifo_half_full[1])                    // output reg 
-        .over(), // output reg 
+        `ifdef DEBUG_FIFO
-        .wcount(), // output[3:0] reg 
+                ,.under(),     // output reg 
-        .rcount(), // output[3:0] reg 
+                .over(),       // output reg 
-        .num_in_fifo() // output[3:0]
+                .wcount(),     // output[3:0] reg 
-`endif         
+                .rcount(),     // output[3:0] reg 
-    );
+                .num_in_fifo() // output[3:0]
+        `endif         
+            );
+        end else begin
+            fifo_same_clock #(
+                .DATA_WIDTH(9),
+                .DATA_DEPTH(4) // 16
+            ) fifo_in0_i (
+                .rst       (1'b0),                                // rst), // input
+                .clk       (clk),                                 // input
+                .sync_rst  (srst),                                // input
+                .we        (start_rcv[0] || rcv_rest_r[0]),       // input
+                .re        (fifo_re[0]),                          // input
+                .data_in   ({rcv_rest_r[0] & ~rq_in[0], db_in0}), // input[8:0] MSB marks last byte
+                .data_out  ({fifo_last_byte[0],fifo0_out}),       // output[8:0]
+                .nempty    (fifo_nempty_pre[0]),                  // output reg
+                .half_full (fifo_half_full[0])                    // output reg 
+        `ifdef DEBUG_FIFO
+                ,.under(),     // output reg 
+                .over(),       // output reg 
+                .wcount(),     // output[3:0] reg 
+                .rcount(),     // output[3:0] reg 
+                .num_in_fifo() // output[3:0]
+        `endif         
+            );
+            fifo_same_clock #(
+                .DATA_WIDTH(9),
+                .DATA_DEPTH(4) // 16
+            ) fifo_in1_i (
+                .rst       (1'b0),                                // rst), // input
+                .clk       (clk),                                 // input
+                .sync_rst  (srst),                                // input
+                .we        (start_rcv[1] || rcv_rest_r[1]),       // input
+                .re        (fifo_re[1]),                          // input
+                .data_in   ({rcv_rest_r[1] & ~rq_in[1], db_in1}), // input[8:0] MSB marks last byte
+                .data_out  ({fifo_last_byte[1],fifo1_out}),       // output[8:0]
+                .nempty    (fifo_nempty_pre[1]),                  // output reg
+                .half_full (fifo_half_full[1])                    // output reg 
+        `ifdef DEBUG_FIFO
+                ,.under(),     // output reg 
+                .over(),       // output reg 
+                .wcount(),     // output[3:0] reg 
+                .rcount(),     // output[3:0] reg 
+                .num_in_fifo() // output[3:0]
+        `endif         
+            );
+        end
+    endgenerate
 // one car per green (round robin priority)
 // start sending out with  with one cycle latency - now 2 cycles because of the FIFO

--- a/util_modules/status_router4.v
+++ b/util_modules/status_router4.v
@@ -47,7 +47,9 @@ module  status_router4(
    wire   [1:0] rq_int;
    wire   [1:0] start_int;  // only for the first cycle, combinatorial
-    status_router2 status_router2_top_i (
+    status_router2  #(
+        .FIFO_TYPE ("TWO_CYCLE") //= "ONE_CYCLE" // higher latency, but easier timing - use on some levels (others - default "ONE_CYCLE")
+    ) status_router2_top_i (
        .rst       (rst), // input
        .clk       (clk), // input
        .srst      (srst), // input

--- a/util_modules/status_router8.v
+++ b/util_modules/status_router8.v
@@ -59,7 +59,9 @@ module  status_router8(
    wire   [1:0] rq_int;
    wire   [1:0] start_int;  // only for the first cycle, combinatorial
-    status_router2 status_router2_top_i (
+    status_router2 #(
+        .FIFO_TYPE ("ONE_CYCLE") //= "ONE_CYCLE" // higher latency, but easier timing - use on some levels (others - default "ONE_CYCLE")
+    ) status_router2_top_i  (
        .rst       (rst), // input
        .clk       (clk), // input
        .srst      (srst), // input

--- a/util_modules/sync_resets.v
+++ b/util_modules/sync_resets.v
@@ -32,7 +32,8 @@ module  sync_resets#(
 );
    reg                 en_locked=0; // mostly for simulation, locked[0] is 1'bx until the first clock[0] pulse
    wire    [WIDTH-1:0] rst_w;  // resets matching input clocks
-    wire                rst_early_master;
+    wire                rst_early_master_w;
+    reg                 rst_early_master;
    assign rst = rst_w;
    reg                mrst = 1;
    always @ (posedge arst or posedge clk[0]) begin
@@ -43,13 +44,16 @@ module  sync_resets#(
        if (arst) mrst <= 1;
        else      mrst <=  ~(locked[0] && en_locked);
    end
+    always @(posedge clk[0]) begin
+        rst_early_master <= rst_early_master_w;
+    end
    level_cross_clocks #(
        .WIDTH      (1),
        .REGISTER   (REGISTER)
    ) level_cross_clocks_mrst_i (
        .clk   (clk[0]),  // input
        .d_in  (mrst),    // input[0:0] 
-        .d_out (rst_early_master) // output[0:0] 
+        .d_out (rst_early_master_w) // output[0:0] 
    );
    generate
@@ -57,7 +61,7 @@ module  sync_resets#(
        for (i = 1; i < WIDTH; i = i + 1) begin: rst_block
            level_cross_clocks #(
                .WIDTH      (1),
-                .REGISTER   (REGISTER)
+                .REGISTER   ((i==5) ? 1: REGISTER) // disable for aclk
            ) level_cross_clocks_rst_i (
                .clk   (clk[i]),                                  // input
                .d_in  (mrst || rst_early_master || ~locked[i] ), // input[0:0] 

--- a/wrap/ddr3_wrap.v
+++ b/wrap/ddr3_wrap.v
@@ -276,7 +276,8 @@ module  ddr3_wrap#(
    assign #(DQS_IN_DELAY_H) DQSU =  en_dqs_in[1]? DQSU_DH3:  1'bz;
    assign #(DQS_IN_DELAY_H) NDQSU = en_dqs_in[1]? NDQSU_DH3: 1'bz;
-    ddr3 #(
+    ddr3
+     /*#(
        .TCK_MIN             (2500), 
        .TJIT_PER            (100),
        .TJIT_CC             (200),
@@ -444,7 +445,8 @@ module  ddr3_wrap#(
        .DIFF_GROUP          (2'd2),
        .SIMUL_500US         (5),
        .SIMUL_200US         (2)
-    ) ddr3_i (
+    ) */        
+    ddr3_i (
        .rst_n   (SDRST_D),         // input 
        .ck      (SDCLK_D),         // input 
        .ck_n    (SDNCLK_D),        // input 

--- a/x393.v
+++ b/x393.v
@@ -1026,6 +1026,7 @@ assign axi_grst = axi_rst_pre;
        .CLKFBOUT_MULT_REF                 (CLKFBOUT_MULT_REF),
        .CLKFBOUT_DIV_REF                  (CLKFBOUT_DIV_REF),
        .DIVCLK_DIVIDE                     (DIVCLK_DIVIDE),
+        .CLKFBOUT_USE_FINE_PS              (CLKFBOUT_USE_FINE_PS),
        .CLKFBOUT_PHASE                    (CLKFBOUT_PHASE),
        .SDCLK_PHASE                       (SDCLK_PHASE),
        .CLK_PHASE                         (CLK_PHASE),

--- a/x393_testbench02.sav
+++ b/x393_testbench02.sav
 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Sun Nov  1 05:57:20 2015
+[*] Tue Nov  3 01:32:22 2015
 [*]
-[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151031160934801.fst"
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151102172822765.fst"
-[dumpfile_mtime] "Sat Oct 31 22:49:05 2015"
+[dumpfile_mtime] "Tue Nov  3 01:03:38 2015"
-[dumpfile_size] 178613066
+[dumpfile_size] 173188638
 [savefile] "/home/andrey/git/x393/x393_testbench02.sav"
-[timestart] 98686720
+[timestart] 101932300
 [size] 1823 1180
-[pos] 1922 0
+[pos] 2 0
-*-14.236287 98735740 111045900 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-14.369095 101958000 111045900 99486000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_testbench02.
 [treeopen] x393_testbench02.compressor_control.
 [treeopen] x393_testbench02.simul_axi_hp1_wr_i.
@@ -25,12 +25,15 @@
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.genblk9.
+[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.
+[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.genblk9.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_cmd_decode_i.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_out_fifo_i.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.
+[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.
 [treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.byte_fifo_block[0].
@@ -56,7 +59,9 @@
 [treeopen] x393_testbench02.x393_i.mcntrl393_i.
 [treeopen] x393_testbench02.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.
 [treeopen] x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.
+[treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.
 [treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
+[treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
 [treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
 [treeopen] x393_testbench02.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
 [treeopen] x393_testbench02.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
@@ -90,6 +95,7 @@
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk7.
+[treeopen] x393_testbench02.x393_i.status_router16_top_i.
 [treeopen] x393_testbench02.x393_i.sync_resets_i.level_cross_clocks_mrst_i.
 [treeopen] x393_testbench02.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].
 [treeopen] x393_testbench02.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.
@@ -97,8 +103,8 @@
 [treeopen] x393_testbench02.x393_i.timing393_i.
 [treeopen] x393_testbench02.x393_i.timing393_i.camsync393_i.
 [treeopen] x393_testbench02.x393_i.timing393_i.rtc393_i.
-[sst_width] 412
+[sst_width] 366
-[signals_width] 351
+[signals_width] 355
 [sst_expanded] 1
 [sst_vpaned_height] 611
 @820
@@ -1902,9 +1908,8 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csco
 x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.pre_first_out
 x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.ywe_r
 x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.use_cr
-@23
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmult1[7:0]
 @22
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmult1[7:0]
 x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmult2[9:0]
 x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmulto[17:0]
 x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmultr[10:0]
@@ -1918,16 +1923,249 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csco
 @200
 -
 @22
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.pdc[7:0]
 x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.y[7:0]
 @28
 x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.ywe
 @22
 x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.yaddr[7:0]
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.sel_cbcrmult1
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.sub_y
+@22
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmult1[7:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.mm1[15:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.mm2[15:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.mm3[15:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.y1[15:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.y2[15:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.y3[15:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.pre_y[7:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.y[7:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.signed_y_r[7:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmult1[7:0]
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.sel_cbcrmult1
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.sub_y
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.ystrt
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.ywe_r
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.nxtline
+@22
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.yaddr[7:0]
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.use_cr
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.strt
+@200
+-outputs
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.ywe
+@22
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.yaddr[7:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.signed_y[7:0]
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cwe
+@22
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.caddr_r[6:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.caddr[6:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.q[8:0]
 @200
 -
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cwe0
+@29
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cwe_r
 @1000200
 -csconvert18
+@c00200
+-buf_average
+@22
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.yaddrw[7:0]
+@c00022
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
+@28
+(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
+(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
+(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
+(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
+(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
+(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
+(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
+(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
+(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
+@1401200
+-group_end
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.ywe
+@22
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.caddrw[7:0]
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_c[8:0]
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.cwe
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.pre_first_in
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.pre_first_mb
+@22
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.do[9:0]
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.ds
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.dv
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.first
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.first_mb_in
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.pre_first_mb
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.raddr_updateBlock
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.ccv_out_start
+@200
+-y-buf
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.we
+@c00022
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+@28
+(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
+@1401200
+-group_end
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.ren
+@c00022
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+@28
+(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
+@1401200
+-group_end
+@200
+-CbCr-buf
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.we
+@c00022
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+@28
+(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
+@1401200
+-group_end
+@28
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.ren
+@c00022
+x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+@28
+(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
+@1401200
+-group_end
+@200
+-
+@1401200
+-buf_average
+@1000200
 -compressor0
+@800200
+-status_routers
+@c00200
+-start_top
+@28
+x393_testbench02.x393_i.status_router16_top_i.start_in0
+x393_testbench02.x393_i.status_router16_top_i.start_in1
+x393_testbench02.x393_i.status_router16_top_i.start_in2
+x393_testbench02.x393_i.status_router16_top_i.start_in3
+x393_testbench02.x393_i.status_router16_top_i.start_in4
+x393_testbench02.x393_i.status_router16_top_i.start_in5
+x393_testbench02.x393_i.status_router16_top_i.start_in6
+x393_testbench02.x393_i.status_router16_top_i.start_in7
+x393_testbench02.x393_i.status_router16_top_i.start_in8
+x393_testbench02.x393_i.status_router16_top_i.start_in9
+x393_testbench02.x393_i.status_router16_top_i.start_in10
+x393_testbench02.x393_i.status_router16_top_i.start_in11
+x393_testbench02.x393_i.status_router16_top_i.start_in12
+x393_testbench02.x393_i.status_router16_top_i.start_in13
+x393_testbench02.x393_i.status_router16_top_i.start_in14
+x393_testbench02.x393_i.status_router16_top_i.start_in15
+@1401200
+-start_top
+@28
+x393_testbench02.x393_i.status_router16_top_i.start_int[1:0]
+x393_testbench02.x393_i.status_router16_top_i.start_out
+@200
+-top_router_2
+@28
+x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.clk
+@800028
+x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.rq_in[1:0]
+@28
+(0)x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.rq_in[1:0]
+(1)x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.rq_in[1:0]
+@1001200
+-group_end
+@200
+-
+@28
+x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.start_in0
+x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.start_in1
+x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.start_out
+@1000200
+-status_routers
+@c00200
+-mcontr_seq
+@800028
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
+@28
+(0)x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
+(1)x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
+(2)x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
+@1001200
+-group_end
+@22
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause_cntr[9:0]
+@28
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_fetch
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_nop
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_sel
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ren0
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ren1
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mclk_pre
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div_pre
+x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_pre
+@200
+-
+@1401200
+-mcontr_seq
 @c00200
 -sim_cmprs_output
 @22

--- a/x393_testbench02.tf
+++ b/x393_testbench02.tf
@@ -1296,6 +1296,7 @@ assign bresp=                              x393_i.ps7_i.MAXIGP0BRESP;
        .CLKFBOUT_DIV_REF                  (CLKFBOUT_DIV_REF),
        .DIVCLK_DIVIDE                     (DIVCLK_DIVIDE),
        .CLKFBOUT_PHASE                    (CLKFBOUT_PHASE),
+        .CLKFBOUT_USE_FINE_PS              (CLKFBOUT_USE_FINE_PS),
        .SDCLK_PHASE                       (SDCLK_PHASE),
        .CLK_PHASE                         (CLK_PHASE),
        .CLK_DIV_PHASE                     (CLK_DIV_PHASE),

--- a/x393_testbench03.tf
+++ b/x393_testbench03.tf
@@ -1423,6 +1423,7 @@ assign bresp=                              x393_i.ps7_i.MAXIGP0BRESP;
        .CLKFBOUT_MULT_REF                 (CLKFBOUT_MULT_REF),
        .CLKFBOUT_DIV_REF                  (CLKFBOUT_DIV_REF),
        .DIVCLK_DIVIDE                     (DIVCLK_DIVIDE),
+        .CLKFBOUT_USE_FINE_PS              (CLKFBOUT_USE_FINE_PS),
        .CLKFBOUT_PHASE                    (CLKFBOUT_PHASE),
        .SDCLK_PHASE                       (SDCLK_PHASE),
        .CLK_PHASE                         (CLK_PHASE),