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Commit db31f7a9 authored by Andrey Filippov's avatar Andrey Filippov
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moved buffer adddress away from sequencer, continue ot memory controller top module

parent e6cbe171
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Showing with 694 additions and 120 deletions
memctrl/cmd_encod_tiled_rd.v
View file @ db31f7a9
......@@ -137,6 +137,8 @@ module cmd_encod_tiled_rd #(
assign pre_act= rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE
assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
//TODO:Add AUTOPRECHARGE + ACTIVATE when column crossed - No, caller should make sure there is no row address change in the same line
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
else if (start) gen_run<= 1;
......
memctrl/mcntrl393.v
View file @ db31f7a9
......@@ -297,7 +297,8 @@ module mcntrl393 #(
wire seq_set0;
wire seq_done0;
wire buf_wr_chn0;
wire [6:0] buf_waddr_chn0;
wire buf_waddr_rst_chn0;
// wire [6:0] buf_waddr_chn0;
wire [63:0] buf_wdata_chn0;
wire want_rq1;
......@@ -308,7 +309,8 @@ module mcntrl393 #(
// wire seq_set1; // not used
wire seq_done1;
wire buf_rd_chn1;
wire [6:0] buf_raddr_chn1;
wire buf_raddr_rst_chn1;
// wire [6:0] buf_raddr_chn1;
wire [63:0] buf_rdata_chn1;
wire want_rq2;
......@@ -319,7 +321,8 @@ module mcntrl393 #(
wire seq_set2x; // may be shared with other channel
wire seq_done2;
wire buf_wr_chn2;
wire [6:0] buf_waddr_chn2;
wire buf_waddr_rst_chn2;
// wire [6:0] buf_waddr_chn2;
wire [63:0] buf_wdata_chn2;
wire want_rq3;
......@@ -330,7 +333,8 @@ module mcntrl393 #(
wire seq_set3x; // may be shared with other channel
wire seq_done3;
wire buf_rd_chn3;
wire [6:0] buf_raddr_chn3;
wire buf_raddr_rst_chn3;
// wire [6:0] buf_raddr_chn3;
wire [63:0] buf_rdata_chn3;
wire want_rq4;
......@@ -341,7 +345,8 @@ module mcntrl393 #(
wire seq_set4;
wire seq_done4;
wire buf_wr_chn4;
wire [6:0] buf_waddr_chn4;
wire buf_waddr_rst_chn4;
// wire [6:0] buf_waddr_chn4;
wire [63:0] buf_wdata_chn4;
// Command tree - insert register layer if needed
......@@ -571,6 +576,7 @@ module mcntrl393 #(
// Port memory buffer (4 pages each, R/W fixed, port 0 - AXI read from DDR, port 1 - AXI write to DDR
// Port 2 (read DDR to AXI) buffer
/*
ram_512x64w_1kx32r #(
.REGISTERS(1)
) chn2_buf_i (
......@@ -585,8 +591,25 @@ module mcntrl393 #(
.web (8'hff), // input[7:0]
.data_in (buf_wdata_chn2) // input[63:0] @negedge mclk
);
*/
/* Instance template for module mcntrl_1kx32r */
mcntrl_1kx32r chn2_buf_i (
.ext_clk (axi_clk), // input
.ext_raddr (buf_raddr), // input[9:0]
.ext_rd (buf2_rd), // input
.ext_regen (buf2_regen), // input
.ext_data_out (buf2_data), // output[31:0]
.wclk (!mclk), // input
.wpage (xfer_page2), // input[1:0]
.waddr_reset (buf_waddr_rst_chn2), // input
.skip_reset (1'b0), // input
.we (buf_wr_chn2), // input
.data_in (buf_wdata_chn2) // input[63:0]
);
// Port 3 (write DDR from AXI) buffer
/*
ram_1kx32w_512x64r #(
.REGISTERS(1)
) chn3_buf_i (
......@@ -601,6 +624,20 @@ module mcntrl393 #(
.web (4'hf), // input[3:0]
.data_in (buf_wdata) // input[31:0]
);
*/
/* Instance template for module mcntrl_1kx32w */
mcntrl_1kx32w chn3_buf_i (
.ext_clk(axi_clk), // input
.ext_waddr(buf_waddr), // input[9:0]
.ext_we(buf3_we), // input
.ext_data_in(buf_wdata), // input[31:0] buf_wdata - from AXI
.rclk(mclk), // input
.rpage(xfer_page3), // input[1:0]
.raddr_reset(buf_raddr_rst_chn3), // input
.skip_reset(1'b0), // input
.rd(buf_rd_chn3), // input
.data_out(buf_rdata_chn3) // output[63:0]
);
/* Instance template for module mcntrl_linear_rw */
mcntrl_linear_rw #(
......@@ -790,7 +827,7 @@ module mcntrl393 #(
.seq_set0 (seq_set0), // output
.seq_done0 (seq_done0), // input
.buf_wr_chn0 (buf_wr_chn0), // input @negedge mclk
.buf_waddr_chn0 (buf_waddr_chn0), // input[6:0] @negedge mclk
.buf_waddr_rst_chn0 (buf_waddr_rst_chn0), // input @negedge mclk
.buf_wdata_chn0 (buf_wdata_chn0), // input[63:0]@negedge mclk
.want_rq1 (want_rq1), // output reg
......@@ -798,7 +835,7 @@ module mcntrl393 #(
.channel_pgm_en1 (channel_pgm_en1), // input
.seq_done1 (seq_done1), // input
.buf_rd_chn1 (buf_rd_chn1), // input
.buf_raddr_chn1 (buf_raddr_chn1), // input[6:0]
.buf_raddr_rst_chn1 (buf_raddr_rst_chn1), // input
.buf_rdata_chn1 (buf_rdata_chn1) // output[63:0]
);
......@@ -896,7 +933,8 @@ module mcntrl393 #(
.seq_set0 (seq_set0), // input
.seq_done0 (seq_done0), // output
.buf_wr_chn0 (buf_wr_chn0), // output
.buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
.buf_waddr_rst_chn0 (buf_waddr_rst_chn0), // output
// .buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
.buf_wdata_chn0 (buf_wdata_chn0), // output[63:0]
.want_rq1 (want_rq1), // input
......@@ -907,7 +945,8 @@ module mcntrl393 #(
.seq_set1 (1'b0), // not used: seq_set1), // input
.seq_done1 (seq_done1), // output
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_raddr_chn1 (buf_raddr_chn1), // output[6:0]
.buf_raddr_rst_chn1 (buf_raddr_rst_chn1), // output
// .buf_raddr_chn1 (buf_raddr_chn1), // output[6:0]
.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]
.want_rq2 (want_rq2), // input
......@@ -918,7 +957,8 @@ module mcntrl393 #(
.seq_set2 (seq_set2x), // input
.seq_done2 (seq_done2), // output
.buf_wr_chn2 (buf_wr_chn2), // output
.buf_waddr_chn2 (buf_waddr_chn2), // output[6:0]
.buf_waddr_rst_chn2 (buf_waddr_rst_chn2), // output
// .buf_waddr_chn2 (buf_waddr_chn2), // output[6:0]
.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]
.want_rq3 (want_rq3), // input
......@@ -929,7 +969,8 @@ module mcntrl393 #(
.seq_set3 (seq_set3x), // input
.seq_done3 (seq_done3), // output
.buf_rd_chn3 (buf_rd_chn3), // output
.buf_raddr_chn3 (buf_raddr_chn3), // output[6:0]
.buf_raddr_rst_chn3 (buf_raddr_rst_chn3), // output
// .buf_raddr_chn3 (buf_raddr_chn3), // output[6:0]
.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]
.want_rq4 (want_rq4), // input
......@@ -940,7 +981,8 @@ module mcntrl393 #(
.seq_set4 (seq_set4), // input
.seq_done4 (seq_done4), // output
.buf_wr_chn4 (buf_wr_chn4), // output
.buf_waddr_chn4 (buf_waddr_chn4), // output[6:0]
.buf_waddr_rst_chn4 (buf_waddr_rst_chn4), // output
// .buf_waddr_chn4 (buf_waddr_chn4), // output[6:0]
.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]
.SDRST (SDRST), // output
......
memctrl/mcntrl_1kx32r.v 0 → 100644
View file @ db31f7a9
/*******************************************************************************
* Module: mcntrl_1kx32r
* Date:2015-02-03
* Author: andrey
* Description: Paged buffer for ddr3 controller read channel
* with address autoincrement. 32 bit external data.
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* mcntrl_1kx32r.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mcntrl_1kx32r.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module mcntrl_1kx32r(
input ext_clk,
input [ 9:0] ext_raddr, // read address
input ext_rd, // read port enable
input ext_regen, // output register enable
output [31:0] ext_data_out, // data out
input wclk, // !mclk (inverted)
input [1:0] wpage, // will register to wclk, input OK with mclk
input waddr_reset, // reset write buffer address (to page start), sync to wclk (!mclk)
input skip_reset, // ignore waddr_reset (resync to wclk)
input we, // write port enable (also increment write buffer address)
input [63:0] data_in // data in
);
reg [1:0] wpage_wclk;
reg skip_reset_wclk;
reg [6:0] waddr;
always @ (posedge wclk) begin
wpage_wclk <= wpage;
skip_reset_wclk <= skip_reset;
if (waddr_reset && !skip_reset_wclk) waddr <= 0;
else if (we) waddr <= waddr +1;
end
ram_512x64w_1kx32r #(
.REGISTERS(1)
) ram_512x64w_1kx32r_i (
.rclk (ext_clk), // input
.raddr (ext_raddr), // input[9:0]
.ren (ext_rd), // input
.regen (ext_regen), // input
.data_out (ext_data_out), // output[31:0]
.wclk (wclk), // input - OK, negedge mclk
.waddr ({wpage_wclk,waddr}), // input[8:0] @negedge mclk
.we (we), // input @negedge mclk
.web (8'hff), // input[7:0]
.data_in (data_in) // input[63:0] @negedge mclk
);
endmodule
memctrl/mcntrl_1kx32w.v 0 → 100644
View file @ db31f7a9
/*******************************************************************************
* Module: mcntrl_1kx32w
* Date:2015-02-03
* Author: andrey
* Description: Paged buffer for ddr3 controller write channel
* with address autoincrement. 32 bit external data. Extends rd to regen
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* mcntrl_1kx32w.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mcntrl_1kx32w.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module mcntrl_1kx32w(
input ext_clk,
input [ 9:0] ext_waddr, // external write address
input ext_we, // external write enable
input [31:0] ext_data_in, // data input
input rclk, // mclk
input [1:0] rpage, // will register to wclk, input OK with mclk
input raddr_reset, // reset buffer read address (to page start)
input skip_reset, // ignore waddr_reset (resync to wclk)
input rd, // read buffer tomemory, increment read address (regester enable will be delayed)
output [63:0] data_out // data out
);
reg skip_reset_rclk;
reg [6:0] raddr;
reg regen;
always @ (posedge rclk) begin
regen <= rd;
skip_reset_rclk <= skip_reset;
if (raddr_reset && !skip_reset_rclk) raddr <= 0;
else if (rd) raddr <= raddr +1;
end
ram_1kx32w_512x64r #(
.REGISTERS(1)
)ram_1kx32w_512x64r_i (
.rclk (rclk), // input
.raddr ({rpage,raddr}), // input[8:0]
.ren (rd), // input
.regen (regen), // input
.data_out (data_out), // output[63:0]
.wclk (ext_clk), // input
.waddr (ext_waddr), // input[9:0]
.we (ext_we), // input
.web (4'hf), // input[3:0]
.data_in (ext_data_in) // input[31:0]
);
endmodule
memctrl/mcntrl_ps_pio.v
View file @ db31f7a9
......@@ -61,7 +61,8 @@ module mcntrl_ps_pio#(
output seq_set0,
input seq_done0,
input buf_wr_chn0,
input [6:0] buf_waddr_chn0,
input buf_waddr_rst_chn0,
// input [6:0] buf_waddr_chn0,
input [63:0] buf_wdata_chn0,
// write port 1
output reg want_rq1,
......@@ -72,7 +73,8 @@ module mcntrl_ps_pio#(
// output seq_set1, // connect externally to seq_set0
input seq_done1,
input buf_rd_chn1,
input [6:0] buf_raddr_chn1,
input buf_raddr_rst_chn1,
// input [6:0] buf_raddr_chn1,
output [63:0] buf_rdata_chn1
);
localparam CMD_WIDTH=14;
......@@ -214,6 +216,7 @@ fifo_same_clock #(
// Port 0 (read DDR to AXI) buffer
/*
ram_512x64w_1kx32r #(
.REGISTERS(1)
) port0_buf_i (
......@@ -228,8 +231,23 @@ fifo_same_clock #(
.web (8'hff), // input[7:0]
.data_in (buf_wdata_chn0) // input[63:0]
);
*/
mcntrl_1kx32r chn0_buf_i (
.ext_clk (port0_clk), // input
.ext_raddr (port0_addr), // input[9:0]
.ext_rd (port0_re), // input
.ext_regen (port0_regen), // input
.ext_data_out (port0_data), // output[31:0]
.wclk (!mclk), // input
.wpage (page), // input[1:0]
.waddr_reset (buf_waddr_rst_chn0), // input
.skip_reset (1'b0), // input
.we (buf_wr_chn0), // input
.data_in (buf_wdata_chn0) // input[63:0]
);
// Port 1 (write DDR from AXI) buffer
/*
ram_1kx32w_512x64r #(
.REGISTERS(1)
) port1_buf_i (
......@@ -244,5 +262,20 @@ fifo_same_clock #(
.web (4'hf), // input[3:0]
.data_in (port1_data) // input[31:0]
);
*/
mcntrl_1kx32w chn1_buf_i (
.ext_clk (port1_clk), // input
.ext_waddr (port1_addr), // input[9:0]
.ext_we (port1_we), // input
.ext_data_in (port1_data), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage (page), // input[1:0]
.raddr_reset (buf_raddr_rst_chn1), // input
.skip_reset (1'b0), // input
.rd (buf_rd_chn1), // input
.data_out (buf_rdata_chn1) // output[63:0]
);
endmodule
memctrl/mcntrl_tiled_rw.v 0 → 100644
View file @ db31f7a9
This diff is collapsed.
memctrl/memctrl16.v
View file @ db31f7a9
This diff is collapsed.
phy/mcontr_sequencer.v
View file @ db31f7a9
......@@ -143,14 +143,17 @@ module mcontr_sequencer #(
// There will be =1 cycle external latency in address/re and 1 cycle latency in read data (should match sequence programs)
// Address data is sync to posedge mclk
output ext_buf_rd,
output [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
output ext_buf_raddr_rst, // reset external buffer address to page start
// output [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
output [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
input [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
// Interface to memory read channels (up to 16)
// Address/data sync to negedge mclk!, any latency OK - just generate DONE appropriately (through the sequencer with delay?
// folowing a sync to negedge!
output ext_buf_wr,
output [6:0] ext_buf_waddr, // valid with ext_buf_wr
output ext_buf_waddr_rst, // reset external buffer address to page start
// output [6:0] ext_buf_waddr, // valid with ext_buf_wr
output [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead of ext_buf_wr!, maybe not needed - will be generated externally
output [63:0] ext_buf_wdata, // valid with ext_buf_wr
// temporary debug data
......@@ -208,8 +211,10 @@ module mcontr_sequencer #(
wire [31:0] phy_cmd_word; // selected output from eithe cmd0 buffer or cmd1 buffer
wire [31:0] phy_cmd0_word; // cmd0 buffer output
wire [31:0] phy_cmd1_word; // cmd1 buffer output
reg [ 6:0] buf_raddr;
reg [ 6:0] buf_waddr_negedge;
wire buf_raddr_reset;
// reg [ 6:0] buf_raddr;
reg buf_waddr_reset_negedge;
// reg [ 6:0] buf_waddr_negedge;
reg buf_wr_negedge;
wire [63:0] buf_wdata; // output[63:0]
reg [63:0] buf_wdata_negedge; // output[63:0]
......@@ -260,13 +265,17 @@ module mcontr_sequencer #(
// assign buf_rdata[63:0] = ({64{buf_sel_1hot[1]}} & buf1_rdata[63:0]); // ORed with other read channels terms
// External buffers buffer related signals
assign buf_raddr_reset= run_seq_d;
assign ext_buf_rd= buf_rd;
assign ext_buf_raddr= buf_raddr;
assign ext_buf_raddr_rst=buf_raddr_reset;
// assign ext_buf_raddr= buf_raddr;
assign ext_buf_rchn= run_chn_d;
assign buf_rdata[63:0] = ext_buf_rdata;
assign ext_buf_wr= buf_wr_negedge;
assign ext_buf_waddr= buf_waddr_negedge;
assign ext_buf_waddr_rst=buf_waddr_reset_negedge;
// assign ext_buf_waddr= buf_waddr_negedge;
assign ext_buf_wchn= run_chn_d_negedge;
assign ext_buf_wdata= buf_wdata_negedge;
......@@ -426,9 +435,9 @@ module mcontr_sequencer #(
if (rst) cmd_sel <= 0;
else if (run_seq) cmd_sel <= run_addr[10];
if (rst) buf_raddr <= 7'h0;
else if (run_seq_d) buf_raddr <= 7'h0;
else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge //SuppressThisWarning ISExst Result of 10-bit expression is truncated to fit in 9-bit target.
// if (rst) buf_raddr <= 7'h0;
// else if (run_seq_d) buf_raddr <= 7'h0;
// else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge //SuppressThisWarning ISExst Result of 10-bit expression is truncated to fit in 9-bit target.
if (rst) run_chn_d <= 0;
else if (run_seq) run_chn_d <= run_chn;
......@@ -438,7 +447,8 @@ module mcontr_sequencer #(
end
// re-register buffer write address to match DDR3 data
always @ (negedge mclk) begin
buf_waddr_negedge <= buf_raddr;
// buf_waddr_negedge <= buf_raddr;
buf_waddr_reset_negedge <= buf_raddr_reset;
buf_wr_negedge <= buf_wr;
buf_wdata_negedge <= buf_wdata;
run_chn_d_negedge <= run_chn_d;
......
util_modules/mcont_from_chnbuf_reg.v
View file @ db31f7a9
......@@ -27,13 +27,15 @@ module mcont_from_chnbuf_reg #(
input rst,
input clk,
input ext_buf_rd,
input [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
input ext_buf_raddr_rst,
// input [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
input [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
input seq_done, // sequence done
output reg buf_done, // sequence done for the specified channel
output reg [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
output reg buf_rd_chn,
output reg [6:0] buf_raddr_chn,
output reg buf_raddr_rst_chn,
// output reg [6:0] buf_raddr_chn,
input [63:0] buf_rdata_chn
);
reg buf_chn_sel;
......@@ -51,7 +53,8 @@ module mcont_from_chnbuf_reg #(
if (rst) buf_done <= 0;
else buf_done <= buf_chn_sel && seq_done;
end
always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
always @ (posedge clk) buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
// always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;
endmodule
util_modules/mcont_to_chnbuf_reg.v
View file @ db31f7a9
......@@ -26,13 +26,15 @@ parameter CHN_NUMBER=0
input rst,
input clk,
input ext_buf_wr,
input [6:0] ext_buf_waddr, // valid with ext_buf_wr
input ext_buf_waddr_rst,
// input [6:0] ext_buf_waddr, // valid with ext_buf_wr
input [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
input [63:0] ext_buf_wdata, // valid with ext_buf_wr
input seq_done, // sequence done
output reg buf_done, // @ posedge mclk sequence done for the specified channel
output reg buf_wr_chn, // @ negedge mclk
output reg [6:0] buf_waddr_chn, // @ negedge mclk
output reg buf_waddr_rst_chn,// @ negedge mclk
// output reg [6:0] buf_waddr_chn, // @ negedge mclk
output reg [63:0] buf_wdata_chn // @ negedge mclk
);
reg buf_chn_sel;
......@@ -49,9 +51,12 @@ parameter CHN_NUMBER=0
else buf_done <= buf_chn_sel && seq_done;
end
always @ (negedge clk) begin
buf_waddr_rst_chn <= ext_buf_waddr_rst && (ext_buf_wchn==CHN_NUMBER);
end
always @ (negedge clk) if (buf_chn_sel && ext_buf_wr) begin
buf_waddr_chn <= ext_buf_waddr;
// buf_waddr_chn <= ext_buf_waddr;
buf_wdata_chn <= ext_buf_wdata;
end
endmodule
......
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