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Commit db31f7a9 authored by Andrey Filippov's avatar Andrey Filippov
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moved buffer adddress away from sequencer, continue ot memory controller top module

parent e6cbe171
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Showing with 694 additions and 120 deletions
memctrl/cmd_encod_tiled_rd.v
View file @ db31f7a9
......@@ -137,6 +137,8 @@ module cmd_encod_tiled_rd #(
assign pre_act= rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE
assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
//TODO:Add AUTOPRECHARGE + ACTIVATE when column crossed - No, caller should make sure there is no row address change in the same line
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
else if (start) gen_run<= 1;
......
memctrl/mcntrl393.v
View file @ db31f7a9
......@@ -297,7 +297,8 @@ module mcntrl393 #(
wire seq_set0;
wire seq_done0;
wire buf_wr_chn0;
wire [6:0] buf_waddr_chn0;
wire buf_waddr_rst_chn0;
// wire [6:0] buf_waddr_chn0;
wire [63:0] buf_wdata_chn0;
wire want_rq1;
......@@ -308,7 +309,8 @@ module mcntrl393 #(
// wire seq_set1; // not used
wire seq_done1;
wire buf_rd_chn1;
wire [6:0] buf_raddr_chn1;
wire buf_raddr_rst_chn1;
// wire [6:0] buf_raddr_chn1;
wire [63:0] buf_rdata_chn1;
wire want_rq2;
......@@ -319,7 +321,8 @@ module mcntrl393 #(
wire seq_set2x; // may be shared with other channel
wire seq_done2;
wire buf_wr_chn2;
wire [6:0] buf_waddr_chn2;
wire buf_waddr_rst_chn2;
// wire [6:0] buf_waddr_chn2;
wire [63:0] buf_wdata_chn2;
wire want_rq3;
......@@ -330,7 +333,8 @@ module mcntrl393 #(
wire seq_set3x; // may be shared with other channel
wire seq_done3;
wire buf_rd_chn3;
wire [6:0] buf_raddr_chn3;
wire buf_raddr_rst_chn3;
// wire [6:0] buf_raddr_chn3;
wire [63:0] buf_rdata_chn3;
wire want_rq4;
......@@ -341,7 +345,8 @@ module mcntrl393 #(
wire seq_set4;
wire seq_done4;
wire buf_wr_chn4;
wire [6:0] buf_waddr_chn4;
wire buf_waddr_rst_chn4;
// wire [6:0] buf_waddr_chn4;
wire [63:0] buf_wdata_chn4;
// Command tree - insert register layer if needed
......@@ -571,6 +576,7 @@ module mcntrl393 #(
// Port memory buffer (4 pages each, R/W fixed, port 0 - AXI read from DDR, port 1 - AXI write to DDR
// Port 2 (read DDR to AXI) buffer
/*
ram_512x64w_1kx32r #(
.REGISTERS(1)
) chn2_buf_i (
......@@ -585,8 +591,25 @@ module mcntrl393 #(
.web (8'hff), // input[7:0]
.data_in (buf_wdata_chn2) // input[63:0] @negedge mclk
);
*/
/* Instance template for module mcntrl_1kx32r */
mcntrl_1kx32r chn2_buf_i (
.ext_clk (axi_clk), // input
.ext_raddr (buf_raddr), // input[9:0]
.ext_rd (buf2_rd), // input
.ext_regen (buf2_regen), // input
.ext_data_out (buf2_data), // output[31:0]
.wclk (!mclk), // input
.wpage (xfer_page2), // input[1:0]
.waddr_reset (buf_waddr_rst_chn2), // input
.skip_reset (1'b0), // input
.we (buf_wr_chn2), // input
.data_in (buf_wdata_chn2) // input[63:0]
);
// Port 3 (write DDR from AXI) buffer
/*
ram_1kx32w_512x64r #(
.REGISTERS(1)
) chn3_buf_i (
......@@ -601,6 +624,20 @@ module mcntrl393 #(
.web (4'hf), // input[3:0]
.data_in (buf_wdata) // input[31:0]
);
*/
/* Instance template for module mcntrl_1kx32w */
mcntrl_1kx32w chn3_buf_i (
.ext_clk(axi_clk), // input
.ext_waddr(buf_waddr), // input[9:0]
.ext_we(buf3_we), // input
.ext_data_in(buf_wdata), // input[31:0] buf_wdata - from AXI
.rclk(mclk), // input
.rpage(xfer_page3), // input[1:0]
.raddr_reset(buf_raddr_rst_chn3), // input
.skip_reset(1'b0), // input
.rd(buf_rd_chn3), // input
.data_out(buf_rdata_chn3) // output[63:0]
);
/* Instance template for module mcntrl_linear_rw */
mcntrl_linear_rw #(
......@@ -790,7 +827,7 @@ module mcntrl393 #(
.seq_set0 (seq_set0), // output
.seq_done0 (seq_done0), // input
.buf_wr_chn0 (buf_wr_chn0), // input @negedge mclk
.buf_waddr_chn0 (buf_waddr_chn0), // input[6:0] @negedge mclk
.buf_waddr_rst_chn0 (buf_waddr_rst_chn0), // input @negedge mclk
.buf_wdata_chn0 (buf_wdata_chn0), // input[63:0]@negedge mclk
.want_rq1 (want_rq1), // output reg
......@@ -798,7 +835,7 @@ module mcntrl393 #(
.channel_pgm_en1 (channel_pgm_en1), // input
.seq_done1 (seq_done1), // input
.buf_rd_chn1 (buf_rd_chn1), // input
.buf_raddr_chn1 (buf_raddr_chn1), // input[6:0]
.buf_raddr_rst_chn1 (buf_raddr_rst_chn1), // input
.buf_rdata_chn1 (buf_rdata_chn1) // output[63:0]
);
......@@ -896,7 +933,8 @@ module mcntrl393 #(
.seq_set0 (seq_set0), // input
.seq_done0 (seq_done0), // output
.buf_wr_chn0 (buf_wr_chn0), // output
.buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
.buf_waddr_rst_chn0 (buf_waddr_rst_chn0), // output
// .buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
.buf_wdata_chn0 (buf_wdata_chn0), // output[63:0]
.want_rq1 (want_rq1), // input
......@@ -907,7 +945,8 @@ module mcntrl393 #(
.seq_set1 (1'b0), // not used: seq_set1), // input
.seq_done1 (seq_done1), // output
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_raddr_chn1 (buf_raddr_chn1), // output[6:0]
.buf_raddr_rst_chn1 (buf_raddr_rst_chn1), // output
// .buf_raddr_chn1 (buf_raddr_chn1), // output[6:0]
.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]
.want_rq2 (want_rq2), // input
......@@ -918,7 +957,8 @@ module mcntrl393 #(
.seq_set2 (seq_set2x), // input
.seq_done2 (seq_done2), // output
.buf_wr_chn2 (buf_wr_chn2), // output
.buf_waddr_chn2 (buf_waddr_chn2), // output[6:0]
.buf_waddr_rst_chn2 (buf_waddr_rst_chn2), // output
// .buf_waddr_chn2 (buf_waddr_chn2), // output[6:0]
.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]
.want_rq3 (want_rq3), // input
......@@ -929,7 +969,8 @@ module mcntrl393 #(
.seq_set3 (seq_set3x), // input
.seq_done3 (seq_done3), // output
.buf_rd_chn3 (buf_rd_chn3), // output
.buf_raddr_chn3 (buf_raddr_chn3), // output[6:0]
.buf_raddr_rst_chn3 (buf_raddr_rst_chn3), // output
// .buf_raddr_chn3 (buf_raddr_chn3), // output[6:0]
.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]
.want_rq4 (want_rq4), // input
......@@ -940,7 +981,8 @@ module mcntrl393 #(
.seq_set4 (seq_set4), // input
.seq_done4 (seq_done4), // output
.buf_wr_chn4 (buf_wr_chn4), // output
.buf_waddr_chn4 (buf_waddr_chn4), // output[6:0]
.buf_waddr_rst_chn4 (buf_waddr_rst_chn4), // output
// .buf_waddr_chn4 (buf_waddr_chn4), // output[6:0]
.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]
.SDRST (SDRST), // output
......
memctrl/mcntrl_1kx32r.v 0 → 100644
View file @ db31f7a9
/*******************************************************************************
* Module: mcntrl_1kx32r
* Date:2015-02-03
* Author: andrey
* Description: Paged buffer for ddr3 controller read channel
* with address autoincrement. 32 bit external data.
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* mcntrl_1kx32r.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mcntrl_1kx32r.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module mcntrl_1kx32r(
input ext_clk,
input [ 9:0] ext_raddr, // read address
input ext_rd, // read port enable
input ext_regen, // output register enable
output [31:0] ext_data_out, // data out
input wclk, // !mclk (inverted)
input [1:0] wpage, // will register to wclk, input OK with mclk
input waddr_reset, // reset write buffer address (to page start), sync to wclk (!mclk)
input skip_reset, // ignore waddr_reset (resync to wclk)
input we, // write port enable (also increment write buffer address)
input [63:0] data_in // data in
);
reg [1:0] wpage_wclk;
reg skip_reset_wclk;
reg [6:0] waddr;
always @ (posedge wclk) begin
wpage_wclk <= wpage;
skip_reset_wclk <= skip_reset;
if (waddr_reset && !skip_reset_wclk) waddr <= 0;
else if (we) waddr <= waddr +1;
end
ram_512x64w_1kx32r #(
.REGISTERS(1)
) ram_512x64w_1kx32r_i (
.rclk (ext_clk), // input
.raddr (ext_raddr), // input[9:0]
.ren (ext_rd), // input
.regen (ext_regen), // input
.data_out (ext_data_out), // output[31:0]
.wclk (wclk), // input - OK, negedge mclk
.waddr ({wpage_wclk,waddr}), // input[8:0] @negedge mclk
.we (we), // input @negedge mclk
.web (8'hff), // input[7:0]
.data_in (data_in) // input[63:0] @negedge mclk
);
endmodule
memctrl/mcntrl_1kx32w.v 0 → 100644
View file @ db31f7a9
/*******************************************************************************
* Module: mcntrl_1kx32w
* Date:2015-02-03
* Author: andrey
* Description: Paged buffer for ddr3 controller write channel
* with address autoincrement. 32 bit external data. Extends rd to regen
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* mcntrl_1kx32w.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mcntrl_1kx32w.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module mcntrl_1kx32w(
input ext_clk,
input [ 9:0] ext_waddr, // external write address
input ext_we, // external write enable
input [31:0] ext_data_in, // data input
input rclk, // mclk
input [1:0] rpage, // will register to wclk, input OK with mclk
input raddr_reset, // reset buffer read address (to page start)
input skip_reset, // ignore waddr_reset (resync to wclk)
input rd, // read buffer tomemory, increment read address (regester enable will be delayed)
output [63:0] data_out // data out
);
reg skip_reset_rclk;
reg [6:0] raddr;
reg regen;
always @ (posedge rclk) begin
regen <= rd;
skip_reset_rclk <= skip_reset;
if (raddr_reset && !skip_reset_rclk) raddr <= 0;
else if (rd) raddr <= raddr +1;
end
ram_1kx32w_512x64r #(
.REGISTERS(1)
)ram_1kx32w_512x64r_i (
.rclk (rclk), // input
.raddr ({rpage,raddr}), // input[8:0]
.ren (rd), // input
.regen (regen), // input
.data_out (data_out), // output[63:0]
.wclk (ext_clk), // input
.waddr (ext_waddr), // input[9:0]
.we (ext_we), // input
.web (4'hf), // input[3:0]
.data_in (ext_data_in) // input[31:0]
);
endmodule
memctrl/mcntrl_ps_pio.v
View file @ db31f7a9
......@@ -61,7 +61,8 @@ module mcntrl_ps_pio#(
output seq_set0,
input seq_done0,
input buf_wr_chn0,
input [6:0] buf_waddr_chn0,
input buf_waddr_rst_chn0,
// input [6:0] buf_waddr_chn0,
input [63:0] buf_wdata_chn0,
// write port 1
output reg want_rq1,
......@@ -72,7 +73,8 @@ module mcntrl_ps_pio#(
// output seq_set1, // connect externally to seq_set0
input seq_done1,
input buf_rd_chn1,
input [6:0] buf_raddr_chn1,
input buf_raddr_rst_chn1,
// input [6:0] buf_raddr_chn1,
output [63:0] buf_rdata_chn1
);
localparam CMD_WIDTH=14;
......@@ -214,6 +216,7 @@ fifo_same_clock #(
// Port 0 (read DDR to AXI) buffer
/*
ram_512x64w_1kx32r #(
.REGISTERS(1)
) port0_buf_i (
......@@ -228,8 +231,23 @@ fifo_same_clock #(
.web (8'hff), // input[7:0]
.data_in (buf_wdata_chn0) // input[63:0]
);
*/
mcntrl_1kx32r chn0_buf_i (
.ext_clk (port0_clk), // input
.ext_raddr (port0_addr), // input[9:0]
.ext_rd (port0_re), // input
.ext_regen (port0_regen), // input
.ext_data_out (port0_data), // output[31:0]
.wclk (!mclk), // input
.wpage (page), // input[1:0]
.waddr_reset (buf_waddr_rst_chn0), // input
.skip_reset (1'b0), // input
.we (buf_wr_chn0), // input
.data_in (buf_wdata_chn0) // input[63:0]
);
// Port 1 (write DDR from AXI) buffer
/*
ram_1kx32w_512x64r #(
.REGISTERS(1)
) port1_buf_i (
......@@ -244,5 +262,20 @@ fifo_same_clock #(
.web (4'hf), // input[3:0]
.data_in (port1_data) // input[31:0]
);
*/
mcntrl_1kx32w chn1_buf_i (
.ext_clk (port1_clk), // input
.ext_waddr (port1_addr), // input[9:0]
.ext_we (port1_we), // input
.ext_data_in (port1_data), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage (page), // input[1:0]
.raddr_reset (buf_raddr_rst_chn1), // input
.skip_reset (1'b0), // input
.rd (buf_rd_chn1), // input
.data_out (buf_rdata_chn1) // output[63:0]
);
endmodule
memctrl/mcntrl_tiled_rw.v 0 → 100644
View file @ db31f7a9
/*******************************************************************************
* Module: mcntrl_tiled_rw
* Date:2015-02-03
* Author: andrey
* Description: Organize paged R/W from DDR3 memory in tiled order
* with window support
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* mcntrl_tiled_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mcntrl_tiled_rw.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module mcntrl_tiled_rw#(
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_TILED_ADDR= 'h120,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (
parameter MCNTRL_TILED_STATUS_REG_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2 // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
)(
input rst,
input mclk,
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // byte-wide address/data
output status_rq, // request to send downstream (last byte with rq==0)
input status_start, // acknowledge of address (first byte) from downsteram
input frame_start, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
input next_page, // page was read/written from/to 4*1kB on-chip buffer
// output page_ready, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
output frame_done, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// optional I/O for channel synchronization
output [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
input suspend, // suspend transfers (from external line number comparator)
output xfer_want, // "want" data transfer
output xfer_need, // "need" - really need a transfer (only 1 page/ room for 1 page left in a buffer), want should still be set.
input xfer_grant, // sequencer programming access granted, deassert wait/need
output xfer_start, // initiate a transfer (next cycle after xfer_grant)
output [2:0] xfer_bank, // start bank address
output [ADDRESS_NUMBER-1:0] xfer_row, // memory row
output [COLADDR_NUMBER-4:0] xfer_col, // start memory column in 8-bursts
// output [NUM_XFER_BITS-1:0] xfer_num128, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
output [5:0] num_rows_m1, // number of rows to read minus 1
output [5:0] num_cols_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
output keep_open, // (programmable bit)keep banks open (for <=8 banks only
input xfer_done, // transfer to/from the buffer finished
output [1:0] xfer_page // page number for transfer (goes to channel buffer memory-side adderss)
);
localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
localparam MPY_WIDTH= NUM_RC_BURST_BITS; // 22
localparam PAR_MOD_LATENCY= 7; // TODO: Find actual worst-case latency for:
reg [FRAME_WIDTH_BITS-1:0] curr_x; // (calculated) start of transfer x (relative to window left)
reg [FRAME_HEIGHT_BITS-1:0] curr_y; // (calculated) start of transfer y (relative to window top)
reg [FRAME_HEIGHT_BITS:0] next_y; // (calculated) next row number
reg [NUM_RC_BURST_BITS-1:0] line_start_addr;// (calculated) Line start (in {row,col8} in burst8
// calculating full width from the frame width
reg [FRAME_HEIGHT_BITS-1:0] frame_y; // current line number referenced to the frame top
reg [FRAME_WIDTH_BITS-1:0] frame_x; // current column number referenced to the frame left
reg [FRAME_HEIGHT_BITS-4:0] frame_y8_r; // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler)
reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY
reg [MPY_WIDTH-1:0] mul_rslt;
reg [NUM_RC_BURST_BITS-1:0] start_addr_r; // 22 bit - to be absorbed by DSP
reg [2:0] bank_reg [2:0];
wire [FRAME_WIDTH_BITS+FRAME_HEIGHT_BITS-3:0] mul_rslt_w;
// wire [2:0] cur_bank;
reg [FRAME_WIDTH_BITS:0] row_left; // number of 8-bursts left in the current row
reg last_in_row;
reg [COLADDR_NUMBER-3:0] mem_page_left; // number of 8-bursts left in the pointed memory page
reg [NUM_XFER_BITS:0] lim_by_xfer; // number of bursts left limited by the longest transfer (currently 64)
reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8
wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
reg [2:0] xfer_start_r;
reg [PAR_MOD_LATENCY-1:0] par_mod_r;
wire calc_valid; // calculated registers have valid values
wire chn_en; // enable requests by channle (continue ones in progress)
wire chn_rst; // resets command, including fifo;
reg [1:0] xfer_page_r;
reg [2:0] page_cntr;
wire cmd_wrmem; // 0: read from memory, 1:write to memory
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
reg busy_r;
reg want_r;
reg need_r;
reg frame_done_r;
wire last_in_row_w;
wire last_row_w;
reg last_block;
reg [MCNTRL_TILED_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers
reg [NUM_RC_BURST_BITS-1:0] row_col_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r [1:0];
wire pre_want;
wire [1:0] status_data;
wire [3:0] cmd_a;
wire [31:0] cmd_data;
wire cmd_we;
wire set_mode_w;
wire set_status_w;
wire set_start_addr_w;
wire set_frame_width_w;
wire set_window_wh_w;
wire set_window_x0y0_w;
wire set_window_start_w;
wire lsw13_zero=!cmd_data[FRAME_WIDTH_BITS-1:0]; // LSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
wire msw13_zero=!cmd_data[FRAME_WIDTH_BITS+15:16]; // MSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
wire msw_zero= !cmd_data[31:16]; // MSW all bits are 0 - set carry bit
reg [5:0] mode_reg;//mode register: {keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_addr; // (programmed) Frame start (in {row,col8} in burst8, bank ==0
// reg [FRAME_WIDTH_BITS:0] frame_width; // (programmed) 0- max
//FIXME!!!!!!!!
reg [FRAME_WIDTH_BITS:0] frame_full_width; // (programmed) increment combined row/col when moving to the next line
// frame_width rounded up to max transfer (half page) if frame_width> max transfer/2,
// otherwise (smaller widths) round up to the nearest power of 2
reg [FRAME_WIDTH_BITS:0] window_width; // (programmed) 0- max
reg [FRAME_HEIGHT_BITS:0] window_height; // (programmed) 0- max
reg [FRAME_WIDTH_BITS-1:0] window_x0; // (programmed) window left
reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top
reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start
reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start
assign set_mode_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE);
assign set_status_w = cmd_we && (cmd_a== MCNTRL_TILED_STATUS_CNTRL);
assign set_start_addr_w = cmd_we && (cmd_a== MCNTRL_TILED_STARTADDR);
assign set_frame_width_w = cmd_we && (cmd_a== MCNTRL_TILED_FRAME_FULL_WIDTH);
assign set_window_wh_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_WH);
assign set_window_x0y0_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_X0Y0);
assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_STARTXY);
// Sett parameter registers
always @(posedge rst or posedge mclk) begin
if (rst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[5:0];
if (rst) start_addr <= 0;
else if (set_start_addr_w) start_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];
if (rst) frame_full_width <= 0;
else if (set_frame_width_w) frame_full_width <= {msw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
if (rst) begin
window_width <= 0;
window_height <= 0;
end else if (set_window_wh_w) begin
window_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
window_height <= {msw_zero,cmd_data[FRAME_HEIGHT_BITS+15:16]};
end
if (rst) begin
window_x0 <= 0;
window_y0 <= 0;
end else if (set_window_x0y0_w) begin
window_x0 <= cmd_data[FRAME_WIDTH_BITS-1:0];
window_y0 <=cmd_data[FRAME_HEIGHT_BITS+15:16];
end
if (rst) begin
start_x <= 0;
start_y <= 0;
end else if (set_window_start_w) begin
start_x <= cmd_data[FRAME_WIDTH_BITS-1:0];
start_y <=cmd_data[FRAME_HEIGHT_BITS+15:16];
end
end
assign mul_rslt_w= frame_y8_r * frame_full_width_r; // 5 MSBs will be discarded
assign xfer_num128= xfer_num128_r[NUM_XFER_BITS-1:0];
assign xfer_start= xfer_start_r[0];
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
assign xfer_page= xfer_page_r;
assign frame_done= frame_done_r;
assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
assign last_row_w= next_y==window_height;
assign xfer_want= want_r;
assign xfer_need= need_r;
assign xfer_bank= bank_reg[2]; // TODO: just a single reg layer
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished=line_unfinished_r[1];
assign chn_en = &mode_reg[1:0]; // enable requests by channle (continue ones in progress)
assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
assign cmd_wrmem = mode_reg[2];// 0: read from memory, 1:write to memory
assign cmd_extra_pages = mode_reg[4:3]; // external module needs more than 1 page
assign keep_open= mode_reg[4:3]; // keep banks open (will be used only if number of rows <= 8
assign status_data= {1'b0, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we;
integer i;
localparam EXTRA_BITS={COLADDR_NUMBER-3-COLADDR_NUMBER-3{1'b0}};
always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
frame_x <= curr_x + window_x0;
frame_y <= curr_y + window_y0;
next_y <= curr_y + 1;
row_left <= window_width - curr_x; // 14 bits - 13 bits
mem_page_left <= (1 << (COLADDR_NUMBER-3)) - frame_x[COLADDR_NUMBER-4:0];
lim_by_xfer <= (|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])?(1<<NUM_XFER_BITS):row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
xfer_num128_r<= (mem_page_left> {{EXTRA_BITS{1'b0}},lim_by_xfer})? mem_page_left[NUM_XFER_BITS:0]:lim_by_xfer[NUM_XFER_BITS:0];
// VDT bug? next line gives a warning
// xfer_num128_r<= (mem_page_left> {{COLADDR_NUMBER-3-COLADDR_NUMBER-3{1'b0}},lim_by_xfer})?mem_page_left[NUM_XFER_BITS-1:0]:lim_by_xfer[NUM_XFER_BITS-1:0];
last_in_row <= last_in_row_w;
frame_y8_r <= frame_y[FRAME_HEIGHT_BITS-1:3]; // lat=2
frame_full_width_r <= frame_full_width;
start_addr_r <= start_addr;
mul_rslt <= mul_rslt_w[MPY_WIDTH-1:0]; // frame_y8_r * frame_width_r; // 7 bits will be discarded lat=3;
line_start_addr <= start_addr_r+mul_rslt; // lat=4
row_col_r <= line_start_addr+frame_x;
bank_reg[0] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
for (i=0;i<2; i = i+1)
bank_reg[i+1] <= bank_reg[i];
end
// now have row start address, bank and row_left ;
// calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page
always @(posedge rst or posedge mclk) begin
if (rst) par_mod_r<=0;
else if (pgm_param_w || xfer_start_r[0] || chn_rst) par_mod_r<=0;
else par_mod_r <= {par_mod_r[PAR_MOD_LATENCY-2:0], 1'b1};
if (rst) busy_r <= 0;
else if (chn_rst) busy_r <= 0;
else if (frame_start) busy_r <= 1;
else if (frame_done_r) busy_r <= 0;
if (rst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (rst) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
else if (pre_want && (page_cntr>=3)) need_r <= 1;
if (rst) want_r <= 0;
else if (chn_rst || xfer_grant) want_r <= 0;
else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
if (rst) page_cntr <= 0;
else if (frame_start) page_cntr <= cmd_wrmem?0:4;
else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;
else if (!xfer_start_r[0] && next_page) page_cntr <= page_cntr - 1;
if (rst) xfer_page_r <= 0;
// else if (chn_rst || frame_start) xfer_page_r <= 0; // TODO: Check if it is better to keep xfer_page_r on frame start?
else if (chn_rst ) xfer_page_r <= 0; // TODO: Check if it is better to reset xfer_page_r on frame start? to zero?
else if (xfer_done) xfer_page_r <= xfer_page_r+1;
// increment x,y (two cycles)
if (rst) curr_x <= 0;
else if (chn_rst || frame_start) curr_x <= start_x;
else if (xfer_start_r[0]) curr_x <= last_in_row?0: curr_x + xfer_num128_r;
if (rst) curr_y <= 0;
else if (chn_rst || frame_start) curr_y <= start_y;
else if (xfer_start_r[0] && last_in_row) curr_y <= next_y[FRAME_HEIGHT_BITS-1:0];
if (rst) last_block <= 0;
else if (chn_rst || !busy_r) last_block <= 0;
else if (last_row_w && last_in_row_w) last_block <= 1;
if (rst) pending_xfers <= 0;
else if (chn_rst || !busy_r) pending_xfers <= 0;
else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;
else if (!xfer_start_r[0] && xfer_done) pending_xfers <= pending_xfers - 1;
if (rst) frame_done_r <= 0;
else frame_done_r <= busy_r && last_block && xfer_done && (pending_xfers==0);
//line_unfinished_r cmd_wrmem
if (rst) line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start) line_unfinished_r[0] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (rst) line_unfinished_r[1] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start) line_unfinished_r[1] <= window_y0+start_y;
// in read mode advance line number ASAP
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r[1] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
// in write mode advance line number only when it is guaranteed it will be the first to acyually access memory
else if (xfer_grant && cmd_wrmem) line_unfinished_r[1] <= line_unfinished_r[0];
end
cmd_deser #(
.ADDR (MCNTRL_TILED_ADDR),
.ADDR_MASK (MCNTRL_TILED_MASK),
.NUM_CYCLES (6),
.ADDR_WIDTH (4),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_ADDR),
.PAYLOAD_BITS (2)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
endmodule
memctrl/memctrl16.v
View file @ db31f7a9
......@@ -165,11 +165,11 @@ module memctrl16 #(
output seq_done0, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn0
output buf_wr_chn0, // @ negedge mclk
output [6:0] buf_waddr_chn0, // @ negedge mclk
output buf_waddr_rst_chn0, // @ negedge mclk
output [63:0] buf_wdata_chn0, // @ negedge mclk
`else
output buf_rd_chn0,
output [6:0] buf_raddr_chn0,
output buf_raddr_rst_chn0,
input [63:0] buf_rdata_chn0,
`endif
`endif
......@@ -185,11 +185,11 @@ module memctrl16 #(
output seq_done1, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn1
output buf_wr_chn1, // @ negedge mclk
output [6:0] buf_waddr_chn1,// @ negedge mclk
output buf_waddr_rst_chn1,// @ negedge mclk
output [63:0] buf_wdata_chn1,// @ negedge mclk
`else
output buf_rd_chn1,
output [6:0] buf_raddr_chn1,
output buf_raddr_rst_chn1,
input [63:0] buf_rdata_chn1,
`endif
`endif
......@@ -205,11 +205,11 @@ module memctrl16 #(
output seq_done2, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn2
output buf_wr_chn2,
output [6:0] buf_waddr_chn2,
output buf_waddr_rst_chn2,
output [63:0] buf_wdata_chn2,
`else
output buf_rd_chn2,
output [6:0] buf_raddr_chn2,
output buf_raddr_rst_chn2,
input [63:0] buf_rdata_chn2,
`endif
`endif
......@@ -225,11 +225,11 @@ module memctrl16 #(
output seq_done3, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn3
output buf_wr_chn3,
output [6:0] buf_waddr_chn3,
output buf_waddr_rst_chn3,
output [63:0] buf_wdata_chn3,
`else
output buf_rd_chn3,
output [6:0] buf_raddr_chn3,
output buf_raddr_rst_chn3,
input [63:0] buf_rdata_chn3,
`endif
`endif
......@@ -245,11 +245,11 @@ module memctrl16 #(
output seq_done4, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn4
output buf_wr_chn4, // @ negedge mclk
output [6:0] buf_waddr_chn4, // @ negedge mclk
output buf_waddr_rst_chn4, // @ negedge mclk
output [63:0] buf_wdata_chn4, // @ negedge mclk
`else
output buf_rd_chn4,
output [6:0] buf_raddr_chn4,
output buf_raddr_rst_chn4,
input [63:0] buf_rdata_chn4,
`endif
`endif
......@@ -265,11 +265,11 @@ module memctrl16 #(
output seq_done5, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn5
output buf_wr_chn5, // @ negedge mclk
output [6:0] buf_waddr_chn5, // @ negedge mclk
output buf_waddr_rst_chn5, // @ negedge mclk
output [63:0] buf_wdata_chn5, // @ negedge mclk
`else
output buf_rd_chn5,
output [6:0] buf_raddr_chn5,
output buf_raddr_rst_chn5,
input [63:0] buf_rdata_chn5,
`endif
`endif
......@@ -285,11 +285,11 @@ module memctrl16 #(
output seq_done6, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn6
output buf_wr_chn6, // @ negedge mclk
output [6:0] buf_waddr_chn6, // @ negedge mclk
output buf_waddr_rst_chn6, // @ negedge mclk
output [63:0] buf_wdata_chn6, // @ negedge mclk
`else
output buf_rd_chn6,
output [6:0] buf_raddr_chn6,
output buf_raddr_rst_chn6,
input [63:0] buf_rdata_chn6,
`endif
`endif
......@@ -305,11 +305,11 @@ module memctrl16 #(
output seq_done7, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn7
output buf_wr_chn7, // @ negedge mclk
output [6:0] buf_waddr_chn7, // @ negedge mclk
output buf_waddr_rst_chn7, // @ negedge mclk
output [63:0] buf_wdata_chn7, // @ negedge mclk
`else
output buf_rd_chn7,
output [6:0] buf_raddr_chn7,
output buf_raddr_rst_chn7,
input [63:0] buf_rdata_chn7,
`endif
`endif
......@@ -325,11 +325,11 @@ module memctrl16 #(
output seq_done8, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn8
output buf_wr_chn8, // @ negedge mclk
output [6:0] buf_waddr_chn8, // @ negedge mclk
output buf_waddr_rst_chn8, // @ negedge mclk
output [63:0] buf_wdata_chn8, // @ negedge mclk
`else
output buf_rd_chn8,
output [6:0] buf_raddr_chn8,
output buf_raddr_rst_chn8,
input [63:0] buf_rdata_chn8,
`endif
`endif
......@@ -345,11 +345,11 @@ module memctrl16 #(
output seq_done9, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn9
output buf_wr_chn9, // @ negedge mclk
output [6:0] buf_waddr_chn9, // @ negedge mclk
output buf_waddr_rst_chn9, // @ negedge mclk
output [63:0] buf_wdata_chn9, // @ negedge mclk
`else
output buf_rd_chn9,
output [6:0] buf_raddr_chn9,
output buf_raddr_rst_chn9,
input [63:0] buf_rdata_chn9,
`endif
`endif
......@@ -365,11 +365,11 @@ module memctrl16 #(
output seq_done10, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn10
output buf_wr_chn10, // @ negedge mclk
output [6:0] buf_waddr_chn10, // @ negedge mclk
output buf_waddr_rst_chn10, // @ negedge mclk
output [63:0] buf_wdata_chn10, // @ negedge mclk
`else
output buf_rd_chn10,
output [6:0] buf_raddr_chn10,
output buf_raddr_rst_chn10,
input [63:0] buf_rdata_chn10,
`endif
`endif
......@@ -385,11 +385,11 @@ module memctrl16 #(
output seq_done11, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn11
output buf_wr_chn11, // @ negedge mclk
output [6:0] buf_waddr_chn11, // @ negedge mclk
output buf_waddr_rst_chn11, // @ negedge mclk
output [63:0] buf_wdata_chn11, // @ negedge mclk
`else
output buf_rd_chn11,
output [6:0] buf_raddr_chn11,
output buf_raddr_rst_chn11,
input [63:0] buf_rdata_chn11,
`endif
`endif
......@@ -405,11 +405,11 @@ module memctrl16 #(
output seq_done12, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn12
output buf_wr_chn12, // @ negedge mclk
output [6:0] buf_waddr_chn12, // @ negedge mclk
output buf_waddr_rst_chn12, // @ negedge mclk
output [63:0] buf_wdata_chn12, // @ negedge mclk
`else
output buf_rd_chn12,
output [6:0] buf_raddr_chn12,
output buf_raddr_rst_chn12,
input [63:0] buf_rdata_chn12,
`endif
`endif
......@@ -425,11 +425,11 @@ module memctrl16 #(
output seq_done13, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn13
output buf_wr_chn13, // @ negedge mclk
output [6:0] buf_waddr_chn13, // @ negedge mclk
output buf_waddr_rst_chn13, // @ negedge mclk
output [63:0] buf_wdata_chn13, // @ negedge mclk
`else
output buf_rd_chn13,
output [6:0] buf_raddr_chn13,
output buf_raddr_rst_chn13,
input [63:0] buf_rdata_chn13,
`endif
`endif
......@@ -445,11 +445,11 @@ module memctrl16 #(
output seq_done14, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn14
output buf_wr_chn14, // @ negedge mclk
output [6:0] buf_waddr_chn14, // @ negedge mclk
output buf_waddr_rst_chn14, // @ negedge mclk
output [63:0] buf_wdata_chn14, // @ negedge mclk
`else
output buf_rd_chn14,
output [6:0] buf_raddr_chn14,
output buf_raddr_rst_chn14,
input [63:0] buf_rdata_chn14,
`endif
`endif
......@@ -465,11 +465,11 @@ module memctrl16 #(
output seq_done15, // sequencer finished executing sequence for this channel
`ifdef def_read_mem_chn15
output buf_wr_chn15, // @ negedge mclk
output [6:0] buf_waddr_chn15, // @ negedge mclk
output buf_waddr_rst_chn15, // @ negedge mclk
output [63:0] buf_wdata_chn15, // @ negedge mclk
`else
output buf_rd_chn15,
output [6:0] buf_raddr_chn15,
output buf_raddr_rst_chn15,
input [63:0] buf_rdata_chn15,
`endif
`endif
......@@ -507,11 +507,13 @@ module memctrl16 #(
wire rst=rst_in; // TODO: decide where toi generate
wire ext_buf_rd;
wire [6:0] ext_buf_raddr;
wire ext_buf_raddr_rst;
// wire [6:0] ext_buf_raddr;
wire [3:0] ext_buf_rchn;
wire [63:0] ext_buf_rdata;
wire ext_buf_wr;
wire [6:0] ext_buf_waddr;
wire ext_buf_waddr_rst;
// wire [6:0] ext_buf_waddr;
wire [3:0] ext_buf_wchn;
wire [63:0] ext_buf_wdata;
......@@ -910,11 +912,13 @@ end
.status_rq (status_rq_phy), // output
.status_start (status_start_phy), // input
.ext_buf_rd (ext_buf_rd), // output
.ext_buf_raddr (ext_buf_raddr), // output[6:0]
.ext_buf_raddr_rst (ext_buf_raddr_rst), // output[6:0]
// .ext_buf_raddr (ext_buf_raddr), // output[6:0]
.ext_buf_rchn (ext_buf_rchn), // output[3:0]
.ext_buf_rdata (ext_buf_rdata), // input[63:0]
.ext_buf_wr (ext_buf_wr), // output
.ext_buf_waddr (ext_buf_waddr), // output[6:0]
.ext_buf_waddr_rst (ext_buf_waddr_rst), // output[6:0]
// .ext_buf_waddr (ext_buf_waddr), // output[6:0]
.ext_buf_wchn (ext_buf_wchn), // output[3:0]
.ext_buf_wdata (ext_buf_wdata), // output[63:0]
.tmp_debug (tmp_debug) // output[11:0]
......@@ -923,176 +927,176 @@ end
// Registering existing channel buffers I/Os
`ifdef def_enable_mem_chn0
`ifdef def_read_mem_chn0
mcont_to_chnbuf_reg #(.CHN_NUMBER( 0)) mcont_to_chnbuf_reg0_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done0),.buf_wr_chn(buf_wr_chn0),.buf_waddr_chn(buf_waddr_chn0),.buf_wdata_chn(buf_wdata_chn0));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 0)) mcont_to_chnbuf_reg0_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done0),.buf_wr_chn(buf_wr_chn0),.buf_waddr_rst_chn(buf_waddr_rst_chn0),.buf_wdata_chn(buf_wdata_chn0));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 0),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg0_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done0),.buf_rd_chn(buf_rd_chn0),.buf_raddr_chn(buf_raddr_chn0),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done0),.buf_rd_chn(buf_rd_chn0),.buf_raddr_rst_chn(buf_raddr_rst_chn0),
.buf_rdata_chn (buf_rdata_chn0));
`endif
`endif
`ifdef def_enable_mem_chn1
`ifdef def_read_mem_chn1
mcont_to_chnbuf_reg #(.CHN_NUMBER( 1)) mcont_to_chnbuf_reg1_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done1),.buf_wr_chn(buf_wr_chn1),.buf_waddr_chn(buf_waddr_chn1),.buf_wdata_chn(buf_wdata_chn1));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 1)) mcont_to_chnbuf_reg1_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done1),.buf_wr_chn(buf_wr_chn1),.buf_waddr_rst_chn(buf_waddr_rst_chn1),.buf_wdata_chn(buf_wdata_chn1));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 1),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg1_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done1),.buf_rd_chn(buf_rd_chn1),.buf_raddr_chn(buf_raddr_chn1),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done1),.buf_rd_chn(buf_rd_chn1),.buf_raddr_rst_chn(buf_raddr_rst_chn1),
.buf_rdata_chn (buf_rdata_chn1));
`endif
`endif
`ifdef def_enable_mem_chn2
`ifdef def_read_mem_chn2
mcont_to_chnbuf_reg #(.CHN_NUMBER( 2)) mcont_to_chnbuf_reg2_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done2),.buf_wr_chn(buf_wr_chn2),.buf_waddr_chn(buf_waddr_chn2),.buf_wdata_chn(buf_wdata_chn2));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 2)) mcont_to_chnbuf_reg2_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done2),.buf_wr_chn(buf_wr_chn2),.buf_waddr_rst_chn(buf_waddr_rst_chn2),.buf_wdata_chn(buf_wdata_chn2));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 2),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg2_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done2),.buf_rd_chn(buf_rd_chn2),.buf_raddr_chn(buf_raddr_chn2),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done2),.buf_rd_chn(buf_rd_chn2),.buf_raddr_rst_chn(buf_raddr_rst_chn2),
.buf_rdata_chn (buf_rdata_chn2));
`endif
`endif
`ifdef def_enable_mem_chn3
`ifdef def_read_mem_chn3
mcont_to_chnbuf_reg #(.CHN_NUMBER( 3)) mcont_to_chnbuf_reg3_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done3),.buf_wr_chn(buf_wr_chn3),.buf_waddr_chn(buf_waddr_chn3),.buf_wdata_chn(buf_wdata_chn3));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 3)) mcont_to_chnbuf_reg3_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done3),.buf_wr_chn(buf_wr_chn3),.buf_waddr_rst_chn(buf_waddr_rst_chn3),.buf_wdata_chn(buf_wdata_chn3));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 3),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg3_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done3),.buf_rd_chn(buf_rd_chn3),.buf_raddr_chn(buf_raddr_chn3),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done3),.buf_rd_chn(buf_rd_chn3),.buf_raddr_rst_chn(buf_raddr_rst_chn3),
.buf_rdata_chn (buf_rdata_chn3));
`endif
`endif
`ifdef def_enable_mem_chn4
`ifdef def_read_mem_chn4
mcont_to_chnbuf_reg #(.CHN_NUMBER( 4)) mcont_to_chnbuf_reg4_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done4),.buf_wr_chn(buf_wr_chn4),.buf_waddr_chn(buf_waddr_chn4),.buf_wdata_chn(buf_wdata_chn4));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 4)) mcont_to_chnbuf_reg4_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done4),.buf_wr_chn(buf_wr_chn4),.buf_waddr_rst_chn(buf_waddr_rst_chn4),.buf_wdata_chn(buf_wdata_chn4));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 4),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg4_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done4),.buf_rd_chn(buf_rd_chn4),.buf_raddr_chn(buf_raddr_chn4),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done4),.buf_rd_chn(buf_rd_chn4),.buf_raddr_rst_chn(buf_raddr_rst_chn4),
.buf_rdata_chn (buf_rdata_chn4));
`endif
`endif
`ifdef def_enable_mem_chn5
`ifdef def_read_mem_chn5
mcont_to_chnbuf_reg #(.CHN_NUMBER( 5)) mcont_to_chnbuf_reg5_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done5),.buf_wr_chn(buf_wr_chn5),.buf_waddr_chn(buf_waddr_chn5),.buf_wdata_chn(buf_wdata_chn5));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 5)) mcont_to_chnbuf_reg5_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done5),.buf_wr_chn(buf_wr_chn5),.buf_waddr_rst_chn(buf_waddr_rst_chn5),.buf_wdata_chn(buf_wdata_chn5));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 5),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg5_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done5),.buf_rd_chn(buf_rd_chn5),.buf_raddr_chn(buf_raddr_chn5),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done5),.buf_rd_chn(buf_rd_chn5),.buf_raddr_rst_chn(buf_raddr_rst_chn5),
.buf_rdata_chn (buf_rdata_chn5));
`endif
`endif
`ifdef def_enable_mem_chn6
`ifdef def_read_mem_chn6
mcont_to_chnbuf_reg #(.CHN_NUMBER( 6)) mcont_to_chnbuf_reg6_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done6),.buf_wr_chn(buf_wr_chn6),.buf_waddr_chn(buf_waddr_chn6),.buf_wdata_chn(buf_wdata_chn6));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 6)) mcont_to_chnbuf_reg6_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done6),.buf_wr_chn(buf_wr_chn6),.buf_waddr_rst_chn(buf_waddr_rst_chn6),.buf_wdata_chn(buf_wdata_chn6));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 6),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg6_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done6),.buf_rd_chn(buf_rd_chn6),.buf_raddr_chn(buf_raddr_chn6),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done6),.buf_rd_chn(buf_rd_chn6),.buf_raddr_rst_chn(buf_raddr_rst_chn6),
.buf_rdata_chn (buf_rdata_chn6));
`endif
`endif
`ifdef def_enable_mem_chn7
`ifdef def_read_mem_chn7
mcont_to_chnbuf_reg #(.CHN_NUMBER( 7)) mcont_to_chnbuf_reg7_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done7),.buf_wr_chn(buf_wr_chn7),.buf_waddr_chn(buf_waddr_chn7),.buf_wdata_chn(buf_wdata_chn7));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 7)) mcont_to_chnbuf_reg7_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done7),.buf_wr_chn(buf_wr_chn7),.buf_waddr_rst_chn(buf_waddr_rst_chn7),.buf_wdata_chn(buf_wdata_chn7));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 7),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg7_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done7),.buf_rd_chn(buf_rd_chn7),.buf_raddr_chn(buf_raddr_chn7),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done7),.buf_rd_chn(buf_rd_chn7),.buf_raddr_rst_chn(buf_raddr_rst_chn7),
.buf_rdata_chn (buf_rdata_chn7));
`endif
`endif
`ifdef def_enable_mem_chn8
`ifdef def_read_mem_chn8
mcont_to_chnbuf_reg #(.CHN_NUMBER( 8)) mcont_to_chnbuf_reg8_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done8),.buf_wr_chn(buf_wr_chn8),.buf_waddr_chn(buf_waddr_chn8),.buf_wdata_chn(buf_wdata_chn8));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 8)) mcont_to_chnbuf_reg8_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done8),.buf_wr_chn(buf_wr_chn8),.buf_waddr_rst_chn(buf_waddr_rst_chn8),.buf_wdata_chn(buf_wdata_chn8));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 8),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg8_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done8),.buf_rd_chn(buf_rd_chn8),.buf_raddr_chn(buf_raddr_chn8),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done8),.buf_rd_chn(buf_rd_chn8),.buf_raddr_rst_chn(buf_raddr_rst_chn8),
.buf_rdata_chn (buf_rdata_chn8));
`endif
`endif
`ifdef def_enable_mem_chn9
`ifdef def_read_mem_chn9
mcont_to_chnbuf_reg #(.CHN_NUMBER( 9)) mcont_to_chnbuf_reg9_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done9),.buf_wr_chn(buf_wr_chn9),.buf_waddr_chn(buf_waddr_chn9),.buf_wdata_chn(buf_wdata_chn9));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 9)) mcont_to_chnbuf_reg9_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done9),.buf_wr_chn(buf_wr_chn9),.buf_waddr_rst_chn(buf_waddr_rst_chn9),.buf_wdata_chn(buf_wdata_chn9));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 9),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg9_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done9),.buf_rd_chn(buf_rd_chn9),.buf_raddr_chn(buf_raddr_chn9),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done9),.buf_rd_chn(buf_rd_chn9),.buf_raddr_rst_chn(buf_raddr_rst_chn9),
.buf_rdata_chn (buf_rdata_chn9));
`endif
`endif
`ifdef def_enable_mem_chn10
`ifdef def_read_mem_chn10
mcont_to_chnbuf_reg #(.CHN_NUMBER( 10)) mcont_to_chnbuf_reg10_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done10),.buf_wr_chn(buf_wr_chn10),.buf_waddr_chn(buf_waddr_chn10),.buf_wdata_chn(buf_wdata_chn10));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 10)) mcont_to_chnbuf_reg10_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done10),.buf_wr_chn(buf_wr_chn10),.buf_waddr_rst_chn(buf_waddr_rst_chn10),.buf_wdata_chn(buf_wdata_chn10));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 10),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg10_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done10),.buf_rd_chn(buf_rd_chn10),.buf_raddr_chn(buf_raddr_chn10),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done10),.buf_rd_chn(buf_rd_chn10),.buf_raddr_rst_chn(buf_raddr_rst_chn10),
.buf_rdata_chn (buf_rdata_chn10));
`endif
`endif
`ifdef def_enable_mem_chn11
`ifdef def_read_mem_chn11
mcont_to_chnbuf_reg #(.CHN_NUMBER( 11)) mcont_to_chnbuf_reg11_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done11),.buf_wr_chn(buf_wr_chn11),.buf_waddr_chn(buf_waddr_chn11),.buf_wdata_chn(buf_wdata_chn11));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 11)) mcont_to_chnbuf_reg11_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done11),.buf_wr_chn(buf_wr_chn11),.buf_waddr_rst_chn(buf_waddr_rst_chn11),.buf_wdata_chn(buf_wdata_chn11));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 11),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg11_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done11),.buf_rd_chn(buf_rd_chn11),.buf_raddr_chn(buf_raddr_chn11),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done11),.buf_rd_chn(buf_rd_chn11),.buf_raddr_rst_chn(buf_raddr_rst_chn11),
.buf_rdata_chn (buf_rdata_chn11));
`endif
`endif
`ifdef def_enable_mem_chn12
`ifdef def_read_mem_chn12
mcont_to_chnbuf_reg #(.CHN_NUMBER( 12)) mcont_to_chnbuf_reg12_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done12),.buf_wr_chn(buf_wr_chn12),.buf_waddr_chn(buf_waddr_chn12),.buf_wdata_chn(buf_wdata_chn12));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 12)) mcont_to_chnbuf_reg12_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done12),.buf_wr_chn(buf_wr_chn12),.buf_waddr_rst_chn(buf_waddr_rst_chn12),.buf_wdata_chn(buf_wdata_chn12));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 12),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg12_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done12),.buf_rd_chn(buf_rd_chn12),.buf_raddr_chn(buf_raddr_chn12),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done12),.buf_rd_chn(buf_rd_chn12),.buf_raddr_rst_chn(buf_raddr_rst_chn12),
.buf_rdata_chn (buf_rdata_chn12));
`endif
`endif
`ifdef def_enable_mem_chn13
`ifdef def_read_mem_chn13
mcont_to_chnbuf_reg #(.CHN_NUMBER( 13)) mcont_to_chnbuf_reg13_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done13),.buf_wr_chn(buf_wr_chn13),.buf_waddr_chn(buf_waddr_chn13),.buf_wdata_chn(buf_wdata_chn13));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 13)) mcont_to_chnbuf_reg13_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done13),.buf_wr_chn(buf_wr_chn13),.buf_waddr_rst_chn(buf_waddr_rst_chn13),.buf_wdata_chn(buf_wdata_chn13));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 13),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg13_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done13),.buf_rd_chn(buf_rd_chn13),.buf_raddr_chn(buf_raddr_chn13),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done13),.buf_rd_chn(buf_rd_chn13),.buf_raddr_rst_chn(buf_raddr_rst_chn13),
.buf_rdata_chn (buf_rdata_chn13));
`endif
`endif
`ifdef def_enable_mem_chn14
`ifdef def_read_mem_chn14
mcont_to_chnbuf_reg #(.CHN_NUMBER( 14)) mcont_to_chnbuf_reg14_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done14),.buf_wr_chn(buf_wr_chn14),.buf_waddr_chn(buf_waddr_chn14),.buf_wdata_chn(buf_wdata_chn14));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 14)) mcont_to_chnbuf_reg14_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done14),.buf_wr_chn(buf_wr_chn14),.buf_waddr_rst_chn(buf_waddr_rst_chn14),.buf_wdata_chn(buf_wdata_chn14));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 14),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg14_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done14),.buf_rd_chn(buf_rd_chn14),.buf_raddr_chn(buf_raddr_chn14),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done14),.buf_rd_chn(buf_rd_chn14),.buf_raddr_rst_chn(buf_raddr_rst_chn14),
.buf_rdata_chn (buf_rdata_chn14));
`endif
`endif
`ifdef def_enable_mem_chn15
`ifdef def_read_mem_chn15
mcont_to_chnbuf_reg #(.CHN_NUMBER( 15)) mcont_to_chnbuf_reg15_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr(ext_buf_waddr),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done15),.buf_wr_chn(buf_wr_chn15),.buf_waddr_chn(buf_waddr_chn15),.buf_wdata_chn(buf_wdata_chn15));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 15)) mcont_to_chnbuf_reg15_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done15),.buf_wr_chn(buf_wr_chn15),.buf_waddr_rst_chn(buf_waddr_rst_chn15),.buf_wdata_chn(buf_wdata_chn15));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 15),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg15_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr(ext_buf_raddr),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done15),.buf_rd_chn(buf_rd_chn15),.buf_raddr_chn(buf_raddr_chn15),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done15),.buf_rd_chn(buf_rd_chn15),.buf_raddr_rst_chn(buf_raddr_rst_chn15),
.buf_rdata_chn (buf_rdata_chn15));
`endif
`endif
......
phy/mcontr_sequencer.v
View file @ db31f7a9
......@@ -143,14 +143,17 @@ module mcontr_sequencer #(
// There will be =1 cycle external latency in address/re and 1 cycle latency in read data (should match sequence programs)
// Address data is sync to posedge mclk
output ext_buf_rd,
output [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
output ext_buf_raddr_rst, // reset external buffer address to page start
// output [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
output [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
input [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
// Interface to memory read channels (up to 16)
// Address/data sync to negedge mclk!, any latency OK - just generate DONE appropriately (through the sequencer with delay?
// folowing a sync to negedge!
output ext_buf_wr,
output [6:0] ext_buf_waddr, // valid with ext_buf_wr
output ext_buf_waddr_rst, // reset external buffer address to page start
// output [6:0] ext_buf_waddr, // valid with ext_buf_wr
output [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead of ext_buf_wr!, maybe not needed - will be generated externally
output [63:0] ext_buf_wdata, // valid with ext_buf_wr
// temporary debug data
......@@ -208,8 +211,10 @@ module mcontr_sequencer #(
wire [31:0] phy_cmd_word; // selected output from eithe cmd0 buffer or cmd1 buffer
wire [31:0] phy_cmd0_word; // cmd0 buffer output
wire [31:0] phy_cmd1_word; // cmd1 buffer output
reg [ 6:0] buf_raddr;
reg [ 6:0] buf_waddr_negedge;
wire buf_raddr_reset;
// reg [ 6:0] buf_raddr;
reg buf_waddr_reset_negedge;
// reg [ 6:0] buf_waddr_negedge;
reg buf_wr_negedge;
wire [63:0] buf_wdata; // output[63:0]
reg [63:0] buf_wdata_negedge; // output[63:0]
......@@ -260,13 +265,17 @@ module mcontr_sequencer #(
// assign buf_rdata[63:0] = ({64{buf_sel_1hot[1]}} & buf1_rdata[63:0]); // ORed with other read channels terms
// External buffers buffer related signals
assign buf_raddr_reset= run_seq_d;
assign ext_buf_rd= buf_rd;
assign ext_buf_raddr= buf_raddr;
assign ext_buf_raddr_rst=buf_raddr_reset;
// assign ext_buf_raddr= buf_raddr;
assign ext_buf_rchn= run_chn_d;
assign buf_rdata[63:0] = ext_buf_rdata;
assign ext_buf_wr= buf_wr_negedge;
assign ext_buf_waddr= buf_waddr_negedge;
assign ext_buf_waddr_rst=buf_waddr_reset_negedge;
// assign ext_buf_waddr= buf_waddr_negedge;
assign ext_buf_wchn= run_chn_d_negedge;
assign ext_buf_wdata= buf_wdata_negedge;
......@@ -426,9 +435,9 @@ module mcontr_sequencer #(
if (rst) cmd_sel <= 0;
else if (run_seq) cmd_sel <= run_addr[10];
if (rst) buf_raddr <= 7'h0;
else if (run_seq_d) buf_raddr <= 7'h0;
else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge //SuppressThisWarning ISExst Result of 10-bit expression is truncated to fit in 9-bit target.
// if (rst) buf_raddr <= 7'h0;
// else if (run_seq_d) buf_raddr <= 7'h0;
// else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge //SuppressThisWarning ISExst Result of 10-bit expression is truncated to fit in 9-bit target.
if (rst) run_chn_d <= 0;
else if (run_seq) run_chn_d <= run_chn;
......@@ -438,7 +447,8 @@ module mcontr_sequencer #(
end
// re-register buffer write address to match DDR3 data
always @ (negedge mclk) begin
buf_waddr_negedge <= buf_raddr;
// buf_waddr_negedge <= buf_raddr;
buf_waddr_reset_negedge <= buf_raddr_reset;
buf_wr_negedge <= buf_wr;
buf_wdata_negedge <= buf_wdata;
run_chn_d_negedge <= run_chn_d;
......
util_modules/mcont_from_chnbuf_reg.v
View file @ db31f7a9
......@@ -27,13 +27,15 @@ module mcont_from_chnbuf_reg #(
input rst,
input clk,
input ext_buf_rd,
input [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
input ext_buf_raddr_rst,
// input [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
input [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
input seq_done, // sequence done
output reg buf_done, // sequence done for the specified channel
output reg [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
output reg buf_rd_chn,
output reg [6:0] buf_raddr_chn,
output reg buf_raddr_rst_chn,
// output reg [6:0] buf_raddr_chn,
input [63:0] buf_rdata_chn
);
reg buf_chn_sel;
......@@ -51,7 +53,8 @@ module mcont_from_chnbuf_reg #(
if (rst) buf_done <= 0;
else buf_done <= buf_chn_sel && seq_done;
end
always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
always @ (posedge clk) buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
// always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;
endmodule
util_modules/mcont_to_chnbuf_reg.v
View file @ db31f7a9
......@@ -26,14 +26,16 @@ parameter CHN_NUMBER=0
input rst,
input clk,
input ext_buf_wr,
input [6:0] ext_buf_waddr, // valid with ext_buf_wr
input [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
input [63:0] ext_buf_wdata, // valid with ext_buf_wr
input seq_done, // sequence done
output reg buf_done, // @ posedge mclk sequence done for the specified channel
output reg buf_wr_chn, // @ negedge mclk
output reg [6:0] buf_waddr_chn, // @ negedge mclk
output reg [63:0] buf_wdata_chn // @ negedge mclk
input ext_buf_waddr_rst,
// input [6:0] ext_buf_waddr, // valid with ext_buf_wr
input [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
input [63:0] ext_buf_wdata, // valid with ext_buf_wr
input seq_done, // sequence done
output reg buf_done, // @ posedge mclk sequence done for the specified channel
output reg buf_wr_chn, // @ negedge mclk
output reg buf_waddr_rst_chn,// @ negedge mclk
// output reg [6:0] buf_waddr_chn, // @ negedge mclk
output reg [63:0] buf_wdata_chn // @ negedge mclk
);
reg buf_chn_sel;
always @ (posedge rst or negedge clk) begin
......@@ -49,9 +51,12 @@ parameter CHN_NUMBER=0
else buf_done <= buf_chn_sel && seq_done;
end
always @ (negedge clk) begin
buf_waddr_rst_chn <= ext_buf_waddr_rst && (ext_buf_wchn==CHN_NUMBER);
end
always @ (negedge clk) if (buf_chn_sel && ext_buf_wr) begin
buf_waddr_chn <= ext_buf_waddr;
// buf_waddr_chn <= ext_buf_waddr;
buf_wdata_chn <= ext_buf_wdata;
end
endmodule
......
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