Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393
Commits
c72a52a9
Commit
c72a52a9
authored
May 31, 2014
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
added warnings for illegal fine delays
parent
4bacb90a
Changes
2
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
10 additions
and
0 deletions
+10
-0
idelay_fine_pipe.v
wrap/idelay_fine_pipe.v
+5
-0
odelay_fine_pipe.v
wrap/odelay_fine_pipe.v
+5
-0
No files found.
wrap/idelay_fine_pipe.v
View file @
c72a52a9
...
...
@@ -43,6 +43,11 @@ module idelay_fine_pipe
if
(
rst
)
fdly
<=
DELAY_VALUE
[
2
:
0
]
;
else
if
(
set
)
fdly
<=
fdly_pre
;
end
`ifdef
IVERILOG
always
@
(
fdly_pre
)
begin
if
(
fdly_pre
>
3'h4
)
$
display
(
"ERROR: fine idelay value should be <5, specified %d @ %t"
,
fdly_pre
,
$
time
)
;
end
`endif
(
*
IODELAY_GROUP
=
IODELAY_GRP
*
)
IDELAYE2_FINEDELAY
#(
.
CINVCTRL_SEL
(
"FALSE"
)
,
...
...
wrap/odelay_fine_pipe.v
View file @
c72a52a9
...
...
@@ -42,6 +42,11 @@ module odelay_fine_pipe
if
(
rst
)
fdly
<=
DELAY_VALUE
[
2
:
0
]
;
else
if
(
set
)
fdly
<=
fdly_pre
;
end
`ifdef
IVERILOG
always
@
(
fdly_pre
)
begin
if
(
fdly_pre
>
3'h4
)
$
display
(
"ERROR: fine odelay value should be <5, specified %d @ %t"
,
fdly_pre
,
$
time
)
;
end
`endif
(
*
IODELAY_GROUP
=
IODELAY_GRP
*
)
ODELAYE2_FINEDELAY
#(
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment