From c72a52a9b632e33e788a18374f9c6286200bc4e4 Mon Sep 17 00:00:00 2001
From: Andrey Filippov <andrey@elphel.com>
Date: Sat, 31 May 2014 00:26:54 -0600
Subject: [PATCH] added warnings for illegal fine delays

---
 wrap/idelay_fine_pipe.v | 5 +++++
 wrap/odelay_fine_pipe.v | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/wrap/idelay_fine_pipe.v b/wrap/idelay_fine_pipe.v
index 2a68aee..8d6a569 100644
--- a/wrap/idelay_fine_pipe.v
+++ b/wrap/idelay_fine_pipe.v
@@ -43,6 +43,11 @@ module  idelay_fine_pipe
         if (rst)      fdly <= DELAY_VALUE[2:0];
         else if (set) fdly <= fdly_pre;
     end
+    `ifdef IVERILOG
+        always @ (fdly_pre) begin
+            if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  
+        end
+    `endif
 (* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2_FINEDELAY
      #(
         .CINVCTRL_SEL("FALSE"),
diff --git a/wrap/odelay_fine_pipe.v b/wrap/odelay_fine_pipe.v
index 8da688f..7ee260f 100644
--- a/wrap/odelay_fine_pipe.v
+++ b/wrap/odelay_fine_pipe.v
@@ -42,6 +42,11 @@ module  odelay_fine_pipe
         if (rst)      fdly <= DELAY_VALUE[2:0];
         else if (set) fdly <= fdly_pre;
     end
+    `ifdef IVERILOG
+        always @ (fdly_pre) begin
+            if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);  
+        end
+    `endif
  
  (* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2_FINEDELAY
      #(
-- 
2.18.1