Commit c72a52a9 authored by Andrey Filippov's avatar Andrey Filippov

added warnings for illegal fine delays

parent 4bacb90a
......@@ -43,6 +43,11 @@ module idelay_fine_pipe
if (rst) fdly <= DELAY_VALUE[2:0];
else if (set) fdly <= fdly_pre;
end
`ifdef IVERILOG
always @ (fdly_pre) begin
if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);
end
`endif
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2_FINEDELAY
#(
.CINVCTRL_SEL("FALSE"),
......
......@@ -42,6 +42,11 @@ module odelay_fine_pipe
if (rst) fdly <= DELAY_VALUE[2:0];
else if (set) fdly <= fdly_pre;
end
`ifdef IVERILOG
always @ (fdly_pre) begin
if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);
end
`endif
(* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2_FINEDELAY
#(
......
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