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Commit baa32a59 authored by Andrey Filippov's avatar Andrey Filippov
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replaced non-memory 2-d arrays with 1-d ones, added _ram suffix to all memories

parent 3946f6c4
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axi/cmprs_afi_mux.v
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axi/cmprs_afi_mux_status.v
View file @ baa32a59
...@@ -49,22 +49,21 @@ module cmprs_afi_mux_status #( ...@@ -49,22 +49,21 @@ module cmprs_afi_mux_status #(
reg [15:0] mode_data_mclk; // some bits unused reg [15:0] mode_data_mclk; // some bits unused
wire mode_we_hclk; wire mode_we_hclk;
reg [7:0] mode_hclk; reg [7:0] mode_hclk;
// wire [1:0] sel[0:3]={mode_hclk[7:6],mode_hclk[5:4],mode_hclk[3:2],mode_hclk[1:0]};
reg [1:0] index; reg [1:0] index;
reg [CMPRS_AFIMUX_CYCBITS-1:0] cntr; reg [CMPRS_AFIMUX_CYCBITS-1:0] cntr;
reg [CMPRS_AFIMUX_WIDTH-1:0] chunk_ptr_hclk; // pointer data reg [CMPRS_AFIMUX_WIDTH-1:0] chunk_ptr_hclk; // pointer data
reg [1:0] chunk_chn_hclk; // pointer channel reg [1:0] chunk_chn_hclk; // pointer channel
reg [CMPRS_AFIMUX_WIDTH-1:0] status_data[0:3]; reg [4 * CMPRS_AFIMUX_WIDTH-1:0] status_data;
wire stb_w; wire stb_w;
reg stb_r; reg stb_r;
wire stb_mclk; wire stb_mclk;
wire [7:0] ad[0:3]; wire [31:0] ad;
wire [3:0] rq; wire [3:0] rq;
wire [3:0] start; wire [3:0] start;
assign stb_w = en && (cntr==0); assign stb_w = en && (cntr==0);
always @ (posedge mclk) begin always @ (posedge mclk) begin
...@@ -78,7 +77,7 @@ module cmprs_afi_mux_status #( ...@@ -78,7 +77,7 @@ module cmprs_afi_mux_status #(
if (mode_data_mclk[10]) mode_hclk[5:4] <= mode_data_mclk[ 9: 8]; if (mode_data_mclk[10]) mode_hclk[5:4] <= mode_data_mclk[ 9: 8];
if (mode_data_mclk[14]) mode_hclk[7:6] <= mode_data_mclk[13:12]; if (mode_data_mclk[14]) mode_hclk[7:6] <= mode_data_mclk[13:12];
if (stb_mclk) status_data[chunk_chn_hclk] <= chunk_ptr_hclk; if (stb_mclk) status_data[chunk_chn_hclk * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH] <= chunk_ptr_hclk;
end end
if (!en) {index,cntr} <= 0; if (!en) {index,cntr} <= 0;
...@@ -104,80 +103,80 @@ module cmprs_afi_mux_status #( ...@@ -104,80 +103,80 @@ module cmprs_afi_mux_status #(
pulse_cross_clock mode_we_hclk_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(mode_we), .out_pulse(mode_we_hclk),.busy()); pulse_cross_clock mode_we_hclk_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(mode_we), .out_pulse(mode_we_hclk),.busy());
pulse_cross_clock stb_mclk_i (.rst(rst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(stb_r), .out_pulse(stb_mclk), .busy()); pulse_cross_clock stb_mclk_i (.rst(rst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(stb_r), .out_pulse(stb_mclk), .busy());
status_router4 status_router4_i ( status_router4 status_router4_i (
.rst (rst), // input .rst (rst), // input
.clk (mclk), // input .clk (mclk), // input
.db_in0 (ad[0]), // input[7:0] .db_in0 (ad[0 * 8 +: 8]), // input[7:0]
.rq_in0 (rq[0]), // input .rq_in0 (rq[0]), // input
.start_in0 (start[0]), // output .start_in0 (start[0]), // output
.db_in1 (ad[1]), // input[7:0] .db_in1 (ad[1 * 8 +: 8]), // input[7:0]
.rq_in1 (rq[1]), // input .rq_in1 (rq[1]), // input
.start_in1 (start[1]), // output .start_in1 (start[1]), // output
.db_in2 (ad[2]), // input[7:0] .db_in2 (ad[2 * 8 +: 8]), // input[7:0]
.rq_in2 (rq[2]), // input .rq_in2 (rq[2]), // input
.start_in2 (start[2]), // output .start_in2 (start[2]), // output
.db_in3 (ad[3]), // input[7:0] .db_in3 (ad[3 * 8 +: 8]), // input[7:0]
.rq_in3 (rq[3]), // input .rq_in3 (rq[3]), // input
.start_in3 (start[3]), // output .start_in3 (start[3]), // output
.db_out (status_ad), // output[7:0] .db_out (status_ad), // output[7:0]
.rq_out (status_rq), // output .rq_out (status_rq), // output
.start_out (status_start) // input .start_out (status_start) // input
); );
status_generate #( status_generate #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0), .STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH) .PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate0_i ( ) status_generate0_i (
.rst (rst), // input .rst (rst), // input
.clk (mclk), // input .clk (mclk), // input
.we (status_we && (cmd_a==0)), // input .we (status_we && (cmd_a==0)), // input
.wd (cmd_data[7:0]), // input[7:0] .wd (cmd_data[7:0]), // input[7:0]
.status (status_data[0]), // input[25:0] .status (status_data[0 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
.ad (ad[0]), // output[7:0] .ad (ad[0 * 8 +: 8]), // output[7:0]
.rq (rq[0]), // output .rq (rq[0]), // output
.start (start[0]) // input .start (start[0]) // input
); );
status_generate #( status_generate #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0), .STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH) .PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate1_i ( ) status_generate1_i (
.rst (rst), // input .rst (rst), // input
.clk (mclk), // input .clk (mclk), // input
.we (status_we && (cmd_a==1)), // input .we (status_we && (cmd_a==1)), // input
.wd (cmd_data[7:0]), // input[7:0] .wd (cmd_data[7:0]), // input[7:0]
.status (status_data[1]), // input[25:0] .status (status_data[1 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
.ad (ad[1]), // output[7:0] .ad (ad[1 * 8 +: 8]), // output[7:0]
.rq (rq[1]), // output .rq (rq[1]), // output
.start (start[1]) // input .start (start[1]) // input
); );
status_generate #( status_generate #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0), .STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH) .PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate2_i ( ) status_generate2_i (
.rst (rst), // input .rst (rst), // input
.clk (mclk), // input .clk (mclk), // input
.we (status_we && (cmd_a==2)), // input .we (status_we && (cmd_a==2)), // input
.wd (cmd_data[7:0]), // input[7:0] .wd (cmd_data[7:0]), // input[7:0]
.status (status_data[2]), // input[25:0] .status (status_data[2 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
.ad (ad[2]), // output[7:0] .ad (ad[2 * 8 +: 8]), // output[7:0]
.rq (rq[2]), // output .rq (rq[2]), // output
.start (start[2]) // input .start (start[2]) // input
); );
status_generate #( status_generate #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0), .STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH) .PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate3_i ( ) status_generate3_i (
.rst (rst), // input .rst (rst), // input
.clk (mclk), // input .clk (mclk), // input
.we (status_we && (cmd_a==3)), // input .we (status_we && (cmd_a==3)), // input
.wd (cmd_data[7:0]), // input[7:0] .wd (cmd_data[7:0]), // input[7:0]
.status (status_data[3]), // input[25:0] .status (status_data[3 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
.ad (ad[3]), // output[7:0] .ad (ad[3 * 8 +: 8]), // output[7:0]
.rq (rq[3]), // output .rq (rq[3]), // output
.start (start[3]) // input .start (start[3]) // input
); );
endmodule endmodule
......
axi/histogram_saxi.v
View file @ baa32a59
...@@ -103,7 +103,7 @@ module histogram_saxi#( ...@@ -103,7 +103,7 @@ module histogram_saxi#(
); );
localparam ATTRIB_WIDTH = NUM_FRAME_BITS + 4 +2;
reg [HIST_SAXI_MODE_WIDTH-1:0] mode; reg [HIST_SAXI_MODE_WIDTH-1:0] mode;
wire en = mode[HIST_SAXI_EN] & mode[HIST_SAXI_NRESET]; wire en = mode[HIST_SAXI_EN] & mode[HIST_SAXI_NRESET];
reg [3:0] awcache_mode; reg [3:0] awcache_mode;
...@@ -123,7 +123,7 @@ module histogram_saxi#( ...@@ -123,7 +123,7 @@ module histogram_saxi#(
reg [1:0] mux_sel; reg [1:0] mux_sel;
wire start_w; wire start_w;
reg started; reg started;
reg [NUM_FRAME_BITS + 4 +2 -1:0] attrib [0:3]; // to hold frame number, sensor number and burst (color) for the histograms in the buffer reg [ATTRIB_WIDTH -1:0] attrib; // to hold frame number, sensor number and burst (color) for the histograms in the buffer
wire page_sent_mclk; // page sent over saxi - pulse in mclk domain wire page_sent_mclk; // page sent over saxi - pulse in mclk domain
reg [1:0] page_wr; // page number being written reg [1:0] page_wr; // page number being written
reg [7:0] page_wa; // 32-bit word address in page being written reg [7:0] page_wa; // 32-bit word address in page being written
...@@ -292,7 +292,7 @@ module histogram_saxi#( ...@@ -292,7 +292,7 @@ module histogram_saxi#(
wr_attr <= en && !dav_r && dav; wr_attr <= en && !dav_r && dav;
if (wr_attr) attrib[page_wr] <= {enc_rq[1:0], sub_chn_r, frame_r, burst[1:0]}; if (wr_attr) attrib[page_wr * ATTRIB_WIDTH +: ATTRIB_WIDTH] <= {enc_rq[1:0], sub_chn_r, frame_r, burst[1:0]};
if (!dav_r) page_wa <= 0; if (!dav_r) page_wa <= 0;
else page_wa <= page_wa + 1; else page_wa <= page_wa + 1;
...@@ -322,7 +322,7 @@ module histogram_saxi#( ...@@ -322,7 +322,7 @@ module histogram_saxi#(
if (!en_aclk) block_start_r <= 0; if (!en_aclk) block_start_r <= 0;
else block_start_r <= {block_run[2:0], block_start_w}; else block_start_r <= {block_run[2:0], block_start_w};
if (block_start_r[0]) attrib_r <= attrib[page_rd]; if (block_start_r[0]) attrib_r <= attrib[page_rd * ATTRIB_WIDTH +: ATTRIB_WIDTH];
if (block_start_r[1]) hist_start_page_r <= hist_start_page[attrib_chn]; if (block_start_r[1]) hist_start_page_r <= hist_start_page[attrib_chn];
if (block_start_r[2]) hist_start_addr[31:12] <= hist_start_page_r + attrib_frame; if (block_start_r[2]) hist_start_addr[31:12] <= hist_start_page_r + attrib_frame;
......
axi/mult_saxi_wr.v
View file @ baa32a59
...@@ -103,6 +103,7 @@ module mult_saxi_wr #( ...@@ -103,6 +103,7 @@ module mult_saxi_wr #(
// localparam BURSTS_CAP0= (MULT_SAXI_HALF_BRAM ? 'h400 : 'h800 ) / MULT_SAXI_BURST0 / 4; // localparam BURSTS_CAP0= (MULT_SAXI_HALF_BRAM ? 'h400 : 'h800 ) / MULT_SAXI_BURST0 / 4;
localparam BRAM_A_WDTH = MULT_SAXI_HALF_BRAM?9:10; localparam BRAM_A_WDTH = MULT_SAXI_HALF_BRAM?9:10;
localparam CHN_A_WDTH = BRAM_A_WDTH - 2;
wire [3:0] en_chn_mclk; wire [3:0] en_chn_mclk;
wire [3:0] run_chn_mclk; wire [3:0] run_chn_mclk;
...@@ -112,16 +113,16 @@ module mult_saxi_wr #( ...@@ -112,16 +113,16 @@ module mult_saxi_wr #(
wire en_aclk= |en_chn_aclk; // at least one channel enabled wire en_aclk= |en_chn_aclk; // at least one channel enabled
wire [3:0] rq_wr; wire [3:0] rq_wr;
wire [3:0] grant_wr; wire [3:0] grant_wr;
wire [BRAM_A_WDTH-3:0] wa_chn[0:3]; wire [4 * CHN_A_WDTH - 1:0] wa_chn;
wire [3:0] adv_wr_done; // outputs grant_wr for short bursts, or several clocks before end of wr wire [3:0] adv_wr_done; // outputs grant_wr for short bursts, or several clocks before end of wr
wire [3:0] rq_out_chn; wire [3:0] rq_out_chn;
wire [BRAM_A_WDTH-3:0] ra_chn[0:3]; wire [4 * CHN_A_WDTH - 1:0] ra_chn;
wire [3:0] pre_re; wire [3:0] pre_re;
reg en_we_arb; // @mclk should be reset by we_grant reg en_we_arb; // @mclk should be reset by we_grant
wire we_grant; // @mclk wire we_grant; // @mclk
wire [1:0] we_cur_chn; // @mclk wire [1:0] we_cur_chn; // @mclk
wire [31:0] data_in[0:3]; wire [127:0] data_in;
wire [3:0] pre_valid; wire [3:0] pre_valid;
reg [3:0] valid; reg [3:0] valid;
reg [BRAM_A_WDTH-1:0] buf_wa; // multiplexed buffer write adderss reg [BRAM_A_WDTH-1:0] buf_wa; // multiplexed buffer write adderss
...@@ -152,10 +153,7 @@ module mult_saxi_wr #( ...@@ -152,10 +153,7 @@ module mult_saxi_wr #(
assign {en_chn3, en_chn2, en_chn1, en_chn0} = en_chn_mclk; assign {en_chn3, en_chn2, en_chn1, en_chn0} = en_chn_mclk;
assign {read_burst3, read_burst2, read_burst1, read_burst0} = grant_wr; // single clock pulse assign {read_burst3, read_burst2, read_burst1, read_burst0} = grant_wr; // single clock pulse
assign data_in[0] = data_in_chn0; assign data_in = {data_in_chn3, data_in_chn2, data_in_chn1, data_in_chn0};
assign data_in[1] = data_in_chn1;
assign data_in[2] = data_in_chn2;
assign data_in[3] = data_in_chn3;
assign pre_valid = {pre_valid_chn3, pre_valid_chn2, pre_valid_chn1, pre_valid_chn0}; assign pre_valid = {pre_valid_chn3, pre_valid_chn2, pre_valid_chn1, pre_valid_chn0};
assign en_chn_mclk = mode_reg[3:0]; assign en_chn_mclk = mode_reg[3:0];
...@@ -182,12 +180,12 @@ module mult_saxi_wr #( ...@@ -182,12 +180,12 @@ module mult_saxi_wr #(
.valid (valid[0]), // input .valid (valid[0]), // input
.rq_wr (rq_wr[0]), // output .rq_wr (rq_wr[0]), // output
.grant_wr (grant_wr[0]), // input .grant_wr (grant_wr[0]), // input
.wa (wa_chn[0]), // output[7:0] .wa (wa_chn[0 * CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
.adv_wr_done (adv_wr_done[0]), // output .adv_wr_done (adv_wr_done[0]), // output
.rq_out (rq_out_chn[0]), // output reg .rq_out (rq_out_chn[0]), // output reg
.grant_out (grant_rd[0]), // input .grant_out (grant_rd[0]), // input
.fifo_half_full(fifo_half_full), // input .fifo_half_full(fifo_half_full), // input
.ra (ra_chn[0]), // output[7:0] .ra (ra_chn[0* CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
.pre_re (pre_re[0]), // output .pre_re (pre_re[0]), // output
.first_re (first_re[0]), // output reg // 1 clock later than pre_re .first_re (first_re[0]), // output reg // 1 clock later than pre_re
.last_re (last_re[0]), // output reg // 1 clock later than pre_re .last_re (last_re[0]), // output reg // 1 clock later than pre_re
...@@ -207,12 +205,12 @@ module mult_saxi_wr #( ...@@ -207,12 +205,12 @@ module mult_saxi_wr #(
.valid (valid[1]), // input .valid (valid[1]), // input
.rq_wr (rq_wr[1]), // output .rq_wr (rq_wr[1]), // output
.grant_wr (grant_wr[1]), // input .grant_wr (grant_wr[1]), // input
.wa (wa_chn[1]), // output[7:0] .wa (wa_chn[1 * CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
.adv_wr_done (adv_wr_done[1]), // output .adv_wr_done (adv_wr_done[1]), // output
.rq_out (rq_out_chn[1]), // output reg .rq_out (rq_out_chn[1]), // output reg
.grant_out (grant_rd[1]), // input .grant_out (grant_rd[1]), // input
.fifo_half_full(fifo_half_full), // input .fifo_half_full(fifo_half_full), // input
.ra (ra_chn[1]), // output[7:0] .ra (ra_chn[1* CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
.pre_re (pre_re[1]), // output .pre_re (pre_re[1]), // output
.first_re (first_re[1]), // output reg // 1 clock later than pre_re .first_re (first_re[1]), // output reg // 1 clock later than pre_re
.last_re (last_re[1]), // output reg // 1 clock later than pre_re .last_re (last_re[1]), // output reg // 1 clock later than pre_re
...@@ -232,12 +230,12 @@ module mult_saxi_wr #( ...@@ -232,12 +230,12 @@ module mult_saxi_wr #(
.valid (valid[2]), // input .valid (valid[2]), // input
.rq_wr (rq_wr[2]), // output .rq_wr (rq_wr[2]), // output
.grant_wr (grant_wr[2]), // input .grant_wr (grant_wr[2]), // input
.wa (wa_chn[2]), // output[7:0] .wa (wa_chn[2 * CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
.adv_wr_done (adv_wr_done[2]), // output .adv_wr_done (adv_wr_done[2]), // output
.rq_out (rq_out_chn[2]), // output reg .rq_out (rq_out_chn[2]), // output reg
.grant_out (grant_rd[2]), // input .grant_out (grant_rd[2]), // input
.fifo_half_full(fifo_half_full), // input .fifo_half_full(fifo_half_full), // input
.ra (ra_chn[2]), // output[7:0] .ra (ra_chn[2* CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
.pre_re (pre_re[2]), // output .pre_re (pre_re[2]), // output
.first_re (first_re[2]), // output reg // 1 clock later than pre_re .first_re (first_re[2]), // output reg // 1 clock later than pre_re
.last_re (last_re[2]), // output reg // 1 clock later than pre_re .last_re (last_re[2]), // output reg // 1 clock later than pre_re
...@@ -257,12 +255,12 @@ module mult_saxi_wr #( ...@@ -257,12 +255,12 @@ module mult_saxi_wr #(
.valid (valid[3]), // input .valid (valid[3]), // input
.rq_wr (rq_wr[3]), // output .rq_wr (rq_wr[3]), // output
.grant_wr (grant_wr[3]), // input .grant_wr (grant_wr[3]), // input
.wa (wa_chn[3]), // output[7:0] .wa (wa_chn[3 * CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
.adv_wr_done (adv_wr_done[3]), // output .adv_wr_done (adv_wr_done[3]), // output
.rq_out (rq_out_chn[3]), // output reg .rq_out (rq_out_chn[3]), // output reg
.grant_out (grant_rd[3]), // input .grant_out (grant_rd[3]), // input
.fifo_half_full(fifo_half_full), // input .fifo_half_full(fifo_half_full), // input
.ra (ra_chn[3]), // output[7:0] .ra (ra_chn[3* CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
.pre_re (pre_re[3]), // output .pre_re (pre_re[3]), // output
.first_re (first_re[3]), // output reg // 1 clock later than pre_re .first_re (first_re[3]), // output reg // 1 clock later than pre_re
.last_re (last_re[3]), // output reg // 1 clock later than pre_re .last_re (last_re[3]), // output reg // 1 clock later than pre_re
...@@ -299,8 +297,8 @@ module mult_saxi_wr #( ...@@ -299,8 +297,8 @@ module mult_saxi_wr #(
if (pre_pre_buf_we && !pre_buf_we) chn_wr <= we_cur_chn; // to re-start arbitration early if (pre_pre_buf_we && !pre_buf_we) chn_wr <= we_cur_chn; // to re-start arbitration early
// multiplex address and data // multiplex address and data
buf_wa <= {chn_wr, wa_chn[chn_wr]}; buf_wa <= {chn_wr, wa_chn[chn_wr * CHN_A_WDTH +: CHN_A_WDTH]};
buf_wd <= data_in[chn_wr]; buf_wd <= data_in[chn_wr* 32 +: 32];
// early re-enable arbitration (en_we_arb) // early re-enable arbitration (en_we_arb)
if (!en_mclk || adv_wr_done[chn_wr]) en_we_arb <= 1; if (!en_mclk || adv_wr_done[chn_wr]) en_we_arb <= 1;
else if (we_grant) en_we_arb <= 0; else if (we_grant) en_we_arb <= 0;
...@@ -318,7 +316,7 @@ module mult_saxi_wr #( ...@@ -318,7 +316,7 @@ module mult_saxi_wr #(
always @ (posedge aclk) begin always @ (posedge aclk) begin
en_chn_aclk <=en_chn_mclk; en_chn_aclk <=en_chn_mclk;
chn_rd <= re_cur_chn; // delay by 1 clock (to increase overlap) chn_rd <= re_cur_chn; // delay by 1 clock (to increase overlap)
buf_ra <= {chn_rd, ra_chn[chn_rd]}; buf_ra <= {chn_rd, ra_chn[chn_rd* CHN_A_WDTH +: CHN_A_WDTH]};
buf_re <= {buf_re[1:0], pre_re[chn_rd]}; buf_re <= {buf_re[1:0], pre_re[chn_rd]};
pre_first_rd_valid <= first_re[chn_rd]; pre_first_rd_valid <= first_re[chn_rd];
is_last_rd <= {is_last_rd[0], last_re[chn_rd]}; is_last_rd <= {is_last_rd[0], last_re[chn_rd]};
......
compressor_jp/encoderDCAC393.v
View file @ baa32a59
...@@ -77,8 +77,8 @@ module encoderDCAC393( ...@@ -77,8 +77,8 @@ module encoderDCAC393(
reg [2:0] block_mem_ra; reg [2:0] block_mem_ra;
reg [2:0] block_mem_wa; reg [2:0] block_mem_wa;
reg [2:0] block_mem_wa_save; reg [2:0] block_mem_wa_save;
reg [6:0] block_mem[0:7]; reg [6:0] block_mem_ram[0:7];
wire [6:0] block_mem_o=block_mem[block_mem_ra[2:0]]; wire [6:0] block_mem_o=block_mem_ram[block_mem_ra[2:0]];
assign comp_numbero[2:0]= block_mem_o[2:0]; assign comp_numbero[2:0]= block_mem_o[2:0];
assign comp_firsto= block_mem_o[3]; assign comp_firsto= block_mem_o[3];
...@@ -86,7 +86,7 @@ module encoderDCAC393( ...@@ -86,7 +86,7 @@ module encoderDCAC393(
assign comp_lastinmbo= block_mem_o[5]; assign comp_lastinmbo= block_mem_o[5];
assign lasto= block_mem_o[6]; assign lasto= block_mem_o[6];
always @ (posedge clk) begin always @ (posedge clk) begin
if (stb) block_mem[block_mem_wa[2:0]] <= {lasti, comp_lastinmbi, comp_colori,comp_firsti,comp_numberi[2:0]}; if (stb) block_mem_ram[block_mem_wa[2:0]] <= {lasti, comp_lastinmbi, comp_colori,comp_firsti,comp_numberi[2:0]};
if (!en) block_mem_wa[2:0] <= 3'h0; if (!en) block_mem_wa[2:0] <= 3'h0;
else if (stb) block_mem_wa[2:0] <= block_mem_wa[2:0] +1; else if (stb) block_mem_wa[2:0] <= block_mem_wa[2:0] +1;
......
compressor_jp/quantizer393.v
View file @ baa32a59
...@@ -112,8 +112,8 @@ module quantizer393( ...@@ -112,8 +112,8 @@ module quantizer393(
reg [ 2:0] block_mem_ra; reg [ 2:0] block_mem_ra;
reg [ 2:0] block_mem_wa; reg [ 2:0] block_mem_wa;
reg [ 2:0] block_mem_wa_save; reg [ 2:0] block_mem_wa_save;
reg [15:0] block_mem[0:7]; reg [15:0] block_mem_ram[0:7];
wire [15:0] block_mem_o=block_mem[block_mem_ra[2:0]]; wire [15:0] block_mem_o=block_mem_ram[block_mem_ra[2:0]];
assign dc[8:0] = block_mem_o[8:0]; assign dc[8:0] = block_mem_o[8:0];
assign ctype = block_mem_o[9]; assign ctype = block_mem_o[9];
...@@ -125,7 +125,7 @@ module quantizer393( ...@@ -125,7 +125,7 @@ module quantizer393(
assign dcc_stb = start[2]; assign dcc_stb = start[2];
always @ (posedge clk) begin always @ (posedge clk) begin
if (stb) block_mem[block_mem_wa[2:0]] <= {coring_num[2:0],tsi[2:0], ctypei, dci[8:0]}; if (stb) block_mem_ram[block_mem_wa[2:0]] <= {coring_num[2:0],tsi[2:0], ctypei, dci[8:0]};
if (!en) block_mem_wa[2:0] <= 3'h0; if (!en) block_mem_wa[2:0] <= 3'h0;
else if (stb) block_mem_wa[2:0] <= block_mem_wa[2:0] +1; else if (stb) block_mem_wa[2:0] <= block_mem_wa[2:0] +1;
......
logger/imu_exttime393.v
View file @ baa32a59
...@@ -71,7 +71,7 @@ module imu_exttime393( ...@@ -71,7 +71,7 @@ module imu_exttime393(
wire [1:0] chn_enc_w; wire [1:0] chn_enc_w;
reg [15:0] ts_ram [0:3]; // inner timestamp x16 memory that receives timestamp from one of the 4 input channel fifos reg [15:0] ts_ram [0:3]; // inner timestamp x16 memory that receives timestamp from one of the 4 input channel fifos
wire [7:0] dout_chn[0:3]; wire [31:0] dout_chn;
wire [7:0] copy_data; // data from the selected input fifos wire [7:0] copy_data; // data from the selected input fifos
reg [7:0] copy_data_r; // low byte of the timestamp data being copied from one of the input fifos to the ts_ram reg [7:0] copy_data_r; // low byte of the timestamp data being copied from one of the input fifos to the ts_ram
...@@ -83,7 +83,7 @@ module imu_exttime393( ...@@ -83,7 +83,7 @@ module imu_exttime393(
chn_pri_w[3] | chn_pri_w[1]}; chn_pri_w[3] | chn_pri_w[1]};
assign pre_copy_w = (|in_full) && !copy_selected[0] && !ts_full; assign pre_copy_w = (|in_full) && !copy_selected[0] && !ts_full;
assign copy_data = dout_chn[sel_chn]; // 4:1 mux assign copy_data = dout_chn[sel_chn * 8 +: 8]; // 4:1 mux
// acquire external timestamps @ mclk // acquire external timestamps @ mclk
...@@ -136,7 +136,7 @@ module imu_exttime393( ...@@ -136,7 +136,7 @@ module imu_exttime393(
.advance (ts_stb[0]), // enough time .advance (ts_stb[0]), // enough time
.rclk (mclk), // input .rclk (mclk), // input
.rstb (pre_copy_started && (sel_chn == 2'h0)),// input .rstb (pre_copy_started && (sel_chn == 2'h0)),// input
.dout (dout_chn[0]) // output[7:0] reg valid with copy_selected[1] .dout (dout_chn[0 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
); );
timestamp_fifo timestamp_fifo_chn1_i ( timestamp_fifo timestamp_fifo_chn1_i (
...@@ -148,7 +148,7 @@ module imu_exttime393( ...@@ -148,7 +148,7 @@ module imu_exttime393(
.advance (ts_stb[1]), // enough time .advance (ts_stb[1]), // enough time
.rclk (mclk), // input .rclk (mclk), // input
.rstb (pre_copy_started && (sel_chn == 2'h1)),// input .rstb (pre_copy_started && (sel_chn == 2'h1)),// input
.dout (dout_chn[1]) // output[7:0] reg valid with copy_selected[1] .dout (dout_chn[1 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
); );
timestamp_fifo timestamp_fifo_chn2_i ( timestamp_fifo timestamp_fifo_chn2_i (
...@@ -160,7 +160,7 @@ module imu_exttime393( ...@@ -160,7 +160,7 @@ module imu_exttime393(
.advance (ts_stb[2]), // enough time .advance (ts_stb[2]), // enough time
.rclk (mclk), // input .rclk (mclk), // input
.rstb (pre_copy_started && (sel_chn == 2'h2)),// input .rstb (pre_copy_started && (sel_chn == 2'h2)),// input
.dout (dout_chn[2]) // output[7:0] reg valid with copy_selected[1] .dout (dout_chn[2 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
); );
timestamp_fifo timestamp_fifo_chn3_i ( timestamp_fifo timestamp_fifo_chn3_i (
...@@ -172,7 +172,7 @@ module imu_exttime393( ...@@ -172,7 +172,7 @@ module imu_exttime393(
.advance (ts_stb[3]), // enough time .advance (ts_stb[3]), // enough time
.rclk (mclk), // input .rclk (mclk), // input
.rstb (pre_copy_started && (sel_chn == 2'h3)),// input .rstb (pre_copy_started && (sel_chn == 2'h3)),// input
.dout (dout_chn[3]) // output[7:0] reg valid with copy_selected[1] .dout (dout_chn[3 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
); );
......
sensor/sensors393.v
View file @ baa32a59
This diff is collapsed.
timing/timing393.v
View file @ baa32a59
This diff is collapsed.
util_modules/cmd_frame_sequencer.v
View file @ baa32a59
...@@ -92,9 +92,9 @@ module cmd_frame_sequencer#( ...@@ -92,9 +92,9 @@ module cmd_frame_sequencer#(
reg we_fifo_wp; // enable writing to fifo write pointer memory reg we_fifo_wp; // enable writing to fifo write pointer memory
reg next_frame_rq; // request to switch to the new frame page, clear pointer for the one just left reg next_frame_rq; // request to switch to the new frame page, clear pointer for the one just left
wire pre_wpage_inc; wire pre_wpage_inc;
reg [PNTR_WIDH-1:0] fifo_wr_pointers [0:7]; reg [PNTR_WIDH-1:0] fifo_wr_pointers_ram [0:7];
wire [PNTR_WIDH-1:0] fifo_wr_pointers_outw=fifo_wr_pointers[wpage_w]; wire [PNTR_WIDH-1:0] fifo_wr_pointers_outw=fifo_wr_pointers_ram[wpage_w];
wire [PNTR_WIDH-1:0] fifo_wr_pointers_outr=fifo_wr_pointers[page_r]; wire [PNTR_WIDH-1:0] fifo_wr_pointers_outr=fifo_wr_pointers_ram[page_r];
reg [PNTR_WIDH-1:0] fifo_wr_pointers_outw_r; reg [PNTR_WIDH-1:0] fifo_wr_pointers_outw_r;
reg [PNTR_WIDH-1:0] fifo_wr_pointers_outr_r; reg [PNTR_WIDH-1:0] fifo_wr_pointers_outr_r;
...@@ -205,7 +205,7 @@ module cmd_frame_sequencer#( ...@@ -205,7 +205,7 @@ module cmd_frame_sequencer#(
if (cmd_we_any_r[1]) fifo_wr_pointers_outw_r <= fifo_wr_pointers_outw; // register pointer RAM output (write port) if (cmd_we_any_r[1]) fifo_wr_pointers_outw_r <= fifo_wr_pointers_outw; // register pointer RAM output (write port)
// write to pointer RAM (to the same address as just read from if read) // write to pointer RAM (to the same address as just read from if read)
if (we_fifo_wp) fifo_wr_pointers[wpage_w] <= wpage_inc[1] ? {PNTR_WIDH{1'b0}}:(fifo_wr_pointers_outw_r + 1); if (we_fifo_wp) fifo_wr_pointers_ram[wpage_w] <= wpage_inc[1] ? {PNTR_WIDH{1'b0}}:(fifo_wr_pointers_outw_r + 1);
if (cmd_we_any_r[1]) seq_cmd_wa <= {wpage_w, fifo_wr_pointers_outw}; if (cmd_we_any_r[1]) seq_cmd_wa <= {wpage_w, fifo_wr_pointers_outw};
......
util_modules/cmd_seq_mux.v
View file @ baa32a59
...@@ -52,21 +52,23 @@ module cmd_seq_mux#( ...@@ -52,21 +52,23 @@ module cmd_seq_mux#(
output reg [31:0] wdata_out, // write data, valid with waddr_out and wr_en_out output reg [31:0] wdata_out, // write data, valid with waddr_out and wr_en_out
input ackn_out // command sequencer address/data accepted input ackn_out // command sequencer address/data accepted
); );
wire [3:0] wr_en = {wr_en3 & ~ackn3, wr_en2 & ~ackn2, wr_en1 & ~ackn1, wr_en0 & ~ackn0}; wire [3:0] wr_en = {wr_en3 & ~ackn3, wr_en2 & ~ackn2, wr_en1 & ~ackn1, wr_en0 & ~ackn0};
wire [3:0] pri_one_rr[0:3]; // round robin priority wire [15:0] pri_one_rr; // round robin priority
wire [3:0] pri_one; wire [3:0] pri_one;
reg [1:0] chn_r; // last served channel reg [1:0] chn_r; // last served channel
wire rq_any; wire rq_any;
wire [1:0] pri_enc_w; wire [1:0] pri_enc_w;
reg full_r; reg full_r;
wire ackn_w; //pre-acknowledge of one of the channels wire ackn_w; //pre-acknowledge of one of the channels
reg [3:0] ackn_r; reg [3:0] ackn_r;
assign pri_one_rr[0]={wr_en[3] & ~(|wr_en[2:1]), wr_en[2] & ~wr_en[1], wr_en[1], wr_en[0] & ~(|wr_en[3:1])}; assign pri_one_rr = {wr_en[3] & ~(|wr_en[2:0]), wr_en[2]&~(|wr_en[1:0]), wr_en[1] & wr_en[0], wr_en[0],
assign pri_one_rr[1]={wr_en[3] & ~ wr_en[2], wr_en[2], wr_en[1] & ~(|wr_en[3:2]) & wr_en[0], wr_en[0] & ~(|wr_en[3:2])}; wr_en[3], wr_en[2]&~(|wr_en[1:0])&wr_en[3], wr_en[1] & ~ wr_en[3] & wr_en[0], wr_en[0] & ~ wr_en[3],
assign pri_one_rr[2]={wr_en[3], wr_en[2]&~(|wr_en[1:0])&wr_en[3], wr_en[1] & ~ wr_en[3] & wr_en[0], wr_en[0] & ~ wr_en[3] }; wr_en[3] & ~ wr_en[2], wr_en[2], wr_en[1] & ~(|wr_en[3:2]) & wr_en[0], wr_en[0] & ~(|wr_en[3:2]),
assign pri_one_rr[3]={wr_en[3] & ~(|wr_en[2:0]), wr_en[2]&~(|wr_en[1:0]), wr_en[1] & wr_en[0], wr_en[0] }; wr_en[3] & ~(|wr_en[2:1]), wr_en[2] & ~wr_en[1], wr_en[1], wr_en[0] & ~(|wr_en[3:1])};
assign pri_one = pri_one_rr[chn_r];
assign pri_one = pri_one_rr[chn_r * 4 +: 4];
assign rq_any= |wr_en; assign rq_any= |wr_en;
assign pri_enc_w ={pri_one[3] | pri_one[2], assign pri_enc_w ={pri_one[3] | pri_one[2],
pri_one[3] | pri_one[1]}; pri_one[3] | pri_one[1]};
......
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