replaced non-memory 2-d arrays with 1-d ones, added _ram suffix to all memories (baa32a59) · Commits · Elphel / x393

axi/cmprs_afi_mux.v

+42 −43

Original line number	Diff line number	Diff line
		@@ -141,12 +141,12 @@ module cmprs_afi_mux#(

		// reg [2:0] cur_chn; // 'b0xx - none, 'b1 - - channel number (should match fifo_ren*)
		reg [1:0] cur_chn; // 'b0xx - none, 'b1 - - channel number (should match fifo_ren*)
		reg [7:0] left_to_eof[0:3]; // number of chunks left to end of frame
		reg [31:0] left_to_eof; // number of chunks left to end of frame
		reg [3:0] fifo_flush_d; // fifo_flush* delayed by 1 clk (to detect rising edge
		reg [3:0] eof_stb; // single-cycle pulse after fifo_flush is asserted
		// reg [1:0] w64_cnt; // count 64-bit words in a chunk
		reg [8:0] counts_corr0[0:3]; // registers to hold corrected (decremented currently processed ones if any) fifo count values, MSB - needs flush
		reg [8:0] counts_corr1[0:1]; // first arbitration level winning values
		reg [35:0] counts_corr0; // registers to hold corrected (decremented currently processed ones if any) fifo count values, MSB - needs flush
		reg [17:0] counts_corr1; // first arbitration level winning values
		reg [8:0] counts_corr2; // second arbitration level winning values

		reg [1:0] winner1; // 2 first level arbitration winners
		@@ -201,10 +201,10 @@ module cmprs_afi_mux#(

		// use last_chunk_w to apply a special id to waddr and wdata and watch for it during readout
		// compose ID of channel number, frame bumber LSBs and last/not last chunk
		assign last_chunk_w[3:0] = {(left_to_eof[3]==1)?1'b1:1'b0,
		(left_to_eof[2]==1)?1'b1:1'b0,
		(left_to_eof[1]==1)?1'b1:1'b0,
		(left_to_eof[0]==1)?1'b1:1'b0};
		assign last_chunk_w[3:0] = {(left_to_eof[3 * 8 +: 8]==1),
		(left_to_eof[2 * 8 +: 8]==1),
		(left_to_eof[1 * 8 +: 8]==1),
		(left_to_eof[0 * 8 +: 8]==1)};

		assign pre_busy_w = !busy[0] && ready_to_start && need_to_bother && !ptr_resetting;
		assign done_burst_w = busy[0] && !(\|wleft[3:1]); // when wleft[3:0] == 0, busy is 0
		@@ -262,60 +262,60 @@ module cmprs_afi_mux#(

		// TODO: change &w64_cnt[1:0] so left_to_eof[*] will be updated earlier and valid at pre_busy_w
		// Done, updating at the first (not last) word of 4
		if (eof_stb[0]) left_to_eof[0] <= fifo_count0 - (fifo_ren0 & (&wleft[1:0]));
		else if (fifo_ren0 & (&wleft[1:0])) left_to_eof[0] <= left_to_eof[0] - 1;
		if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0 - (fifo_ren0 & (&wleft[1:0]));
		else if (fifo_ren0 & (&wleft[1:0])) left_to_eof[0 * 8 +: 8] <= left_to_eof[0 * 8 +: 8] - 1;

		if (eof_stb[1]) left_to_eof[1] <= fifo_count1 - (fifo_ren1 & (&wleft[1:0]));
		else if (fifo_ren1 & (&wleft[1:0])) left_to_eof[1] <= left_to_eof[1] - 1;
		if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1 - (fifo_ren1 & (&wleft[1:0]));
		else if (fifo_ren1 & (&wleft[1:0])) left_to_eof[1 * 8 +: 8] <= left_to_eof[1 * 8 +: 8] - 1;

		if (eof_stb[2]) left_to_eof[2] <= fifo_count2 - (fifo_ren2 & (&wleft[1:0]));
		else if (fifo_ren2 & (&wleft[1:0])) left_to_eof[2] <= left_to_eof[2] - 1;
		if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2 - (fifo_ren2 & (&wleft[1:0]));
		else if (fifo_ren2 & (&wleft[1:0])) left_to_eof[2 * 8 +: 8] <= left_to_eof[2 * 8 +: 8] - 1;

		if (eof_stb[3]) left_to_eof[3] <= fifo_count3 - (fifo_ren3 & (&wleft[1:0]));
		else if (fifo_ren3 & (&wleft[1:0])) left_to_eof[3] <= left_to_eof[3] - 1;
		if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3 - (fifo_ren3 & (&wleft[1:0]));
		else if (fifo_ren3 & (&wleft[1:0])) left_to_eof[3 * 8 +: 8] <= left_to_eof[3 * 8 +: 8] - 1;

		// Calculate corrected values decrementing currently served channel (if any) values by 1 (latency 1 clk)

		if ((fifo_count0 == 0) \|\| !en_chn[0]) counts_corr0[0] <= 0;
		else if (fifo_ren[0]) counts_corr0[0] <= (fifo_count0_m1 == 0)? 0 : {fifo_flush0,fifo_count0_m1};
		else counts_corr0[0] <= {fifo_flush0,fifo_count0};
		if ((fifo_count0 == 0) \|\| !en_chn[0]) counts_corr0[0 * 9 +: 9] <= 0;
		else if (fifo_ren[0]) counts_corr0[0 * 9 +: 9] <= (fifo_count0_m1 == 0)? 0 : {fifo_flush0,fifo_count0_m1};
		else counts_corr0[0 * 9 +: 9] <= {fifo_flush0,fifo_count0};

		if ((fifo_count1 == 0) \|\| !en_chn[1]) counts_corr0[1] <= 0;
		else if (fifo_ren[1]) counts_corr0[1] <= (fifo_count1_m1 == 0)? 0 : {fifo_flush1,fifo_count1_m1};
		else counts_corr0[1] <= {fifo_flush1,fifo_count1};
		if ((fifo_count1 == 0) \|\| !en_chn[1]) counts_corr0[1 * 9 +: 9] <= 0;
		else if (fifo_ren[1]) counts_corr0[1 * 9 +: 9] <= (fifo_count1_m1 == 0)? 0 : {fifo_flush1,fifo_count1_m1};
		else counts_corr0[1 * 9 +: 9] <= {fifo_flush1,fifo_count1};

		if ((fifo_count2 == 0) \|\| !en_chn[2]) counts_corr0[2] <= 0;
		else if (fifo_ren[2]) counts_corr0[2] <= (fifo_count2_m1 == 0)? 0 : {fifo_flush2,fifo_count2_m1};
		else counts_corr0[2] <= {fifo_flush2,fifo_count2};
		if ((fifo_count2 == 0) \|\| !en_chn[2]) counts_corr0[2 * 9 +: 9] <= 0;
		else if (fifo_ren[2]) counts_corr0[2 * 9 +: 9] <= (fifo_count2_m1 == 0)? 0 : {fifo_flush2,fifo_count2_m1};
		else counts_corr0[2 * 9 +: 9] <= {fifo_flush2,fifo_count2};

		if ((fifo_count3 == 0) \|\| !en_chn[3]) counts_corr0[3] <= 0;
		else if (fifo_ren[3]) counts_corr0[3] <= (fifo_count3_m1 == 0)? 0 : {fifo_flush3,fifo_count3_m1};
		else counts_corr0[3] <= {fifo_flush3,fifo_count3};
		if ((fifo_count3 == 0) \|\| !en_chn[3]) counts_corr0[3 * 9 +: 9] <= 0;
		else if (fifo_ren[3]) counts_corr0[3 * 9 +: 9] <= (fifo_count3_m1 == 0)? 0 : {fifo_flush3,fifo_count3_m1};
		else counts_corr0[3 * 9 +: 9] <= {fifo_flush3,fifo_count3};

		// 2-level arbitration
		// first arbitration level (latency 2 clk)
		if (counts_corr0[1] > counts_corr0[0]) begin
		counts_corr1[0] <= counts_corr0[1];
		if (counts_corr0[1 * 9 +: 9] > counts_corr0[0 * 9 +: 9]) begin
		counts_corr1[0 * 9 +: 9] <= counts_corr0[1 * 9 +: 9];
		winner1[0] <= 1;
		end else begin
		counts_corr1[0] <= counts_corr0[0];
		counts_corr1[0 * 9 +: 9] <= counts_corr0[0 * 9 +: 9];
		winner1[0] <= 0;
		end

		if (counts_corr0[3] > counts_corr0[2]) begin
		counts_corr1[1] <= counts_corr0[3];
		if (counts_corr0[3 * 9 +: 9] > counts_corr0[2 * 9 +: 9]) begin
		counts_corr1[1 * 9 +: 9] <= counts_corr0[3 * 9 +: 9];
		winner1[1] <= 1;
		end else begin
		counts_corr1[1] <= counts_corr0[2];
		counts_corr1[1 * 9 +: 9] <= counts_corr0[2 * 9 +: 9];
		winner1[1] <= 0;
		end

		// second arbitration level (latency 3 clk)
		if (counts_corr1[1] > counts_corr1[0]) begin
		counts_corr2 <= counts_corr1[1];
		if (counts_corr1[1 * 9 +: 9] > counts_corr1[0 * 9 +: 9]) begin
		counts_corr2 <= counts_corr1[1 * 9 +: 9];
		winner2 <= {1'b1,winner1[1]};
		end else begin
		counts_corr2 <= counts_corr1[0];
		counts_corr2 <= counts_corr1[0 * 9 +: 9];
		winner2 <= {1'b0,winner1[0]};
		end
		//ready_to_start need_to_bother
		@@ -325,7 +325,7 @@ module cmprs_afi_mux#(
		else if (done_burst_w) busy <= 0; // {busy[2:0],1'b0};

		if (!en) wleft <= 0;
		else if (pre_busy_w) wleft <= {(\|counts_corr2[7:2])? 2'b11 : left_to_eof[winner2][1:0], 2'b11};
		else if (pre_busy_w) wleft <= {(\|counts_corr2[7:2])? 2'b11 : left_to_eof[winner2 * 8 +: 8][1:0], 2'b11};
		else if (wleft != 0) wleft <= wleft - 1;


		@@ -354,7 +354,7 @@ module cmprs_afi_mux#(

		if (pre_busy_w) chunk_inc <= (\|counts_corr2[7:2])?
		3'h4 :
		({1'b0,left_to_eof[winner2][1:0]} + 3'h1);
		({1'b0,left_to_eof[winner2 * 8 +: 8][1:0]} + 3'h1);

		end

		@@ -395,8 +395,7 @@ module cmprs_afi_mux#(
		.we (cmd_we) // output
		);


		wire [26:0] chunk_ptr_rd01[0:1];
		wire [53:0] chunk_ptr_rd01; // [0:1];

		cmprs_afi_mux_ptr cmprs_afi_mux_ptr_i (
		.hclk (hclk), // input
		@@ -414,9 +413,9 @@ module cmprs_afi_mux#(
		.ptr_resetting (ptr_resetting), // output
		.chunk_addr (chunk_addr), // output[26:0] reg
		.chunk_ptr_ra (chunk_ptr_ra[2:0]), // input[2:0]
		.chunk_ptr_rd (chunk_ptr_rd01[0]) // output[26:0]
		.chunk_ptr_rd (chunk_ptr_rd01[0 * 27 +: 27]) // output[26:0]
		);
		assign chunk_ptr_rd=chunk_ptr_ra[3]?chunk_ptr_rd01[1]:chunk_ptr_rd01[0];
		assign chunk_ptr_rd=chunk_ptr_ra[3]?chunk_ptr_rd01[1 * 27 +: 27]:chunk_ptr_rd01[0 * 27 +: 27];
		cmprs_afi_mux_ptr_wresp cmprs_afi_mux_ptr_wresp_i (
		.hclk (hclk), // input
		.length_di (sa_len_d[26:0]), // input[26:0]
		@@ -425,7 +424,7 @@ module cmprs_afi_mux#(
		.en (en), // input
		.reset_pointers (reset_pointers), // input[3:0]
		.chunk_ptr_ra (chunk_ptr_ra[2:0]), // input[2:0]
		.chunk_ptr_rd (chunk_ptr_rd01[1]), // output[26:0]
		.chunk_ptr_rd (chunk_ptr_rd01[1* 27 +: 27]), // output[26:0]
		.eof_written ({eof_written3,eof_written2,eof_written1,eof_written0}), // output[3:0] reg
		.afi_bvalid (afi_bvalid), // input
		.afi_bready (afi_bready), // output

axi/cmprs_afi_mux_status.v

+58 −59

Original line number	Diff line number	Diff line
		@@ -49,20 +49,19 @@ module cmprs_afi_mux_status #(
		reg [15:0] mode_data_mclk; // some bits unused
		wire mode_we_hclk;
		reg [7:0] mode_hclk;
		// wire [1:0] sel[0:3]={mode_hclk[7:6],mode_hclk[5:4],mode_hclk[3:2],mode_hclk[1:0]};

		reg [1:0] index;
		reg [CMPRS_AFIMUX_CYCBITS-1:0] cntr;
		reg [CMPRS_AFIMUX_WIDTH-1:0] chunk_ptr_hclk; // pointer data
		reg [1:0] chunk_chn_hclk; // pointer channel

		reg [CMPRS_AFIMUX_WIDTH-1:0] status_data[0:3];
		reg [4 * CMPRS_AFIMUX_WIDTH-1:0] status_data;

		wire stb_w;
		reg stb_r;
		wire stb_mclk;

		wire [7:0] ad[0:3];
		wire [31:0] ad;
		wire [3:0] rq;
		wire [3:0] start;

		@@ -78,7 +77,7 @@ module cmprs_afi_mux_status #(
		if (mode_data_mclk[10]) mode_hclk[5:4] <= mode_data_mclk[ 9: 8];
		if (mode_data_mclk[14]) mode_hclk[7:6] <= mode_data_mclk[13:12];

		if (stb_mclk) status_data[chunk_chn_hclk] <= chunk_ptr_hclk;
		if (stb_mclk) status_data[chunk_chn_hclk * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH] <= chunk_ptr_hclk;
		end

		if (!en) {index,cntr} <= 0;
		@@ -106,17 +105,17 @@ module cmprs_afi_mux_status #(
		status_router4 status_router4_i (
		.rst (rst), // input
		.clk (mclk), // input
		.db_in0 (ad[0]), // input[7:0]
		.db_in0 (ad[0 * 8 +: 8]), // input[7:0]
		.rq_in0 (rq[0]), // input
		.start_in0 (start[0]), // output

		.db_in1 (ad[1]), // input[7:0]
		.db_in1 (ad[1 * 8 +: 8]), // input[7:0]
		.rq_in1 (rq[1]), // input
		.start_in1 (start[1]), // output
		.db_in2 (ad[2]), // input[7:0]
		.db_in2 (ad[2 * 8 +: 8]), // input[7:0]
		.rq_in2 (rq[2]), // input
		.start_in2 (start[2]), // output
		.db_in3 (ad[3]), // input[7:0]
		.db_in3 (ad[3 * 8 +: 8]), // input[7:0]
		.rq_in3 (rq[3]), // input
		.start_in3 (start[3]), // output
		.db_out (status_ad), // output[7:0]
		@@ -132,8 +131,8 @@ module cmprs_afi_mux_status #(
		.clk (mclk), // input
		.we (status_we && (cmd_a==0)), // input
		.wd (cmd_data[7:0]), // input[7:0]
		.status (status_data[0]), // input[25:0]
		.ad (ad[0]), // output[7:0]
		.status (status_data[0 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
		.ad (ad[0 * 8 +: 8]), // output[7:0]
		.rq (rq[0]), // output
		.start (start[0]) // input
		);
		@@ -146,8 +145,8 @@ module cmprs_afi_mux_status #(
		.clk (mclk), // input
		.we (status_we && (cmd_a==1)), // input
		.wd (cmd_data[7:0]), // input[7:0]
		.status (status_data[1]), // input[25:0]
		.ad (ad[1]), // output[7:0]
		.status (status_data[1 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
		.ad (ad[1 * 8 +: 8]), // output[7:0]
		.rq (rq[1]), // output
		.start (start[1]) // input
		);
		@@ -160,8 +159,8 @@ module cmprs_afi_mux_status #(
		.clk (mclk), // input
		.we (status_we && (cmd_a==2)), // input
		.wd (cmd_data[7:0]), // input[7:0]
		.status (status_data[2]), // input[25:0]
		.ad (ad[2]), // output[7:0]
		.status (status_data[2 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
		.ad (ad[2 * 8 +: 8]), // output[7:0]
		.rq (rq[2]), // output
		.start (start[2]) // input
		);
		@@ -174,8 +173,8 @@ module cmprs_afi_mux_status #(
		.clk (mclk), // input
		.we (status_we && (cmd_a==3)), // input
		.wd (cmd_data[7:0]), // input[7:0]
		.status (status_data[3]), // input[25:0]
		.ad (ad[3]), // output[7:0]
		.status (status_data[3 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
		.ad (ad[3 * 8 +: 8]), // output[7:0]
		.rq (rq[3]), // output
		.start (start[3]) // input
		);

axi/histogram_saxi.v

+4 −4

Original line number	Diff line number	Diff line
		@@ -103,7 +103,7 @@ module histogram_saxi#(


		);

		localparam ATTRIB_WIDTH = NUM_FRAME_BITS + 4 +2;
		reg [HIST_SAXI_MODE_WIDTH-1:0] mode;
		wire en = mode[HIST_SAXI_EN] & mode[HIST_SAXI_NRESET];
		reg [3:0] awcache_mode;
		@@ -123,7 +123,7 @@ module histogram_saxi#(
		reg [1:0] mux_sel;
		wire start_w;
		reg started;
		reg [NUM_FRAME_BITS + 4 +2 -1:0] attrib [0:3]; // to hold frame number, sensor number and burst (color) for the histograms in the buffer
		reg [ATTRIB_WIDTH -1:0] attrib; // to hold frame number, sensor number and burst (color) for the histograms in the buffer
		wire page_sent_mclk; // page sent over saxi - pulse in mclk domain
		reg [1:0] page_wr; // page number being written
		reg [7:0] page_wa; // 32-bit word address in page being written
		@@ -292,7 +292,7 @@ module histogram_saxi#(

		wr_attr <= en && !dav_r && dav;

		if (wr_attr) attrib[page_wr] <= {enc_rq[1:0], sub_chn_r, frame_r, burst[1:0]};
		if (wr_attr) attrib[page_wr * ATTRIB_WIDTH +: ATTRIB_WIDTH] <= {enc_rq[1:0], sub_chn_r, frame_r, burst[1:0]};

		if (!dav_r) page_wa <= 0;
		else page_wa <= page_wa + 1;
		@@ -322,7 +322,7 @@ module histogram_saxi#(
		if (!en_aclk) block_start_r <= 0;
		else block_start_r <= {block_run[2:0], block_start_w};

		if (block_start_r[0]) attrib_r <= attrib[page_rd];
		if (block_start_r[0]) attrib_r <= attrib[page_rd * ATTRIB_WIDTH +: ATTRIB_WIDTH];

		if (block_start_r[1]) hist_start_page_r <= hist_start_page[attrib_chn];
		if (block_start_r[2]) hist_start_addr[31:12] <= hist_start_page_r + attrib_frame;

axi/mult_saxi_wr.v

+16 −18

Original line number	Diff line number	Diff line
		@@ -103,6 +103,7 @@ module mult_saxi_wr #(

		// localparam BURSTS_CAP0= (MULT_SAXI_HALF_BRAM ? 'h400 : 'h800 ) / MULT_SAXI_BURST0 / 4;
		localparam BRAM_A_WDTH = MULT_SAXI_HALF_BRAM?9:10;
		localparam CHN_A_WDTH = BRAM_A_WDTH - 2;

		wire [3:0] en_chn_mclk;
		wire [3:0] run_chn_mclk;
		@@ -112,16 +113,16 @@ module mult_saxi_wr #(
		wire en_aclk= \|en_chn_aclk; // at least one channel enabled
		wire [3:0] rq_wr;
		wire [3:0] grant_wr;
		wire [BRAM_A_WDTH-3:0] wa_chn[0:3];
		wire [4 * CHN_A_WDTH - 1:0] wa_chn;
		wire [3:0] adv_wr_done; // outputs grant_wr for short bursts, or several clocks before end of wr
		wire [3:0] rq_out_chn;
		wire [BRAM_A_WDTH-3:0] ra_chn[0:3];
		wire [4 * CHN_A_WDTH - 1:0] ra_chn;
		wire [3:0] pre_re;

		reg en_we_arb; // @mclk should be reset by we_grant
		wire we_grant; // @mclk
		wire [1:0] we_cur_chn; // @mclk
		wire [31:0] data_in[0:3];
		wire [127:0] data_in;
		wire [3:0] pre_valid;
		reg [3:0] valid;
		reg [BRAM_A_WDTH-1:0] buf_wa; // multiplexed buffer write adderss
		@@ -152,10 +153,7 @@ module mult_saxi_wr #(
		assign {en_chn3, en_chn2, en_chn1, en_chn0} = en_chn_mclk;

		assign {read_burst3, read_burst2, read_burst1, read_burst0} = grant_wr; // single clock pulse
		assign data_in[0] = data_in_chn0;
		assign data_in[1] = data_in_chn1;
		assign data_in[2] = data_in_chn2;
		assign data_in[3] = data_in_chn3;
		assign data_in = {data_in_chn3, data_in_chn2, data_in_chn1, data_in_chn0};
		assign pre_valid = {pre_valid_chn3, pre_valid_chn2, pre_valid_chn1, pre_valid_chn0};

		assign en_chn_mclk = mode_reg[3:0];
		@@ -182,12 +180,12 @@ module mult_saxi_wr #(
		.valid (valid[0]), // input
		.rq_wr (rq_wr[0]), // output
		.grant_wr (grant_wr[0]), // input
		.wa (wa_chn[0]), // output[7:0]
		.wa (wa_chn[0 * CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
		.adv_wr_done (adv_wr_done[0]), // output
		.rq_out (rq_out_chn[0]), // output reg
		.grant_out (grant_rd[0]), // input
		.fifo_half_full(fifo_half_full), // input
		.ra (ra_chn[0]), // output[7:0]
		.ra (ra_chn[0* CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
		.pre_re (pre_re[0]), // output
		.first_re (first_re[0]), // output reg // 1 clock later than pre_re
		.last_re (last_re[0]), // output reg // 1 clock later than pre_re
		@@ -207,12 +205,12 @@ module mult_saxi_wr #(
		.valid (valid[1]), // input
		.rq_wr (rq_wr[1]), // output
		.grant_wr (grant_wr[1]), // input
		.wa (wa_chn[1]), // output[7:0]
		.wa (wa_chn[1 * CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
		.adv_wr_done (adv_wr_done[1]), // output
		.rq_out (rq_out_chn[1]), // output reg
		.grant_out (grant_rd[1]), // input
		.fifo_half_full(fifo_half_full), // input
		.ra (ra_chn[1]), // output[7:0]
		.ra (ra_chn[1* CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
		.pre_re (pre_re[1]), // output
		.first_re (first_re[1]), // output reg // 1 clock later than pre_re
		.last_re (last_re[1]), // output reg // 1 clock later than pre_re
		@@ -232,12 +230,12 @@ module mult_saxi_wr #(
		.valid (valid[2]), // input
		.rq_wr (rq_wr[2]), // output
		.grant_wr (grant_wr[2]), // input
		.wa (wa_chn[2]), // output[7:0]
		.wa (wa_chn[2 * CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
		.adv_wr_done (adv_wr_done[2]), // output
		.rq_out (rq_out_chn[2]), // output reg
		.grant_out (grant_rd[2]), // input
		.fifo_half_full(fifo_half_full), // input
		.ra (ra_chn[2]), // output[7:0]
		.ra (ra_chn[2* CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
		.pre_re (pre_re[2]), // output
		.first_re (first_re[2]), // output reg // 1 clock later than pre_re
		.last_re (last_re[2]), // output reg // 1 clock later than pre_re
		@@ -257,12 +255,12 @@ module mult_saxi_wr #(
		.valid (valid[3]), // input
		.rq_wr (rq_wr[3]), // output
		.grant_wr (grant_wr[3]), // input
		.wa (wa_chn[3]), // output[7:0]
		.wa (wa_chn[3 * CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
		.adv_wr_done (adv_wr_done[3]), // output
		.rq_out (rq_out_chn[3]), // output reg
		.grant_out (grant_rd[3]), // input
		.fifo_half_full(fifo_half_full), // input
		.ra (ra_chn[3]), // output[7:0]
		.ra (ra_chn[3* CHN_A_WDTH +: CHN_A_WDTH]), // output[7:0]
		.pre_re (pre_re[3]), // output
		.first_re (first_re[3]), // output reg // 1 clock later than pre_re
		.last_re (last_re[3]), // output reg // 1 clock later than pre_re
		@@ -299,8 +297,8 @@ module mult_saxi_wr #(
		if (pre_pre_buf_we && !pre_buf_we) chn_wr <= we_cur_chn; // to re-start arbitration early

		// multiplex address and data
		buf_wa <= {chn_wr, wa_chn[chn_wr]};
		buf_wd <= data_in[chn_wr];
		buf_wa <= {chn_wr, wa_chn[chn_wr * CHN_A_WDTH +: CHN_A_WDTH]};
		buf_wd <= data_in[chn_wr* 32 +: 32];
		// early re-enable arbitration (en_we_arb)
		if (!en_mclk \|\| adv_wr_done[chn_wr]) en_we_arb <= 1;
		else if (we_grant) en_we_arb <= 0;
		@@ -318,7 +316,7 @@ module mult_saxi_wr #(
		always @ (posedge aclk) begin
		en_chn_aclk <=en_chn_mclk;
		chn_rd <= re_cur_chn; // delay by 1 clock (to increase overlap)
		buf_ra <= {chn_rd, ra_chn[chn_rd]};
		buf_ra <= {chn_rd, ra_chn[chn_rd* CHN_A_WDTH +: CHN_A_WDTH]};
		buf_re <= {buf_re[1:0], pre_re[chn_rd]};
		pre_first_rd_valid <= first_re[chn_rd];
		is_last_rd <= {is_last_rd[0], last_re[chn_rd]};

compressor_jp/encoderDCAC393.v

+3 −3

Original line number	Diff line number	Diff line
		@@ -77,8 +77,8 @@ module encoderDCAC393(
		reg [2:0] block_mem_ra;
		reg [2:0] block_mem_wa;
		reg [2:0] block_mem_wa_save;
		reg [6:0] block_mem[0:7];
		wire [6:0] block_mem_o=block_mem[block_mem_ra[2:0]];
		reg [6:0] block_mem_ram[0:7];
		wire [6:0] block_mem_o=block_mem_ram[block_mem_ra[2:0]];

		assign comp_numbero[2:0]= block_mem_o[2:0];
		assign comp_firsto= block_mem_o[3];
		@@ -86,7 +86,7 @@ module encoderDCAC393(
		assign comp_lastinmbo= block_mem_o[5];
		assign lasto= block_mem_o[6];
		always @ (posedge clk) begin
		if (stb) block_mem[block_mem_wa[2:0]] <= {lasti, comp_lastinmbi, comp_colori,comp_firsti,comp_numberi[2:0]};
		if (stb) block_mem_ram[block_mem_wa[2:0]] <= {lasti, comp_lastinmbi, comp_colori,comp_firsti,comp_numberi[2:0]};
		if (!en) block_mem_wa[2:0] <= 3'h0;
		else if (stb) block_mem_wa[2:0] <= block_mem_wa[2:0] +1;

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