debugging histograms (debug code will be removed at next commit)

axi/histogram_saxi.v

@@ -139,7 +139,7 @@ module  histogram_saxi#(
 `endif    
 */
     localparam ATTRIB_WIDTH = NUM_FRAME_BITS + 4 +2;
-    reg  [HIST_SAXI_MODE_WIDTH-1:0]  mode;
+    reg  [HIST_SAXI_MODE_WIDTH-1:0]  mode = 0;
     wire                             en =     mode[HIST_SAXI_EN] & mode[HIST_SAXI_NRESET];
     reg                        [3:0] awcache_mode;
     reg                              confirm_write;
@@ -316,7 +316,7 @@ module  histogram_saxi#(
     
     assign saxi_awaddr = {start_addr_r[31:6],6'b0};
     
-    assign saxi_awvalid = (|start_addr_r[9:6]) || first_burst;    
+    assign saxi_awvalid = ((|start_addr_r[9:6]) || first_burst) && !arst;    
 //{enc_rq[1:0], sub_chn_r, frame_r,  burst[1:0]}
     
     // assign block_end= ???;
@@ -406,8 +406,7 @@ module  histogram_saxi#(
     // Buffer read, SAXI send logic
     always @(posedge aclk) begin
         preen_aclk <= en; 
-        en_aclk <=    preen_aclk && en; 
-
+        en_aclk <=    preen_aclk && en && !arst; 
         prenreset_aclk <= nreset; 
         nreset_aclk <=    prenreset_aclk && nreset; 
 
@@ -440,7 +439,7 @@ module  histogram_saxi#(
         if (arst || block_start_r[3]) start_addr_r[31:6] <= {hist_start_addr[31:10], 4'b0}; 
         else if (saxi_start_burst_w)  start_addr_r[31:6] <= start_addr_r[31:6] + 1;
         
-        if (!nreset_aclk)            first_burst <= 0;
+        if (!nreset_aclk ||  arst)   first_burst <= 0;
         else if (block_start_r[3])   first_burst <= 1; // block_start_r[3] - same as start_addr_r set
         else if (saxi_start_burst_w) first_burst <= 0;
         

cocotb/x393_cocotb_server.py

@@ -141,7 +141,7 @@ class X393_cocotb_server(object):
                                     autoflush =  self.autoflush,
                                     blatency =   5)
         
-        level = logging.DEBUG if debug else logging.WARNING
+        level = logging.DEBUG if debug else logging.INFO # WARNING
         self.dut._log.info('Set debug level '+str(level)+", debug="+str(debug))
         
         self.maxigp0.log.setLevel(level)

cocotb/x393interfaces.py

@@ -172,7 +172,6 @@ class SAXIWrSim(BusDriver):
         @param autoflush flush file after each write
         @param blatency  number of cycles to delay write response (b) channel
         """
-#        self.log.setLevel(logging.DEBUG)
         BusDriver.__init__(self, entity, name, clock)
         self.name = name
         self.log.debug ("SAXIWrSim: name='%s', mempath='%s', memhigh=0x%08x, data_bytes=%d, autoflush=%s, blatency=%d"%
@@ -251,7 +250,7 @@ class SAXIWrSim(BusDriver):
             try:
                 data = self.bus.wr_data.value.integer
             except:
-                self.log.warning ("SAXIWrSim() writing undefined data")
+                self.log.warning ("SAXIWrSim(%s:%d) writing undefined data"%(self.name,self._data_bytes))
                 bv = self.bus.wr_data.value
                 bv.binstr = re.sub("[^1]","0",bv.binstr)
                 data = bv.integer
@@ -270,7 +269,7 @@ class SAXIWrSim(BusDriver):
                        self._memfile.seek(1,1)
             if self.autoflush:
                 self._memfile.flush()
-            self.log.debug ("SAXIWrSim() 0x%x -> 0x%x, mask = 0x%x"%(address,data,bv.integer))
+            self.log.info ("SAXIWrSim(%s:%d) 0x%x <- 0x%x"%(self.name,self._data_bytes,address,data))
             yield RisingEdge(self.clock)
             
             
@@ -301,7 +300,7 @@ class SAXIRdSim(BusDriver):
         @param data_bytes data width, in bytes
         
         """
-#        self.log.setLevel(logging.DEBUG)
+        
         BusDriver.__init__(self, entity, name, clock)
         self.name = name
         self.log.debug ("SAXIRdSim: name='%s', mempath='%s', memhigh=0x%08x, data_bytes=%d"%
@@ -458,7 +457,6 @@ class MAXIGPMaster(BusDriver):
     _channels = [AR_CHN,AW_CHN,R_CHN,W_CHN,B_CHN]
     def __init__(self, entity, name, clock, rdlag=None, blag=None):
         BusDriver.__init__(self, entity, name, clock)
-#        self.log.setLevel(logging.DEBUG)
         self.name = name
         # set read and write back channels simulation lag between AXI sets valid and host responds with
         # ready. If None - drive these signals  

fpga_version.vh

@@ -35,29 +35,36 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-          parameter FPGA_VERSION =          32'h039300ae;      // parallel, increasing sesnsor-channels maximal delays to 12 bits -0.091/25, 79.89%
-//        parameter FPGA_VERSION =          32'h039300ad;      // parallel, resetting frame_pre_run. All met, 79.97%
-//        parameter FPGA_VERSION =          32'h039300ac;      // parallel, adding reset needed_page in compressor -0.012 (2), 79.39%
-//        parameter FPGA_VERSION =          32'h039300ab;      // parallel, more on frame sync in compressor All met, 79.04%
-//        parameter FPGA_VERSION =          32'h039300aa;      // parallel, improving frame sync in compressor -0.036ns, 79.60%
-//        parameter FPGA_VERSION =          32'h039300a9;      // parallel, added copying maste-t-slave frame number -0.169(8 paths), 80.28%
-//        parameter FPGA_VERSION =          32'h039300a8;      // parallel, fixing BUG in command sequencer that was missing some commands 79.25%, all met
-//        parameter FPGA_VERSION =          32'h039300a7;      // parallel, changing parameter to reset buffer pages at each frame start. 79.4%, -0.022 (2 paths)
-//        parameter FPGA_VERSION =          32'h039300a6;      // parallel, adding frame sync delays to mcntrl_linear 79.26, mclk and xclk violated
-//        parameter FPGA_VERSION =          32'h039300a5;      // parallel, fixing command sequencer and ARO 80.21%, -0.068
-//        parameter FPGA_VERSION =          32'h039300a4;      // parallel 79.66, -0.1
-//        parameter FPGA_VERSION =          32'h039300a3;      // hispi, after minor interface changes (separated control bits)80.52% -0.163
-//        parameter FPGA_VERSION =          32'h039300a2;      // hispi trying default placement 81.39% not met by -0.183
-//        parameter FPGA_VERSION =          32'h039300a1;      // hispi 81.19%, not met by -0.07
-//        parameter FPGA_VERSION =          32'h039300a0;      // parallel, re-ran after bug fix, %79.38%, not met -0.072
-//        parameter FPGA_VERSION =          32'h039300a0;    // parallel, else same as 9f 78.91%, not met by -0.032
-//        parameter FPGA_VERSION =          32'h0393009f;    // hispi, adding IRQ status register (placemnt "explore") 81.36%, all met - broken on one channel?
-//        parameter FPGA_VERSION =          32'h0393009e;    // hispi, adding IRQ status register 80.90%, timing failed by -0.218
-//        parameter FPGA_VERSION =          32'h0393009d;    // hispi, adding IRQ from multi_saxi  80.95%, timing not met (-0.034 )
-//        parameter FPGA_VERSION =          32'h0393009c;    // parallel, adding IRQ from multi_saxi  79.31% , timing met (2015.3)
-//        parameter FPGA_VERSION =          32'h0393009b;    // parallel, bug fixed in dct_chen 79.58, timing met (2015.3)
-//        parameter FPGA_VERSION =          32'h0393009a;    // serial, bug fixed in dct_chen 80.94%, timing met (2015.3)
-//        parameter FPGA_VERSION =          32'h03930099;    // parallel, with dct_chen, all met, 79.2%
+        parameter FPGA_VERSION =          32'h039300b4;      //-a parallel, and more - -0.180/33, 80.68 %
+//        parameter FPGA_VERSION =          32'h039300b4;      // parallel, and more -0.094/37, 80.18 %
+//      parameter FPGA_VERSION =          32'h039300b3;      // parallel, and more  -0.052/8, 79.56%
+//      parameter FPGA_VERSION =          32'h039300b2;      // parallel, and more -0.163 /47,  79.93%
+//      parameter FPGA_VERSION =          32'h039300b1;      // parallel, more debug -0.335/86, 79.66%
+//      parameter FPGA_VERSION =          32'h039300b0;      // parallel, more debug -0.047/8, 79.51%
+//      parameter FPGA_VERSION =          32'h039300af;      // parallel, debugging histograms all met, 79.45%
+//      parameter FPGA_VERSION =          32'h039300ae;      // parallel, increasing sesnsor-channels maximal delays to 12 bits -0.091/25, 79.89%
+//      parameter FPGA_VERSION =          32'h039300ad;      // parallel, resetting frame_pre_run. All met, 79.97%
+//      parameter FPGA_VERSION =          32'h039300ac;      // parallel, adding reset needed_page in compressor -0.012 (2), 79.39%
+//      parameter FPGA_VERSION =          32'h039300ab;      // parallel, more on frame sync in compressor All met, 79.04%
+//      parameter FPGA_VERSION =          32'h039300aa;      // parallel, improving frame sync in compressor -0.036ns, 79.60%
+//      parameter FPGA_VERSION =          32'h039300a9;      // parallel, added copying maste-t-slave frame number -0.169(8 paths), 80.28%
+//      parameter FPGA_VERSION =          32'h039300a8;      // parallel, fixing BUG in command sequencer that was missing some commands 79.25%, all met
+//      parameter FPGA_VERSION =          32'h039300a7;      // parallel, changing parameter to reset buffer pages at each frame start. 79.4%, -0.022 (2 paths)
+//      parameter FPGA_VERSION =          32'h039300a6;      // parallel, adding frame sync delays to mcntrl_linear 79.26, mclk and xclk violated
+//      parameter FPGA_VERSION =          32'h039300a5;      // parallel, fixing command sequencer and ARO 80.21%, -0.068
+//      parameter FPGA_VERSION =          32'h039300a4;      // parallel 79.66, -0.1
+//      parameter FPGA_VERSION =          32'h039300a3;      // hispi, after minor interface changes (separated control bits)80.52% -0.163
+//      parameter FPGA_VERSION =          32'h039300a2;      // hispi trying default placement 81.39% not met by -0.183
+//      parameter FPGA_VERSION =          32'h039300a1;      // hispi 81.19%, not met by -0.07
+//      parameter FPGA_VERSION =          32'h039300a0;      // parallel, re-ran after bug fix, %79.38%, not met -0.072
+//      parameter FPGA_VERSION =          32'h039300a0;    // parallel, else same as 9f 78.91%, not met by -0.032
+//      parameter FPGA_VERSION =          32'h0393009f;    // hispi, adding IRQ status register (placemnt "explore") 81.36%, all met - broken on one channel?
+//      parameter FPGA_VERSION =          32'h0393009e;    // hispi, adding IRQ status register 80.90%, timing failed by -0.218
+//      parameter FPGA_VERSION =          32'h0393009d;    // hispi, adding IRQ from multi_saxi  80.95%, timing not met (-0.034 )
+//      parameter FPGA_VERSION =          32'h0393009c;    // parallel, adding IRQ from multi_saxi  79.31% , timing met (2015.3)
+//      parameter FPGA_VERSION =          32'h0393009b;    // parallel, bug fixed in dct_chen 79.58, timing met (2015.3)
+//      parameter FPGA_VERSION =          32'h0393009a;    // serial, bug fixed in dct_chen 80.94%, timing met (2015.3)
+//      parameter FPGA_VERSION =          32'h03930099;    // parallel, with dct_chen, all met, 79.2%
 //      parameter FPGA_VERSION =          32'h03930098;    // serial, trying dct_chen - works, removing old completely, constraints met80.?%
 //      parameter FPGA_VERSION =          32'h03930097;    // serial, trying dct_chen - works
 //      parameter FPGA_VERSION =          32'h03930096;    // serial, next (before changing DCT)

py393/x393_export_c.py

@@ -1962,15 +1962,15 @@ class X393ExportC(object):
 
     def _enc_gamma_ctl(self):
         dw=[]
-        dw.append(("bayer",           0,  2,   0,  "Bayer color shift (pixel to gamma table)"))
-        dw.append(("bayer_set",       2,  1,   0,  "Set 'bayer' field"))
-        dw.append(("page",            3,  1,   0,  "Table page (only available if SENS_GAMMA_BUFFER in Verilog)"))
-        dw.append(("page_set",        4,  1,   0,  "Set 'page' field"))
-        dw.append(("en",              5,  1,   1,  "Enable module"))
-        dw.append(("en_set",          6,  1,   1,  "Set 'en' field"))
-        dw.append(("repet",           7,  1,   1,  "Repetitive (normal) mode. Set 0 for testing of the single-frame mode"))
-        dw.append(("repet_set",       8,  1,   1,  "Set 'repet' field"))
-        dw.append(("trig",            9,  1,   0,  "Single trigger used when repetitive mode is off (self clearing bit)"))
+        dw.append(("bayer",           vrlg.SENS_GAMMA_MODE_BAYER,      2,   0,  "Bayer color shift (pixel to gamma table)"))
+        dw.append(("bayer_set",       vrlg.SENS_GAMMA_MODE_BAYER_SET,  1,   0,  "Set 'bayer' field"))
+        dw.append(("page",            vrlg.SENS_GAMMA_MODE_PAGE,  1,   0,  "Table page (only available if SENS_GAMMA_BUFFER in Verilog)"))
+        dw.append(("page_set",        vrlg.SENS_GAMMA_MODE_PAGE_SET,   1,   0,  "Set 'page' field"))
+        dw.append(("en",              vrlg.SENS_GAMMA_MODE_EN,         1,   1,  "Enable module"))
+        dw.append(("en_set",          vrlg.SENS_GAMMA_MODE_EN_SET,     1,   1,  "Set 'en' field"))
+        dw.append(("repet",           vrlg.SENS_GAMMA_MODE_REPET,      1,   1,  "Repetitive (normal) mode. Set 0 for testing of the single-frame mode"))
+        dw.append(("repet_set",       vrlg.SENS_GAMMA_MODE_REPET_SET,  1,   1,  "Set 'repet' field"))
+        dw.append(("trig",            vrlg.SENS_GAMMA_MODE_TRIG,       1,   0,  "Single trigger used when repetitive mode is off (self clearing bit)"))
         return dw
 
     def _enc_gamma_tbl_addr(self):

py393/x393_jpeg.py

@@ -1055,6 +1055,31 @@ set_rtc # maybe not needed as it can be set differently
 camsync_setup 0xf # sensor mask - use local timestamps)
 jpeg_write  "img.jpeg" 0 80
 
+####### Parallel - setup sensor 1 (sensor 0 is set by drivers) ##############
+setup_all_sensors True None 0x2 # sensor 1
+set_sensor_io_ctl  1 None None 1 # Set ARO low - check if it is still needed?
+#set quadrants
+set_sensor_io_ctl 1 None None None None None 0 0xe
+compressor_control  1  None  None  None None None  3 #bayer
+#Get rid of the corrupted last pixel column
+#longer line (default 0xa1f)
+write_sensor_i2c  1 1 0 0x90040a23
+#increase scanline write (memory controller) width in 16-bursts (was 0xa2)
+axi_write_single_w 0x696 0x079800a3
+#Gamma 0.57
+program_gamma 1 0 0.57 0.04
+#colors - outdoor
+write_sensor_i2c  1 1 0 0x9035000a
+write_sensor_i2c  1 1 0 0x902c000e
+write_sensor_i2c  1 1 0 0x902d000d
+#exposure 0x100 lines (default was 0x797)
+#write_sensor_i2c  1 1 0 0x90090100
+#exposure 0x797 (default)
+#write_sensor_i2c  1 1 0 0x90090797
+#run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
+set_qtables 1l 0 80
+compressor_control 1 3
+jpeg_write  "img.jpeg" 1 80
 
 
 ################## Parallel ##################
@@ -1607,6 +1632,10 @@ write_cmd_frame_sequencer  0  1  4 0x6c6 0x300006 #save more lines than compress
 write_cmd_frame_sequencer  0  1  4  0x6c0  0x7d4b # run compressor memory       (+2)
 write_cmd_frame_sequencer  0  1  4  0x600  0x7    # run compressor              (+0)
 
+#testing histograms
+write_control_register 0x409 0xc0
+
+
 #sequencer test
 #ctrl_cmd_frame_sequencer  <num_sensor>  <reset=False>  <start=False>  <stop=False>
 ctrl_cmd_frame_sequencer   0  0  1  0
@@ -1624,20 +1653,27 @@ write_cmd_frame_sequencer  0  0  2  0x700  0x60
 write_cmd_frame_sequencer  0  0  2  0x700  0x90
 write_cmd_frame_sequencer  0  0  2  0x700  0x600
 write_cmd_frame_sequencer  0  0  2  0x700  0x900
-
-
-
-
-
+r
+read_status 0x21
+r
 #set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
 #set_sensor_io_ctl all None None None None None 1 None # load all delays?
 compressor_control  all  None  None  None None None  2
 compressor_interrupt_control all clr
 compressor_interrupt_control all en
 compressor_control  all  3
+r
+read_status 0x21
+r
 jpeg_sim_multi 4
-jpeg_sim_multi 8
-jpeg_sim_multi 4
+r
+read_status 0x21
+r
+jpeg_sim_multi 3
+r
+read_status 0x21
+r
+
 
 write_cmd_frame_sequencer  0  1  1 0x686 0x240005 # correct lines                                                                                                   
 write_cmd_frame_sequencer  0  1  1 0x6c6 0x200006 # correct lines                                                                                                                                    

py393/x393_sensor.py

@@ -267,7 +267,7 @@ class X393Sensor(object):
         @return: sensor mode control word
         """
         rslt = 0;
-        if (not hist_en is None) and (hist_nrst is None):
+        if (not hist_en is None) and (not hist_nrst is None):
             rslt |= (hist_en & 0xf) <<   vrlg.SENSOR_HIST_EN_BITS
             rslt |= (hist_nrst & 0xf) << vrlg.SENSOR_HIST_NRST_BITS
             rslt |= 1 << vrlg.SENSOR_HIST_BITS_SET;

sensor/sens_histogram_snglclk.v

@@ -39,7 +39,7 @@
  * with at least one of the Free Software programs.
  */
 `timescale 1ns/1ps
-
+`include "system_defines.vh" // just for debugging histograms 
 module  sens_histogram_snglclk #(
     parameter HISTOGRAM_RAM_MODE =     "BUF32", // valid: "NOBUF" (32-bits, no buffering - now is replaced by BUF32), "BUF18", "BUF32"
     parameter HISTOGRAM_ADDR =         'h33c,
@@ -75,7 +75,12 @@ module  sens_histogram_snglclk #(
     ,output                       debug_do, // output to the debug ring
      input                        debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load // SuppressThisWarning VEditor - not used
      input                        debug_di  // input from the debug ring
-`endif         
+`endif
+
+`ifdef DEBUG_HISTOGRAMS
+    ,output [3:0] dbg_hist_data
+`endif
+         
 );
     
     localparam HIST_WIDTH = (HISTOGRAM_RAM_MODE == "BUF18") ? 18 : 32;
@@ -273,6 +278,22 @@ module  sens_histogram_snglclk #(
     reg                     eq_prev;         // pixel equals  previous of the same color
     wire                    eq_prev_d3;      // eq_prev delayed by 3 clocks to select r1 source
 //    wire                    start_hor_woi = hcntr_zero_w && left_margin && vert_woi;
+`ifdef DEBUG_HISTOGRAMS
+    assign dbg_hist_data[3:0] = {frame_active, hist_done, vert_woi, vcntr_zero_w };
+//    assign dbg_hist_data[3:0] = {frame_active, hist_rst_pclk, hist_en_pclk, vcntr_zero_w };
+    reg    [2:0] dbg_toggle=0;
+//    assign dbg_hist_data[3:0] = {dbg_toggle, en_new, en, vcntr_zero_w };
+//    assign dbg_hist_data[3:0] = {dbg_toggle, vcntr_zero_w }; // version b4 (toggles)
+//        hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
+//        if      (hist_rst_pclk)                               en <= 0;
+//        else if (hist_en_pclk)                                en <= 1;
+//    reg           en;
+//    reg           en_new; // @ pclk - enable new frame
+    always @(posedge pclk) begin
+        if (sof) dbg_toggle <= dbg_toggle+1;
+    end
+    
+`endif
         
     
     // hist_di is 2 cycles ahead of hor_woi
@@ -326,7 +347,7 @@ module  sens_histogram_snglclk #(
     reg en_rq_start;
     
     always @ (posedge mclk) begin
-        en_mclk <= en;
+        en_mclk <= en && !hist_rst;
         if      (!en_mclk)       hist_out <= 0;
         else if (hist_done_mclk) hist_out <= 1;
         else if (&hist_raddr)    hist_out <= 0;
@@ -339,7 +360,7 @@ module  sens_histogram_snglclk #(
 // prevent starting rq if grant is still on (back-to-back)
         if      (!hist_out)   en_rq_start <= 0;
         else if (!hist_grant) en_rq_start <= 1;
-        hist_rq_r <= en_mclk && hist_out && !(&hist_raddr) && en_rq_start;
+        hist_rq_r <= !hist_rst & en_mclk && hist_out && !(&hist_raddr) && en_rq_start;
         
         if      (!hist_out || (&hist_raddr[7:0])) hist_re[0] <= 0;
         else if (hist_grant)                      hist_re[0] <= 1;

sensor/sens_parallel12.v

@@ -37,7 +37,7 @@
  * with at least one of the Free Software programs.
  */
 `timescale 1ns/1ps
-
+`include "system_defines.vh" // just for debugging histograms 
 module  sens_parallel12 #(
     parameter SENSIO_ADDR =        'h330,
     parameter SENSIO_ADDR_MASK =   'h7f8,
@@ -144,6 +144,10 @@ module  sens_parallel12 #(
     output  [7:0] status_ad,   // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
     output        status_rq,   // input request to send status downstream
     input         status_start // Acknowledge of the first status packet byte (address)
+`ifdef DEBUG_HISTOGRAMS
+    ,input  [7:0] dbg_hist_data
+`endif
+    
 );
 
     // delaying vact and pxd by one clock cycle to match hact register
@@ -247,7 +251,14 @@ module  sens_parallel12 #(
                      xfpgatdo_byte[7:0],
                      vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm, 
                      clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
-                     ps_rdy, ps_out, xfpgatdo, senspgmin};
+                     ps_rdy,
+`ifdef DEBUG_HISTOGRAMS
+                     dbg_hist_data,
+`else
+                     ps_out,
+`endif
+                     
+                     xfpgatdo, senspgmin};
                         
     assign hact_out = hact_r;
     assign iaro = trigger_mode?  ~trig : iaro_soft;

sensor/sensor_channel.v

@@ -37,6 +37,7 @@
  * with at least one of the Free Software programs.
  */
 `timescale 1ns/1ps
+`include "system_defines.vh" // just for debugging histograms 
 
 module  sensor_channel#(
     // parameters, individual to sensor channels and those likely to be modified
@@ -463,6 +464,25 @@ module  sensor_channel#(
     reg          eof_out_r;       
     wire         prsts;  // @pclk - includes sensor reset and sensor PLL reset
     
+`ifdef DEBUG_HISTOGRAMS
+    wire [7:0] dbg_hist_data;
+    wire [3:0] dbg_hist_data_hist;
+    reg [15:0] dbg_cntr;
+//    reg [1:0] dbg_cntr;  // verion B4 - toggles
+    always @ (posedge pclk) begin
+//        if      (prst) dbg_cntr <= 0;
+//        else
+//         if (sof_out_r) dbg_cntr <=  dbg_cntr + 1;
+          if (hist_gr[0] && hist_rq[0]) dbg_cntr <=  dbg_cntr + 1; // verion B4 - toggles
+    
+    end
+    assign dbg_hist_data = {dbg_cntr[11], hist_en[0], hist_gr[0], hist_rq[0], dbg_hist_data_hist[3:0]};
+//    assign dbg_hist_data = {prst, hist_en[0], dbg_cntr, dbg_hist_data_hist[3:0]}; // verion B4
+//                .hist_en    (hist_en[0]),     // input
+//                .hist_rst   (!hist_nrst[0]),     // input
+    
+`endif        
+    
     // TODO: insert vignetting and/or flat field, pixel defects before gamma_*_in
     assign lens_pxd_in = {pxd[11:0],4'b0};
     assign lens_hact_in = hact;
@@ -576,8 +596,8 @@ module  sensor_channel#(
         else if (sensor_ctrl_we && sensor_ctrl_data[SENSOR_HIST_BITS_SET])  hist_nrst <= sensor_ctrl_data[SENSOR_HIST_NRST_BITS +:4];
         if      (mrst)                                                      en_mclk <=   0;
         else if (sensor_ctrl_we && sensor_ctrl_data[SENSOR_CHN_EN_BIT_SET]) en_mclk <=   sensor_ctrl_data[SENSOR_CHN_EN_BIT];
-        if      (mrst)                                                      bit16 <=   0;
-        else if (sensor_ctrl_we && sensor_ctrl_data[SENSOR_16BIT_BIT_SET])  bit16 <=   sensor_ctrl_data[SENSOR_16BIT_BIT];
+        if      (mrst)                                                      bit16 <=     0;
+        else if (sensor_ctrl_we && sensor_ctrl_data[SENSOR_16BIT_BIT_SET])  bit16 <=     sensor_ctrl_data[SENSOR_16BIT_BIT];
     end
     
     always @ (posedge pclk) begin
@@ -948,6 +968,10 @@ module  sensor_channel#(
             .status_ad            (sens_phys_status_ad),   // output[7:0] 
             .status_rq            (sens_phys_status_rq),   // output
             .status_start         (sens_phys_status_start) // input
+`ifdef DEBUG_HISTOGRAMS
+            , .dbg_hist_data        (dbg_hist_data)
+`endif
+            
         );
 
 // TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
@@ -1179,7 +1203,11 @@ module  sensor_channel#(
                 ,.debug_do    (debug_ring[0]),         // output
                 .debug_sl     (debug_sl),              // input
                 .debug_di     (debug_ring[1])        // input
-    `endif         
+    `endif
+    `ifdef DEBUG_HISTOGRAMS
+    
+    ,.dbg_hist_data(dbg_hist_data_hist[3:0])         
+    `endif
                   
             );
         else

simulation_modules/simul_saxi_gp_wr.v

@@ -268,7 +268,7 @@ fifo_same_clock_fill   #( .DATA_WIDTH(50),.DATA_DEPTH(AW_FIFO_DEPTH)) // read -
         .re           (start_write_burst_w),
         .data_in      ({awid[5:0],     awburst[1:0],    awsize[1:0],    awlen[3:0],    awaddr[31:0],     awqos[3:0]}),
         .data_out     ({awid_out[5:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[31:0], sim_wr_qos[3:0]}),
-        .nempty       (aw_nempty),
+        .nempty       (aw_nempty), // output
         .half_full    (),        // aw_half_full),
         .under        (),        // waddr_under),  // output reg 
         .over         (),        // waddr_over),   // output reg

system_defines.vh

@@ -40,6 +40,7 @@
   // This file may be used to define same pre-processor macros to be included into each parsed file
 `ifndef SYSTEM_DEFINES
   `define SYSTEM_DEFINES
+  `define DEBUG_HISTOGRAMS
   // TODO: Later compare instantiate/infer
   `define INSTANTIATE_DSP48E1 // not yet tesetd/debugged otherwise
 // https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI4-Bursts-4KB-Address-Boundary-Limitation/td-p/216413