Commit b2d85b91 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

debugging histograms (debug code will be removed at next commit)

parent d6b38a63

axi/histogram_saxi.v

+4 −5
Original line number Diff line number Diff line
@@ -139,7 +139,7 @@ module histogram_saxi#( 
`endif    

*/

    localparam ATTRIB_WIDTH = NUM_FRAME_BITS + 4 +2;

    reg  [HIST_SAXI_MODE_WIDTH-1:0]  mode;

    reg  [HIST_SAXI_MODE_WIDTH-1:0]  mode = 0;

    wire                             en =     mode[HIST_SAXI_EN] & mode[HIST_SAXI_NRESET];

    reg                        [3:0] awcache_mode;

    reg                              confirm_write;
@@ -316,7 +316,7 @@ module histogram_saxi#( 
    

    assign saxi_awaddr = {start_addr_r[31:6],6'b0};

    

    assign saxi_awvalid = (|start_addr_r[9:6]) || first_burst;    

    assign saxi_awvalid = ((|start_addr_r[9:6]) || first_burst) && !arst;    

//{enc_rq[1:0], sub_chn_r, frame_r,  burst[1:0]}

    

    // assign block_end= ???;
@@ -406,8 +406,7 @@ module histogram_saxi#( 
    // Buffer read, SAXI send logic

    always @(posedge aclk) begin

        preen_aclk <= en; 

        en_aclk <=    preen_aclk && en; 



        en_aclk <=    preen_aclk && en && !arst; 

        prenreset_aclk <= nreset; 

        nreset_aclk <=    prenreset_aclk && nreset;
@@ -440,7 +439,7 @@ module histogram_saxi#( 
        if (arst || block_start_r[3]) start_addr_r[31:6] <= {hist_start_addr[31:10], 4'b0}; 

        else if (saxi_start_burst_w)  start_addr_r[31:6] <= start_addr_r[31:6] + 1;

        

        if (!nreset_aclk)            first_burst <= 0;

        if (!nreset_aclk ||  arst)   first_burst <= 0;

        else if (block_start_r[3])   first_burst <= 1; // block_start_r[3] - same as start_addr_r set

        else if (saxi_start_burst_w) first_burst <= 0;

cocotb/x393_cocotb_02.sav

+266 −31
Original line number Diff line number Diff line 
[*]

[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI

[*] Wed Sep  7 07:20:21 2016

[*] Thu Sep  8 23:28:43 2016

[*]

[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160906212704383.fst"

[dumpfile_mtime] "Wed Sep  7 07:20:01 2016"

[dumpfile_size] 411501315

[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160908170329425.fst"

[dumpfile_mtime] "Thu Sep  8 23:28:35 2016"

[dumpfile_size] 111373882

[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_02.sav"

[timestart] 0

[size] 1836 1171

[size] 1820 1171

[pos] 1928 23

*-26.595917 254087388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

*-25.450548 115800000 239467388 239402388 239527388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[treeopen] x393_dut.

[treeopen] x393_dut.ddr3_i.ddr3_i.

[treeopen] x393_dut.simul_axi_master_wdata_i.

[treeopen] x393_dut.simul_saxi_gp0_wr_i.

[treeopen] x393_dut.x393_i.

[treeopen] x393_dut.x393_i.cmd_mux_i.

[treeopen] x393_dut.x393_i.compressor393_i.

[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].

[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.

[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.
@@ -36,7 +36,6 @@ 
[treeopen] x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.

[treeopen] x393_dut.x393_i.frame_sequencer_block[0].

[treeopen] x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.

[treeopen] x393_dut.x393_i.mcntrl393_i.

[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.

[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.

[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
@@ -51,16 +50,24 @@ 
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].

[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].

[treeopen] x393_dut.x393_i.sensors393_i.

[treeopen] x393_dut.x393_i.sensors393_i.histogram_saxi_i.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk4.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk6.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk8.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].

[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].

[treeopen] x393_dut.x393_i.timing393_i.

[sst_width] 278

[signals_width] 428

[sst_width] 409

[signals_width] 315

[sst_expanded] 1

[sst_vpaned_height] 641

@820
@@ -537,8 +544,9 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.waddr[8:0] 
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.wpage[1:0]

@1401200

-all_par_hispi

@800200

@c00200

-compressor_0

@800200

-linear

@22

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.mode_reg[14:0]
@@ -732,7 +740,7 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_tiled_rd_compressor_i.fram 
-tile_chn1

@1401200

-other_channels

@800200

@c00200

-tile

@22

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
@@ -747,6 +755,7 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.fram 
@8022

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]

@28

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.cmd_we

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.set_mode_w

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_en

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.repeat_frames
@@ -781,9 +790,7 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.fram 
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_en

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_page_rst_rd

@29

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_page_rst_pos

@28

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.calc_valid

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pre_want

(4)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
@@ -811,7 +818,7 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.num_ 
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.num_rows_m1[5:0]

@28

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.suspend

@1000200

@1401200

-tile

@c00200

-sdram
@@ -867,7 +874,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_ 
-

@1000200

-cmprs_pixel_buffer_ifacde

@800200

@c00200

-cmprs_macroblock

@28

x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.buf_ready_w
@@ -943,7 +950,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macrob 
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.multipulse_cross_clock_i.num_pulses[2:0]

@200

-

@1000200

@1401200

-cmprs_macroblock

@28

x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start
@@ -1159,7 +1166,7 @@ x393_dut.simul_axi_hp1_wr_i.sim_wr_address[31:0] 
x393_dut.simul_axi_hp1_wr_i.sim_wr_data[63:0]

@28

x393_dut.simul_axi_hp1_wr_i.sim_wr_valid

@1000200

@1401200

-compressor_0

@800200

-follow_master
@@ -1481,11 +1488,11 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.buf_pxd[7:0] 
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.buf_pxd[7:0]

@1401200

-compressors_all

@c00200

@800200

-cmdseq_0

@28

x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.frame_sync

@800200

@c00200

-command_write

@c00022

x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.cmdseq_di[63:0]
@@ -1647,9 +1654,9 @@ x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.wpage_inc[1:0] 
x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.cmd_we_ctl_w

@1001200

-group_end

@1000200

@1401200

-command_write

@800200

@c00200

-command_read

@28

x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.seq_enrun
@@ -1685,9 +1692,9 @@ x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.ackn 
x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.mclk

@1001200

-group_end

@1000200

-command_read

@1401200

-command_read

@1000200

-cmdseq_0

@c00200

-cmdseq_mux
@@ -1788,14 +1795,26 @@ x393_dut.x393_i.cmd_mux_i.start_axi_w 
x393_dut.x393_i.cmd_mux_i.start_wburst

@1401200

-cmd_mux

@800200

@c00200

-cmd_mux

@28

x393_dut.x393_i.cmd_mux_i.mclk

@22

x393_dut.x393_i.cmd_mux_i.byte_ad[7:0]

@28

x393_dut.x393_i.cmd_mux_i.ad_stb

@200

-

@1401200

-cmd_mux

@c00200

-readback

@28

x393_dut.x393_i.cmd_readback_i.we

@22

x393_dut.x393_i.cmd_readback_i.waddr[10:0]

x393_dut.x393_i.cmd_readback_i.wdata[31:0]

@1000200

@1401200

-readback

@c00200

-gpio
@@ -2193,7 +2212,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.vsync_late 
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hclk

@1401200

-compressor_channel0

@800200

@c00200

-interrupts

@c00022

x393_dut.irq_r[8:0]
@@ -2229,9 +2248,6 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status 
(11)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]

@1401200

-group_end

@200

-

@1000200

-interrupts

@c00200

-afi0_mux
@@ -2479,9 +2495,228 @@ x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.valid 
@22

x393_dut.x393_i.frame_num[15:0]

x393_dut.x393_i.frame_num_compressed[15:0]

@1000200

-frames

@800200

-histgograms

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_out

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.mclk

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en_mclk

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_rq[3:0]

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_nrst[3:0]

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_chn[1:0]

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_data[31:0]

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_dv[3:0]

@800200

-chn0

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_sof_in

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_sof_out

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_hact_out

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_pxd_out[7:0]

@800200

-sens_histogram_0

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_en_pclk

@29

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_en_pclk

@c00022

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

@28

(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(9)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(10)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(11)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(12)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(13)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(14)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(15)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(16)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(17)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(18)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(19)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(20)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(21)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(22)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(23)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(24)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

(25)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]

@1401200

-group_end

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.dbg_hist_data[7:0]

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.top_margin

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vert_woi

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_xfer_busy

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en_rq_start

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pre_first_line

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.frame_active

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.line_start_w

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vert_woi

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vcntr[15:0]

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vcntr_zero_w

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_even

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_odd

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re_even

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re_odd

@1000200

-sens_histogram_0

-chn0

@800200

-histogram_saxi

@28

x393_dut.x393_i.sensors393_i.histogram_saxi_i.nreset

@22

x393_dut.x393_i.sensors393_i.histogram_saxi_i.frame0[3:0]

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request0

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn0[1:0]

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request1

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn1[1:0]

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request2

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn2[1:0]

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request3

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn3[1:0]

@28

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_grant0

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_dvalid0

@22

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data0[31:0]

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data1[31:0]

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data2[31:0]

x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data3[31:0]

@28

x393_dut.x393_i.sensors393_i.histogram_saxi_i.first_burst

@22

x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]

@28

x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awvalid

x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awready

@22

x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]

@1000200

-histogram_saxi

@800200

-simul_saxi

@28

x393_dut.x393_i.sensors393_i.histogram_saxi_i.arst

x393_dut.x393_i.sensors393_i.histogram_saxi_i.en_aclk

x393_dut.simul_saxi_gp0_wr_i.awvalid

x393_dut.simul_saxi_gp0_wr_i.awready

x393_dut.simul_saxi_gp0_wr_i.sim_wr_ready

@22

x393_dut.simul_saxi_gp0_wr_i.sim_wr_address[31:0]

@c00022

x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

@28

(0)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(1)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(2)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(3)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(4)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(5)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(6)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(7)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(8)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(9)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(10)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(11)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(12)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(13)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(14)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(15)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(16)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(17)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(18)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(19)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(20)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(21)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(22)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(23)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(24)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(25)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(26)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(27)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(28)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(29)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(30)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

(31)x393_dut.simul_saxi_gp0_wr_i.sim_wr_data[31:0]

@1401200

-group_end

@22

x393_dut.simul_saxi_gp0_wr_i.sim_wr_mask[3:0]

@c00022

x393_dut.simul_saxi_gp0_wr_i.sim_wr_stb[3:0]

@28

(0)x393_dut.simul_saxi_gp0_wr_i.sim_wr_stb[3:0]

(1)x393_dut.simul_saxi_gp0_wr_i.sim_wr_stb[3:0]

(2)x393_dut.simul_saxi_gp0_wr_i.sim_wr_stb[3:0]

(3)x393_dut.simul_saxi_gp0_wr_i.sim_wr_stb[3:0]

@1401200

-group_end

@28

x393_dut.simul_saxi_gp0_wr_i.sim_wr_valid

x393_dut.simul_saxi_gp0_wr_i.rst

x393_dut.simul_saxi_gp0_wr_i.aclk

@22

x393_dut.simul_saxi_gp0_wr_i.wacount[3:0]

@28

x393_dut.simul_saxi_gp0_wr_i.aw_nempty

@22

x393_dut.simul_saxi_gp0_wr_i.wcount[3:0]

@28

x393_dut.simul_saxi_gp0_wr_i.w_nempty

@800200

-waddr

@28

x393_dut.simul_saxi_gp0_wr_i.waddr_i.rst

x393_dut.simul_saxi_gp0_wr_i.waddr_i.clk

x393_dut.simul_saxi_gp0_wr_i.waddr_i.we

x393_dut.simul_saxi_gp0_wr_i.waddr_i.re

x393_dut.simul_saxi_gp0_wr_i.waddr_i.nempty

x393_dut.simul_saxi_gp0_wr_i.waddr_i.out_full

x393_dut.simul_saxi_gp0_wr_i.waddr_i.rem

x393_dut.simul_saxi_gp0_wr_i.waddr_i.ram_nempty

@22

x393_dut.simul_saxi_gp0_wr_i.waddr_i.next_fill[3:0]

@200

-

@1000200

-frames

-waddr

-simul_saxi

-histgograms

@800200

-ps7

@28

x393_dut.x393_i.ps7_i.SAXIGP0ACLK

x393_dut.x393_i.ps7_i.SAXIGP0ARESETN

x393_dut.x393_i.ps7_i.MAXIGP0ACLK

x393_dut.x393_i.ps7_i.MAXIGP0ARESETN

@200

-

@1000200

-ps7

@200

-

[pattern_trace] 1

[pattern_trace] 0

cocotb/x393_cocotb_server.py

+1 −1
Original line number Diff line number Diff line
@@ -141,7 +141,7 @@ class X393_cocotb_server(object): 
                                    autoflush =  self.autoflush,

                                    blatency =   5)

        

        level = logging.DEBUG if debug else logging.WARNING

        level = logging.DEBUG if debug else logging.INFO # WARNING

        self.dut._log.info('Set debug level '+str(level)+", debug="+str(debug))

        

        self.maxigp0.log.setLevel(level)

cocotb/x393interfaces.py

+3 −5
Original line number Diff line number Diff line
@@ -172,7 +172,6 @@ class SAXIWrSim(BusDriver): 
        @param autoflush flush file after each write

        @param blatency  number of cycles to delay write response (b) channel

        """

#        self.log.setLevel(logging.DEBUG)

        BusDriver.__init__(self, entity, name, clock)

        self.name = name

        self.log.debug ("SAXIWrSim: name='%s', mempath='%s', memhigh=0x%08x, data_bytes=%d, autoflush=%s, blatency=%d"%
@@ -251,7 +250,7 @@ class SAXIWrSim(BusDriver): 
            try:

                data = self.bus.wr_data.value.integer

            except:

                self.log.warning ("SAXIWrSim() writing undefined data")

                self.log.warning ("SAXIWrSim(%s:%d) writing undefined data"%(self.name,self._data_bytes))

                bv = self.bus.wr_data.value

                bv.binstr = re.sub("[^1]","0",bv.binstr)

                data = bv.integer
@@ -270,7 +269,7 @@ class SAXIWrSim(BusDriver): 
                       self._memfile.seek(1,1)

            if self.autoflush:

                self._memfile.flush()

            self.log.debug ("SAXIWrSim() 0x%x -> 0x%x, mask = 0x%x"%(address,data,bv.integer))

            self.log.info ("SAXIWrSim(%s:%d) 0x%x <- 0x%x"%(self.name,self._data_bytes,address,data))

            yield RisingEdge(self.clock)
@@ -301,7 +300,7 @@ class SAXIRdSim(BusDriver): 
        @param data_bytes data width, in bytes

        

        """

#        self.log.setLevel(logging.DEBUG)

        

        BusDriver.__init__(self, entity, name, clock)

        self.name = name

        self.log.debug ("SAXIRdSim: name='%s', mempath='%s', memhigh=0x%08x, data_bytes=%d"%
@@ -458,7 +457,6 @@ class MAXIGPMaster(BusDriver): 
    _channels = [AR_CHN,AW_CHN,R_CHN,W_CHN,B_CHN]

    def __init__(self, entity, name, clock, rdlag=None, blag=None):

        BusDriver.__init__(self, entity, name, clock)

#        self.log.setLevel(logging.DEBUG)

        self.name = name

        # set read and write back channels simulation lag between AXI sets valid and host responds with

        # ready. If None - drive these signals

fpga_version.vh

+30 −23
Original line number Diff line number Diff line
@@ -35,7 +35,14 @@ 
 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

          parameter FPGA_VERSION =          32'h039300ae;      // parallel, increasing sesnsor-channels maximal delays to 12 bits -0.091/25, 79.89%

        parameter FPGA_VERSION =          32'h039300b4;      //-a parallel, and more - -0.180/33, 80.68 %

//        parameter FPGA_VERSION =          32'h039300b4;      // parallel, and more -0.094/37, 80.18 %

//      parameter FPGA_VERSION =          32'h039300b3;      // parallel, and more  -0.052/8, 79.56%

//      parameter FPGA_VERSION =          32'h039300b2;      // parallel, and more -0.163 /47,  79.93%

//      parameter FPGA_VERSION =          32'h039300b1;      // parallel, more debug -0.335/86, 79.66%

//      parameter FPGA_VERSION =          32'h039300b0;      // parallel, more debug -0.047/8, 79.51%

//      parameter FPGA_VERSION =          32'h039300af;      // parallel, debugging histograms all met, 79.45%

//      parameter FPGA_VERSION =          32'h039300ae;      // parallel, increasing sesnsor-channels maximal delays to 12 bits -0.091/25, 79.89%

//      parameter FPGA_VERSION =          32'h039300ad;      // parallel, resetting frame_pre_run. All met, 79.97%

//      parameter FPGA_VERSION =          32'h039300ac;      // parallel, adding reset needed_page in compressor -0.012 (2), 79.39%

//      parameter FPGA_VERSION =          32'h039300ab;      // parallel, more on frame sync in compressor All met, 79.04%