updated to version 0xb9 (parallel only), worked on camsync/rtc

cocotb/x393_cocotb_02.sav

 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Wed Sep 14 19:28:33 2016
+[*] Tue Sep 20 04:34:10 2016
 [*]
-[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160914091637595.fst"
-[dumpfile_mtime] "Wed Sep 14 17:55:04 2016"
-[dumpfile_size] 377060747
+[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160919202856605.fst"
+[dumpfile_mtime] "Tue Sep 20 04:31:39 2016"
+[dumpfile_size] 93558968
 [savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_02.sav"
-[timestart] 43511100
-[size] 1814 1171
-[pos] 1936 23
-*-14.509074 43557388 77654500 77716800 80133500 86987400 89448000 91674200 91801500 95195280 96480090 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[timestart] 42705000
+[size] 1201 767
+[pos] 2223 211
+*-19.051508 43557388 77654500 77716800 80133500 86987400 89448000 91674200 91801500 95195280 96480090 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_dut.
 [treeopen] x393_dut.ddr3_i.ddr3_i.
 [treeopen] x393_dut.simul_axi_master_wdata_i.
@@ -73,10 +73,10 @@
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
 [treeopen] x393_dut.x393_i.timing393_i.
-[sst_width] 435
+[sst_width] 212
 [signals_width] 312
 [sst_expanded] 1
-[sst_vpaned_height] 642
+[sst_vpaned_height] 380
 @820
 x393_dut.TEST_TITLE[639:0]
 @800200

cocotb/x393_dut.v

@@ -677,10 +677,10 @@ module  x393_dut#(
 
 
 
-    wire [ 9:0] gpio_pins; // inout[9:0] ([6]-synco0,[7]-syncio0,[8]-synco1,[9]-syncio1)
+    wire [ 9:0] gpio_pins; // inout[9:0] ([8]-synco0,[7]-syncio0,[6]-synco1,[9]-syncio1)
 // Connect trigger outs to triggets in (#10 needed for Icarus)
-assign #10 gpio_pins[7] = gpio_pins[6];
-assign #10 gpio_pins[9] = gpio_pins[8];
+assign #10 gpio_pins[7] = gpio_pins[8];
+assign #10 gpio_pins[9] = gpio_pins[6];
 
   // DDR3 signals
     wire        SDRST;

fpga_version.vh

@@ -35,8 +35,10 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-        parameter FPGA_VERSION =          32'h039300b7;      //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92%
-//        parameter FPGA_VERSION =          32'h039300b6;      //parallel, working on histograms odd colors bug -0.207 /58,  79.68%
+        parameter FPGA_VERSION =          32'h039300b9;      //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64%
+//      parameter FPGA_VERSION =          32'h039300b8;      //parallel, working on camsync -0.330/99, 80.52% -> -0.143 /40, 79.88% 
+//      parameter FPGA_VERSION =          32'h039300b7;      //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92%
+//      parameter FPGA_VERSION =          32'h039300b6;      //parallel, working on histograms odd colors bug -0.207 /58,  79.68%
 //      parameter FPGA_VERSION =          32'h039300b5;      //parallel, moving histograms earlier -0.123/30, 79.47 
 //      parameter FPGA_VERSION =          32'h039300b4;      //-a parallel, and more - -0.180/33, 80.68 %
 //      parameter FPGA_VERSION =          32'h039300b4;      // parallel, and more -0.094/37, 80.18 %

py393/x393_camsync.py

@@ -142,7 +142,7 @@ class X393Camsync(object):
         @param sub_chn - sensor channel (0..3)
         @param delay -   delay value in 10 ns steps - max 42.95 sec
         """
-        self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_TRIG_PERIOD, delay)
+        self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_TRIG_DELAY0+sub_chn, delay)
     
     def camsync_setup(self,
                       sensor_mask =        None,

py393/x393_jpeg.py

@@ -819,7 +819,9 @@ class X393Jpeg(object):
         if useNextReady:
             channel = self.x393Cmprs.compressor_interrupt_acknowledge(enabledOnly=True)
             if channel is None:
-                raise Exception ("No channels have new compressed images ready")
+#                raise Exception ("No channels have new compressed images ready")
+                print ("*********** No channels have new compressed images ready ************")
+                return
             else:
                 schn="-"+str(channel)
                 if '@' in file_path:
@@ -1891,6 +1893,129 @@ jpeg_sim_multi 4
 jpeg_sim_multi 4
 jpeg_sim_multi 4
 
+################## Simulate Parallel 9 - external trigger ####################
+./py393/test_mcntrl.py @py393/cocoargs  --simulated=localhost:7777
+measure_all "*DI"
+setup_all_sensors True None 0xf
+set_sensor_io_ctl  all None None 1 # Set ARO low - check if it is still needed?
+#just testing
+set_gpio_ports  1   1 # enable software gpio pins and porta (camsync)
+set_gpio_pins 0 1 # pin 0 low, pin 1 - high
+
+set_camsync_period 31 # set bit duration
+set_camsync_period 7500 # 75 usec
+set_camsync_delay 0 0
+set_camsync_delay 1 100
+set_camsync_delay 2 200
+set_camsync_delay 3 300
+#set_camsync_inout  <is_out>  <bit_number>  <active_positive>
+set_camsync_inout  1  8  0
+#set_camsync_inout  0  7  0
+reset_camsync_inout  0 # start with internal trigger
+
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
+set_camsync_mode  1 1 1 1 0 0xf
+ 
+
+
+
+set_sensor_histogram_window  0  0  4  4  25 21
+set_sensor_histogram_window  1  0  4  4  41 21
+set_sensor_histogram_window  2  0  4  4  25 41
+set_sensor_histogram_window  3  0  4  4  41 41
+
+
+
+
+r
+read_control_register 0x430
+read_control_register 0x431
+write_cmd_frame_sequencer  0  1  2  0x600  0x48   # compressor q page = 1 // too late for frame 2
+set_qtables 0 0 80
+set_qtables 0 1 70
+
+#irq coming, image not changing - yes
+write_cmd_frame_sequencer  0  1  1 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1 0x680 0x5507 #enable abort
+#write_cmd_frame_sequencer  0  1  1 0x6c6 0x300006 #save 4 more lines that compressor has                                                                                                                                    
+
+write_cmd_frame_sequencer  0  1  2  0x600  0x5    #stop    compressor           `      
+write_cmd_frame_sequencer  0  1  2  0x680  0x5405 # stop  sensor memory         (+0) // sensor memory should be controlled first, (9 commands
+write_cmd_frame_sequencer  0  1  2  0x6c0  0x5c49 # stop compressor memory      (+0)
+
+write_cmd_frame_sequencer  0  1  3 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  3  0x680  0x5507 # run sensor memory           (+1) Can not be 0
+
+write_cmd_frame_sequencer  0  1  4 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4  0x6c0  0x7d4b # run compressor memory       (+2)
+write_cmd_frame_sequencer  0  1  4  0x600  0x7    # run compressor              (+0)
+
+write_cmd_frame_sequencer  0  1  1  0x600  0x48   # compressor q page = 1
+write_cmd_frame_sequencer  0  1  4  0x600  0x40   # compressor q page = 0
+
+read_control_register 0x431
+read_control_register 0x430
+
+#testing histograms
+write_control_register 0x409 0xc0
+
+
+#sequencer test
+#ctrl_cmd_frame_sequencer  <num_sensor>  <reset=False>  <start=False>  <stop=False>
+ctrl_cmd_frame_sequencer   0  0  1  0
+write_cmd_frame_sequencer  0  1  1  0x700  0x6
+write_cmd_frame_sequencer  0  1  1  0x700  0x9
+write_cmd_frame_sequencer  0  1  1  0x700  0xa0
+write_cmd_frame_sequencer  0  1  1  0x700  0x50
+#write_cmd_frame_sequencer  0  0  3  0x700  0xa000
+write_cmd_frame_sequencer  0  1  0  0x700  0x90
+#write_cmd_frame_sequencer  0  0  2  0x700  0xe00
+write_cmd_frame_sequencer  0  0  3  0x700  0xa
+write_cmd_frame_sequencer  0  0  2  0x700  0x6
+write_cmd_frame_sequencer  0  0  2  0x700  0x9
+write_cmd_frame_sequencer  0  0  2  0x700  0x60
+write_cmd_frame_sequencer  0  0  2  0x700  0x90
+#write_cmd_frame_sequencer  0  0  2  0x700  0x600
+#write_cmd_frame_sequencer  0  0  2  0x700  0x900
+r
+read_status 0x21
+r
+#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
+#set_sensor_io_ctl all None None None None None 1 None # load all delays?
+compressor_control  all  None  None  None None None  2
+compressor_interrupt_control all clr
+compressor_interrupt_control all en
+compressor_control  all  3
+r
+read_status 0x21
+r
+jpeg_sim_multi 4
+r
+read_status 0x21
+r
+jpeg_sim_multi 3
+r
+read_status 0x21
+r
+
+write_cmd_frame_sequencer  0  1  1 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  1 0x6c6 0x200006 # correct lines                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1  0x680  0x5507 # run sensor memory, update frame#, reset buffers
+write_cmd_frame_sequencer  0  1  1  0x6c0  0x7d4b # run compressor memory
+write_cmd_frame_sequencer  0  1  1  0x600  0x7    # run compressor
+
+jpeg_sim_multi 4
+
+#switch to external (wired) trigger
+set_camsync_inout  0  7  0
+
+jpeg_sim_multi 4
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
+set_camsync_mode     None        None            None                      0
+jpeg_sim_multi 4
+jpeg_sim_multi 4
+
 
 
 ################## Serial ####################

simulation_modules/simul_sensor12bits.v

@@ -198,7 +198,8 @@ end
 
 always begin
    @ (posedge MCLK) begin
-      #tMD   c = !stoppedd;
+//      #tMD   c = !stoppedd;
+      #tMD   c = ARST && MRST; // NC393: when both are incative, (do not stop clock) 
       end
    @ (negedge MCLK) begin
       #tMD   c = 1'b0;

timing/camsync393.v

@@ -275,6 +275,7 @@ module camsync393       #(
     wire          pre_set_period;
     reg           set_period;
     wire          start_late ;// delayed start to wait for time stamp to be available
+    wire          start_late_first; // do not restart
 
     reg   [31:0]  sr_snd_first;
     reg   [31:0]  sr_snd_second;
@@ -301,7 +302,8 @@ module camsync393       #(
 
     reg           ts_external_pclk; // 1 - use external timestamp (combines ts_external and input_use_intern)
     reg           triggered_mode_pclk;
-    
+    reg           armed_internal_trigger; // to prevent re-start as in internal trigger mode timestamp over for master channel trigger s the sequence
+                                          // and that timestmp is acquired fro each delayed channel (includin master) again
     
     wire    [3:0] local_got; // received local timestamp (@ posedge mclk)
     wire    [3:0] local_got_pclk; // local_got reclocked @pclk
@@ -359,7 +361,8 @@ module camsync393       #(
     assign {ts_snap_mclk_chn3, ts_snap_mclk_chn2, ts_snap_mclk_chn1, ts_snap_mclk_chn0 } = {4{en}} & (triggered_mode? ts_snap_triggered_mclk: frame_sync);
      // keep previous value if 2'b01
 //    assign input_use_w = pre_input_use | (~pre_input_use & pre_input_pattern & input_use);
-    wire [9:0] input_mask = pre_input_pattern | ~pre_input_use;
+//    wire [9:0] input_mask = pre_input_pattern | ~pre_input_use;
+    wire [9:0] input_mask = ~pre_input_pattern | pre_input_use;
     wire [9:0] input_use_w =     ((input_use     ^ pre_input_use)     & input_mask) ^ input_use;
     wire [9:0] input_pattern_w = ((input_pattern ^ pre_input_pattern) & input_mask) ^ input_pattern;
 
@@ -464,6 +467,9 @@ module camsync393       #(
         endcase
     end    
     always @ (posedge pclk) begin
+        if (!input_use_intern || start_late) armed_internal_trigger <= 0;
+        else if (start_pclk[2])              armed_internal_trigger <= 1;
+        
         ts_snap_triggered <=  chn_en & ({4{(start_pclk[2] & ts_snd_en_pclk)}} | //strobe by internal generator if output timestamp is enabled
                               (trig_r & ~{4{ts_external_pclk}}));  // get local timestamp of the trigger (ext/int)
 
@@ -557,7 +563,10 @@ module camsync393       #(
                                        (rcv_run_or_deaf && !(bit_rcv_duration_zero  && (bit_rcv_counter[6:0]==0))));
 
         rcv_run_d <= rcv_run; 
-        start_dly <= input_use_intern ? (start_late && start_en) : (rcv_run && !rcv_run_d); // all start at the same time - master/others
+        
+        start_dly <= input_use_intern ?
+                      (start_late_first && start_en) : // only use armed_internal_trigger with timestamps
+                      (rcv_run && !rcv_run_d);  // all start at the same time - master/others
 // simulation problems w/o "start_en &&" ? 
 
         dly_cntr_run_d <= dly_cntr_run;
@@ -574,10 +583,10 @@ module camsync393       #(
         else                 dly_cntr_chn3[31:0] <= input_dly_chn3[31:0];
         
         /// bypass delay to trig_r in internal trigger mode
-        trig_r[0] <= (input_use_intern && (master_chn ==0)) ? (start_late && start_en): dly_cntr_end[0];
-        trig_r[1] <= (input_use_intern && (master_chn ==1)) ? (start_late && start_en): dly_cntr_end[1];
-        trig_r[2] <= (input_use_intern && (master_chn ==2)) ? (start_late && start_en): dly_cntr_end[2];
-        trig_r[3] <= (input_use_intern && (master_chn ==3)) ? (start_late && start_en): dly_cntr_end[3];
+        trig_r[0] <= (input_use_intern && (master_chn ==0)) ? (start_late_first && start_en): dly_cntr_end[0];
+        trig_r[1] <= (input_use_intern && (master_chn ==1)) ? (start_late_first && start_en): dly_cntr_end[1];
+        trig_r[2] <= (input_use_intern && (master_chn ==2)) ? (start_late_first && start_en): dly_cntr_end[2];
+        trig_r[3] <= (input_use_intern && (master_chn ==3)) ? (start_late_first && start_en): dly_cntr_end[3];
         
 /// 64-bit serial receiver (52 bit payload, 6 pre magic and 6 bits post magic for error checking
         if      (!rcv_run_or_deaf)         bit_rcv_duration[7:0] <= bit_length_short[7:0]; // 3/4 bit length-1
@@ -636,9 +645,9 @@ module camsync393       #(
     end
 
     assign ts_stb = (!ts_external || pre_input_use_intern) ? local_got : {4{rcv_done_mclk}};
-    // Making delayed start that waits for timestamp use timestamp_got, otherwize - nothing to wait
+    // Making delayed start that waits for timestamp use timestamp_got, otherwise - nothing to wait
     assign start_late = ts_snd_en_pclk?local_got_pclk[master_chn] :  start_pclk[2];    
-    
+    assign start_late_first = start_late && (armed_internal_trigger|| !ts_snd_en_pclk);
     
     cmd_deser #(
         .ADDR       (CAMSYNC_ADDR),

timing/rtc393.v

@@ -139,11 +139,18 @@ module  rtc393 #(
     
     always @ (posedge mclk) begin
         
-        if (!enable_rtc || halfusec[0]) pre_cntr <= RTC_MHZ-2;
-        else if (refclk2x_mclk)         pre_cntr <= pre_cntr - 1;
+//        if (!enable_rtc || halfusec[0]) pre_cntr <= RTC_MHZ-2;
+//        else if (refclk2x_mclk)         pre_cntr <= pre_cntr - 1;
+        
+//        if (!enable_rtc) halfusec <= 0;
+//        else             halfusec <= {halfusec[2:0], (|pre_cntr || !refclk2x_mclk)?1'b0:1'b1};
+
+        if      (!enable_rtc)   pre_cntr <= RTC_MHZ-1;
+        else if (refclk2x_mclk) pre_cntr <= (|pre_cntr) ? (pre_cntr - 1) : (RTC_MHZ-1);
         
         if (!enable_rtc) halfusec <= 0;
         else             halfusec <= {halfusec[2:0], (|pre_cntr || !refclk2x_mclk)?1'b0:1'b1};
+
         
         if (set_usec_w)      pend_set_cntr <= 1'b0; // just to get rid of undefined
         if (set_sec_w)       pend_set_cntr <= 1'b1;