Commit a500d197 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Finished simulation/testing of a single-channel...

Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
parent df351507
Loading
Loading
Loading
Loading
+14 −14
Original line number Diff line number Diff line
@@ -62,42 +62,42 @@
		<link>
			<name>vivado_logs/VivadoBitstream.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150723191855730.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150818191452916.log</location>
		</link>
		<link>
			<name>vivado_logs/VivadoOpt.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150723191855730.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150818190618667.log</location>
		</link>
		<link>
			<name>vivado_logs/VivadoOptPhys.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150723191855730.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150818191452916.log</location>
		</link>
		<link>
			<name>vivado_logs/VivadoOptPower.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150723191855730.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150818190618667.log</location>
		</link>
		<link>
			<name>vivado_logs/VivadoPlace.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150723191855730.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150818190618667.log</location>
		</link>
		<link>
			<name>vivado_logs/VivadoRoute.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150723191855730.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150818191452916.log</location>
		</link>
		<link>
			<name>vivado_logs/VivadoSynthesis.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150725144518149.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150818185615292.log</location>
		</link>
		<link>
			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150723191855730.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150818191452916.log</location>
		</link>
		<link>
			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
@@ -107,32 +107,32 @@
		<link>
			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150723191855730.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150818191452916.log</location>
		</link>
		<link>
			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150725144518149.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150818185615292.log</location>
		</link>
		<link>
			<name>vivado_state/x393-opt-phys.dcp</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150723191855730.dcp</location>
			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150818191452916.dcp</location>
		</link>
		<link>
			<name>vivado_state/x393-place.dcp</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_state/x393-place-20150723191855730.dcp</location>
			<location>/home/andrey/git/x393/vivado_state/x393-place-20150818190618667.dcp</location>
		</link>
		<link>
			<name>vivado_state/x393-route.dcp</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_state/x393-route-20150723191855730.dcp</location>
			<location>/home/andrey/git/x393/vivado_state/x393-route-20150818191452916.dcp</location>
		</link>
		<link>
			<name>vivado_state/x393-synth.dcp</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150725144518149.dcp</location>
			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150818185615292.dcp</location>
		</link>
	</linkedResources>
</projectDescription>
+2 −1
Original line number Diff line number Diff line
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
VivadoSynthesis_95_ShowInfo=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->
eclipse.preferences.version=1
+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@
** -----------------------------------------------------------------------------**
**
*/
`include "system_defines.vh" 
`timescale 1ns/1ps
//TODO: Modify to work with other modes (now only on color)
module focus_sharp393(
+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@
** -----------------------------------------------------------------------------**
**
*/
`include "system_defines.vh" 
// 01/22/2004 - extended flush until ready (modified stuffer.v too)
module huffman393    (
    input             xclk,            // pixel clock, sync to incoming data
+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@
** -----------------------------------------------------------------------------**
**
*/

`include "system_defines.vh" 
`timescale 1ns/1ps

// will add extracted DC (8 bits) to data from DCT here that will make data 12 bits (signed) long.
Loading