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.settings Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
axi more simulating cmprs_afi_mux
compressor_jp Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
ddr3 continiuing co-simulation with 353 code, verified martching data to the compressor input
docs Description of the memory controller clocks and programmable delays
hardware_tests eye pattern tests at 400MHz
helpers continue debugging
includes Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
input_data making previous simulation tasks run on the full x393 code
logger modified files similar to x353 ones
memctrl Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
py393 project settings for Eclipse Mars
sensor Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
simulation_modules simulating cmprs_afi_mux
timing Matched simulation (agianst 353) through all the compression modules
unisims_patches patch to work with Icarus Verilog simulator
util_modules continiuing co-simulation with 353 code, verified martching data to the compressor input
wrap Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
.editor_defines copied CVC-related changes from master branch
.gitignore fixed gitignore - had spaces at the eol
.project Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
.pydevproject organized new/debug files
OSERDESE1.diff Modifications for Icarus Verilog
README.md formatting
address_map.txt before adding extra register layer between channel buffers outputs and memory controller
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README.md

x393

FPGA code for Elphel 393 camera, created with VDT plugin

Branch master includes the code that is simulated and tested with the NC393 hardware as described in the blog post about the multichannel memory controller.

Branch adding_sensors is the current development branch that is not yet simulated, synthesized or tested.