Merge branch 'serial-sensors' to master (944ff196) · Commits · Elphel / x393

.project

+8 −8

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		@@ -62,42 +62,42 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151107204814914.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151117233913191.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151107161051349.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151117233913191.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151107161322372.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151117233913191.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151107161051349.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151117233913191.log</location>
		</link>
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		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151107161322372.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151117233913191.log</location>
		</link>
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		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151107161322372.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151117233913191.log</location>
		</link>
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		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151107160339590.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151117233307674.log</location>
		</link>
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		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151107204814914.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151117233913191.log</location>
		</link>
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		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

axi/cmprs_afi_mux.v

+19 −7

Original line number	Diff line number	Diff line
		@@ -195,11 +195,12 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),

		// reg [2:0] cur_chn; // 'b0xx - none, 'b1 - - channel number (should match fifo_ren*)
		reg [1:0] cur_chn; // 'b0xx - none, 'b1 - - channel number (should match fifo_ren*)
		reg [31:0] left_to_eof; // number of chunks left to end of frame
		reg [31:0] left_to_eof; // number of chunks left to end of frame (one less: 3 means 4 left)
		reg [3:0] fifo_flush_d; // fifo_flush* delayed by 1 clk (to detect rising edge
		reg [3:0] eof_stb; // single-cycle pulse after fifo_flush is asserted
		// reg [1:0] w64_cnt; // count 64-bit words in a chunk
		// adjusted counters used for channel arbitration
		// pessimistic FIFO content counter - decrements (form FIFO counter) on FIFO reads, knows nothing of writes
		reg [35:0] counts_corr0; // registers to hold corrected (decremented currently processed ones if any) fifo count values, MSB - needs flush
		reg [17:0] counts_corr1; // first arbitration level winning values
		reg [8:0] counts_corr2; // second arbitration level winning values
		@@ -231,6 +232,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
		// 3'h4 :
		// ({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);

		// Why it has priority for \|counts_corr2[7:2] ? If next frame started, it may skip EOF? Or not?
		// it is just to pass to a channel, actual transfer size will be decided here (depending on EOF)
		wire [1:0] pre_chunk_inc_m1 = (\|counts_corr2[7:2])? // Would like to increment, if not roll-over
		2'h3 :
		left_to_eof[winner2 * 8 +: 2];
		@@ -252,12 +255,15 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),

		wire [26:0] chunk_ptr_rd;
		wire [ 3:0] chunk_ptr_ra;

		// If flushing - whatever is left to EOF, otherwise corrected FIFO contents of the winner
		wire [ 7:0] items_left = counts_corr2[8] ? left_to_eof[(winner2 * 8) +: 8] : counts_corr2[7:0];

		reg [5:0] afi_awid_r;

		// "rollover" - roll over destination memory range
		wire [2:0] max_wlen; // 0,1,2,3,7 (7 - not limited by rollover) - calculated by cmprs_afi_mux_ptr
		wire [1:0] want_wleft32 = (\|items_left[7:2])? 2'b11 : items_left[1:0]; // want to set wleft[3:2] if not roll-over
		// wants to write (want_wleft32+1) 32-byte chunks (4,3,2,1)
		wire [1:0] want_wleft32 = (\|items_left[7:2])? 2'b11 : items_left[1:0]; // want to set wleft[3:2] if not roll-over (actually "3" means 2)

		assign cmd_we_status_w = cmd_we && ((cmd_a & 'hc) == CMPRS_AFIMUX_STATUS_CNTRL);
		assign cmd_we_mode_w = cmd_we && (cmd_a == CMPRS_AFIMUX_MODE);
		@@ -366,16 +372,22 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
		// TODO: change &w64_cnt[1:0] so left_to_eof[*] will be updated earlier and valid at pre_busy_w
		// Done, updating at the first (not last) word of 4
		// Now seems that eof_stb[i] & fifo_ren{i} == 0
		if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - (fifo_ren0 & (&wleft[1:0]));
		// Seems needs to decrement fifo_count0_m1 regardless of &wleft[1:0] - if started, will eventually decrement
		// How to make sure that decremented value always >0?
		// if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - (fifo_ren0 & (&wleft[1:0]));
		if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - fifo_ren0;
		else if (fifo_ren0 & (&wleft[1:0])) left_to_eof[0 * 8 +: 8] <= left_to_eof[0 * 8 +: 8] - 1;

		if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - (fifo_ren1 & (&wleft[1:0]));
		// if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - (fifo_ren1 & (&wleft[1:0]));
		if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - fifo_ren1;
		else if (fifo_ren1 & (&wleft[1:0])) left_to_eof[1 * 8 +: 8] <= left_to_eof[1 * 8 +: 8] - 1;

		if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - (fifo_ren2 & (&wleft[1:0]));
		// if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - (fifo_ren2 & (&wleft[1:0]));
		if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - fifo_ren2;
		else if (fifo_ren2 & (&wleft[1:0])) left_to_eof[2 * 8 +: 8] <= left_to_eof[2 * 8 +: 8] - 1;

		if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - (fifo_ren3 & (&wleft[1:0]));
		// if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - (fifo_ren3 & (&wleft[1:0]));
		if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - fifo_ren3;
		else if (fifo_ren3 & (&wleft[1:0])) left_to_eof[3 * 8 +: 8] <= left_to_eof[3 * 8 +: 8] - 1;

		// Calculate corrected values decrementing currently served channel (if any) values by 1 (latency 1 clk)

axi/membridge.v

+2 −1

Original line number	Diff line number	Diff line
		@@ -749,6 +749,7 @@ wire [63:0] afi_wdata0;
		.ext_rd (bufrd_rd[0]), // input
		.ext_regen (bufrd_rd[1]), // input
		.ext_data_out (afi_wdata0), // output[63:0]
		// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
		.wclk (!mclk), // input
		.wpage_in (2'b0), // input[1:0]
		.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start

compressor_jp/bit_stuffer_metadata.v

+1 −1

Original line number	Diff line number	Diff line
		@@ -146,7 +146,7 @@ module bit_stuffer_metadata(

		// just for testing
		`ifdef DEBUG_RING
		assign dbg_ = ts_rstb;
		assign dbg_ts_rstb = ts_rstb;
		assign dbg_ts_dout = ts_dout;

		always @ (posedge xclk) begin

compressor_jp/cmprs_pixel_buf_iface.v

+28 −9

Original line number	Diff line number	Diff line
		@@ -67,9 +67,11 @@ module cmprs_pixel_buf_iface #(
		// controller this can just be the same as mb_pre_end_in
		input mb_pre_start, // 1 clock cycle before stream of addresses to the buffer
		input [ 1:0] start_page, // page to read next tile from (or first of several pages)
		input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide
		input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide.
		// valid 3 cycles before mb_pre_start
		output reg [ 7:0] data_out, //
		output pre_first_out, // For each macroblock in a frame
		output pre2_first_out, // 1 cycle before pre_first_out
		output reg data_valid //
		);
		localparam PERIOD_COLOR18 = 384; // >1818, limited by 664 (macroblocks)
		@@ -105,8 +107,13 @@ module cmprs_pixel_buf_iface #(
		reg [ 8:0] period_cntr;
		reg mb_pre_end_r;
		reg mb_release_buf_r;
		reg pre_first_out_r;
		reg [CMPRS_BUF_EXTRA_LATENCY+2:0] pre_first_out_r;

		reg [ 2:0] mb_col_number; // number of tile column where macrobloc starts - valid 2 cycles before mb_pre_start
		wire [ 9:0] extra_start_addr_w = mb_col_number * mb_h_m1; //added to mb_start_addr when non-zero column
		reg [ 5:0] extra_start_addr_r;
		// reg [ 5:0] mb_h; // macroblock height (lost MSB - OK)
		reg [ 9:0] mb_start_addr; // was macroblock_x, noccrected for multi-column. valid with mb_pre_start

		assign buf_ra = bufa_r;
		assign tile_width_or= tile_width[1]?(tile_width[0]?0:'h40):(tile_width[0]?'h60:'h70);
		@@ -119,9 +126,15 @@ module cmprs_pixel_buf_iface #(
		assign mb_release_buf = mb_release_buf_r;
		assign buf_rd = buf_re[1:0];
		// assign data_out = do_r;
		assign pre_first_out = pre_first_out_r;
		assign pre_first_out = pre_first_out_r[0];
		assign pre2_first_out = pre_first_out_r[1];

		always @(posedge xclk) begin
		// mb_h <= mb_h_m1+1; // macroblock height
		mb_col_number <= {macroblock_x[6:5],tile_col_width?1'b0:macroblock_x[4]};
		extra_start_addr_r <= extra_start_addr_w[5:0];
		mb_start_addr <= {3'b0,macroblock_x} + {extra_start_addr_r,4'b0};

		if (!frame_en) buf_re[0] <= 0;
		else if (mb_pre_start) buf_re[0] <= 1'b1;
		else if (addr_run_end) buf_re[0] <= 1'b0;
		@@ -131,9 +144,13 @@ module cmprs_pixel_buf_iface #(

		// Buffer data read:
		if (buf_re[CMPRS_BUF_EXTRA_LATENCY+2]) data_out <= buf_di;

		//mb_pre_start
		if (!frame_en) pre_first_out_r <= 0;
		else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
		else pre_first_out_r <= {mb_pre_start, pre_first_out_r[CMPRS_BUF_EXTRA_LATENCY + 2 : 1]};
		// else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];

		// if (!frame_en) pre2_first_out <= 0;
		// else pre2_first_out <= buf_re[CMPRS_BUF_EXTRA_LATENCY + 0] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY + 1];

		if (mb_pre_start) rows_left <= mb_h_m1;
		else if (last_col) rows_left <= rows_left - 1;
		@@ -153,7 +170,8 @@ module cmprs_pixel_buf_iface #(

		first_col <= (mb_pre_start \|\| (last_col && !last_row));

		if (mb_pre_start) row_sa <= {start_page,3'b0,macroblock_x};
		// if (mb_pre_start) row_sa <= {start_page,3'b0,mb_start_addr}; // macroblock_x};
		if (mb_pre_start) row_sa <= {start_page,mb_start_addr}; // macroblock_x};
		else if (first_col) row_sa <= row_sa + (tile_col_width ? 12'h20:12'h10);

		if (mb_pre_start) tile_sa <= 0;
		@@ -172,7 +190,8 @@ module cmprs_pixel_buf_iface #(
		else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1;

		// Most time critical - calculation of the buffer address
		if (mb_pre_start) bufa_r[9:0] <= {3'b0,macroblock_x};
		// if (mb_pre_start) bufa_r[9:0] <= {3'b0,mb_start_addr}; // macroblock_x};
		if (mb_pre_start) bufa_r[9:0] <= {mb_start_addr}; // macroblock_x};
		else if (last_col) bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start
		else if (last_in_tile) bufa_r[9:0] <= tile_sa;
		else if (buf_re[0]) bufa_r[9:0] <= bufa_r[9:0] + {last_in_col?col_inc[9:4]:6'b0,4'b1};

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