Skip to content

X
x393
Commit 9145e396 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

merged with framepars

parents b02bac09 cf5bee66
Hide whitespace changes
Inline Side-by-side
Showing with 308 additions and 40 deletions
Makefile
View file @ 9145e396
......@@ -23,6 +23,9 @@ COMMAND_FILES = py393/hargs \
py393/hargs-auto \
py393/hargs-after \
py393/hargs-eyesis \
py393/hargs-post-par12 \
py393/hargs-power_par12 \
py393/hargs-power-eyesis \
py393/includes \
py393/startup5 \
py393/startup14
......
cocotb/x393_cocotb_03.sav
View file @ 9145e396
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Thu Oct 27 01:40:51 2016
[*] Mon Nov 7 00:04:33 2016
[*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161026180017757.fst"
[dumpfile_mtime] "Thu Oct 27 01:39:08 2016"
[dumpfile_size] 418439836
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161106163115099.fst"
[dumpfile_mtime] "Mon Nov 7 00:03:53 2016"
[dumpfile_size] 125174737
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav"
[timestart] 0
[size] 1814 1171
[pos] 0 0
*-27.006804 350100000 53094051 136169617 216213845 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-25.890059 103100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.simul_sensor12bits_2_i.
[treeopen] x393_dut.simul_sensor12bits_3_i.
......@@ -25,15 +25,20 @@
[treeopen] x393_dut.x393_i.event_logger_i.i_logger_arbiter.
[treeopen] x393_dut.x393_i.event_logger_i.i_nmea_decoder.
[treeopen] x393_dut.x393_i.event_logger_i.i_rs232_rcv.
[treeopen] x393_dut.x393_i.frame_sequencer_block[0].
[treeopen] x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
[treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.
[treeopen] x393_dut.x393_i.sensors393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_parallel12_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
......@@ -41,7 +46,7 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.timing393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[sst_width] 282
[sst_width] 440
[signals_width] 319
[sst_expanded] 1
[sst_vpaned_height] 486
......@@ -771,13 +776,13 @@ x393_dut.x393_i.axiwr_wen
x393_dut.x393_i.axiwr_wdata[31:0]
@1401200
- cmd
@800200
@c00200
-i2c
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.rpointer[5:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wpage0[3:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.page_r[3:0]
@1000200
@1401200
-i2c
@c00200
-gpio
......@@ -1838,7 +1843,7 @@ x393_dut.IMU_SDA
x393_dut.IMU_TAPS[5:1]
@1401200
-IMU_
@800200
@c00200
-camsync_ext_int
@800022
x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
......@@ -1907,9 +1912,9 @@ x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition
x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_filtered
@22
x393_dut.x393_i.timing393_i.camsync393_i.input_pattern[9:0]
@c00023
@c00022
x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
@29
@28
(0)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
(1)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
(2)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
......@@ -1920,15 +1925,114 @@ x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
(7)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
(8)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
(9)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
@1401201
@1401200
-group_end
@1001200
-group_end
-group_end
-group_end
@1401200
-camsync_ext_int
@800200
-sequencers_0
-cmd_frame_seq0
@28
x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.frame_sync
@22
x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.frame_no[3:0]
@1000200
-cmd_frame_seq0
@800200
-i2c_seq_0
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_sync
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.req_clr
@c00028
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wpage0_inc[1:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wpage0_inc[1:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wpage0_inc[1:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sync_to_seq
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sync_to_eof
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_num_seq[3:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_num[3:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.eof_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.use_eof
@1000200
-i2c_seq_0
@800200
-sensor_channel0
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_out_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof_out_r
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.en_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hact
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.frame_num_seq[3:0]
@800200
-sesns_sync
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_late
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_out_pclk
@200
-
@1000200
-camsync_ext_int
-sesns_sync
-sensor_channel0
-sequencers_0
@800200
-sensor_channel_a
@28
x393_dut.simul_sensor12bits_2_i.MRST
x393_dut.simul_sensor12bits_2_i.HACT
x393_dut.simul_sensor12bits_2_i.VACT
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sof_out_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.en_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.en_pclk
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.frame_num_seq[3:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.sof_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.sof_out_pclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.sof_late
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.frame_num_seq[3:0]
@200
-chn2
@28
x393_dut.simul_sensor12bits_3_i.MRST
x393_dut.simul_sensor12bits_3_i.HACT
x393_dut.simul_sensor12bits_3_i.VACT
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.en_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.en_pclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sof_out_mclk
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.eof_mclk
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.frame_num_seq[3:0]
@800200
-sens_sync2
@200
-
@1000200
-sens_sync2
-sensor_channel_a
@800022
x393_dut.x393_i.sof_out_mclk[3:0]
@28
(0)x393_dut.x393_i.sof_out_mclk[3:0]
(1)x393_dut.x393_i.sof_out_mclk[3:0]
(2)x393_dut.x393_i.sof_out_mclk[3:0]
(3)x393_dut.x393_i.sof_out_mclk[3:0]
@1001200
-group_end
[pattern_trace] 1
[pattern_trace] 0
cocotb/x393_dut.v
View file @ 9145e396
......@@ -1613,7 +1613,7 @@ simul_axi_hp_wr #(
.new_bayer (0) //SENSOR12BITS_NEW_BAYER) was 1
) simul_sensor12bits_2_i (
.MCLK (PX2_MCLK), // input
.MRST (PX2_MRST), // input
.MRST (PX2_MRST & 0), // input // force reset !!!
.ARO (PX2_ARO), // input
.ARST (PX2_ARST), // input
.OE (1'b0), // input output enable active low
......
fpga_version.vh
View file @ 9145e396
......@@ -35,8 +35,12 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300c3; //parallel - fixing timestamps
// parameter FPGA_VERSION = 32'h039300c2; //parallel - external sync for Eyesis -0.160/71 79.84%
parameter FPGA_VERSION = 32'h039300c7; //parallel - disable SoF when channel disabled
// parameter FPGA_VERSION = 32'h039300c6; //parallel - same -0.132 /31, 80.73%
// parameter FPGA_VERSION = 32'h039300c5; //parallel - made i2c ahead of system frame number for eof -0.027/12 , 82.08%
// parameter FPGA_VERSION = 32'h039300c4; //parallel - option to use EOF for i2c sequencer timing met, 79.66%
// parameter FPGA_VERSION = 32'h039300c3; //parallel - fixing timestamps -0.209/47, 79.86%
// parameter FPGA_VERSION = 32'h039300c2; //parallel - external sync for Eyesis -0.160/71 79.84%
// parameter FPGA_VERSION = 32'h039300c1; //parallel - modified after troubleshooting simulation -0.069/41, 79.90 %
// parameter FPGA_VERSION = 32'h039300c0; //parallel - changing LOGGER_PAGE_IMU 3->0 (how it was in 353) -0.044/16, 79.59%
// parameter FPGA_VERSION = 32'h039300bf; //parallel - mask extrenal timestamps mode -0.043/17 79.56%
......
includes/x393_parameters.vh
View file @ 9145e396
......@@ -386,6 +386,7 @@
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_USE_EOF = 8, // [9:8] - 0: advance sequencer at SOF, 1 - advance sequencer at EOF
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
......
py393/hargs-post-par12 0 → 100644
View file @ 9145e396
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_parallel.bit
-c measure_all "*DI"
-c setSensorClock 24.0 "2V5_LVDS"
-c set_rtc
py393/hargs-power-eyesis 0 → 100644
View file @ 9145e396
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c setEyesisPower 1
py393/hargs-power_par12 0 → 100644
View file @ 9145e396
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c setupSensorsPower "PAR12" all 0 0.2
py393/x393_export_c.py
View file @ 9145e396
......@@ -1900,6 +1900,7 @@ class X393ExportC(object):
dw.append(("soft_scl", vrlg.SENSI2C_CMD_SOFT_SCL, 2,0, "Control SCL pin (when stopped): 0 - nop, 1 - low, 2 - high (driven), 3 - float "))
dw.append(("soft_sda", vrlg.SENSI2C_CMD_SOFT_SDA, 2,0, "Control SDA pin (when stopped): 0 - nop, 1 - low, 2 - high (driven), 3 - float "))
dw.append(("eof_not_sof", vrlg.SENSI2C_CMD_USE_EOF, 2,0, "Advance I2C sequencer: 0 - SOF, 1 - EOF"))
dw.append(("cmd_run", vrlg.SENSI2C_CMD_RUN-1, 2,0, "Sequencer run/stop control: 0,1 - nop, 2 - stop, 3 - run "))
dw.append(("reset", vrlg.SENSI2C_CMD_RESET, 1,0, "Sequencer reset all FIFO (takes 16 clock pulses), also - stops i2c until run command"))
......
py393/x393_jpeg.py
View file @ 9145e396
......@@ -2166,6 +2166,7 @@ measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 1 # enable software gpio pins and porta (camsync)
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
......@@ -2280,12 +2281,22 @@ jpeg_sim_multi 8
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#use EOF instead of SOF for i2c sequencer advance
set_sensor_i2c_command all False None None None None None None True
#just testing
set_gpio_ports 1 1 # enable software gpio pins and porta (camsync)
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
write_control_register 0x480 0x400 # disable sensor chn 2
reset_camsync_inout 1 # reset all outputs
set_camsync_period 31 # set bit duration
set_camsync_period 8000 # 80 usec
......
py393/x393_sensor.py
View file @ 9145e396
......@@ -287,6 +287,7 @@ class X393Sensor(object):
advance_FIFO = None,
sda = None,
scl = None,
use_eof = None,
verbose = 1):
"""
@param rst_cmd - reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
......@@ -296,6 +297,7 @@ class X393Sensor(object):
@param advance_FIFO - advance i2c read FIFO
@param sda - control SDA line (stopped mode only): I<nput>, L<ow> or 0, High or 1
@param scl - control SCL line (stopped mode only): I<nput>, L<ow> or 0, High or 1
@param use_eof - advance sequencer at EOF, not at SOF
@param verbose - verbose level
@return combined command word.
active_sda and early_release_0 should be defined both to take effect (any of the None skips setting these parameters)
......@@ -338,6 +340,10 @@ class X393Sensor(object):
rslt |= 1 << vrlg.SENSI2C_CMD_ACIVE
if advance_FIFO:
rslt |= 1 << vrlg.SENSI2C_CMD_FIFO_RD
if not use_eof is None:
rslt |= 1 << (vrlg.SENSI2C_CMD_USE_EOF + 1)
rslt |= (0,1)[use_eof] << (vrlg.SENSI2C_CMD_USE_EOF)
rslt |= parse_sda_scl(sda) << vrlg.SENSI2C_CMD_SOFT_SDA
rslt |= parse_sda_scl(scl) << vrlg.SENSI2C_CMD_SOFT_SCL
if verbose>0:
......@@ -554,6 +560,7 @@ class X393Sensor(object):
advance_FIFO = None,
sda = None,
scl = None,
use_eof = None,
verbose = 1):
"""
@param num_sensor - sensor port number (0..3) or all
......@@ -564,6 +571,7 @@ class X393Sensor(object):
@param advance_FIFO - advance i2c read FIFO
@param sda - control SDA line (stopped mode only): I<nput>, L<ow> or 0, High or 1
@param scl - control SCL line (stopped mode only): I<nput>, L<ow> or 0, High or 1
@param use_eof - advance sequencer at EOF, not at SOF
@param verbose - verbose level
active_sda and early_release_0 should be defined both to take effect (any of the None skips setting these parameters)
......@@ -579,6 +587,7 @@ class X393Sensor(object):
advance_FIFO = advance_FIFO,
sda = sda,
scl = scl,
use_eof = use_eof,
verbose = verbose)
return
......@@ -595,6 +604,7 @@ class X393Sensor(object):
advance_FIFO = advance_FIFO,
sda = sda,
scl = scl,
use_eof = use_eof,
verbose = verbose-1))
def set_sensor_i2c_table_reg_wr (self,
......
sensor/sens_sync.v
View file @ 9145e396
......@@ -98,7 +98,7 @@ module sens_sync#(
reg trig_r;
reg [SENS_SYNC_MINBITS-1:0] period_cntr;
reg period_dly; // runnning counter to enforce > min period
reg en_pclk;
assign set_data_mclk = cmd_we && ((cmd_a == SENS_SYNC_MULT) || (cmd_a == SENS_SYNC_LATE));
assign zero_frames_left = !(|sub_frames_left);
assign hact_single = hact && !hact_r;
......@@ -113,6 +113,9 @@ module sens_sync#(
end
always @ (posedge pclk) begin
en_pclk <= en;
if (set_data_pclk && (cmd_a_r == SENS_SYNC_MULT))
sub_frames_pclk <= cmd_data_r[SENS_SYNC_FBITS-1:0];
......@@ -186,7 +189,7 @@ module sens_sync#(
);
pulse_cross_clock pulse_cross_clock_trig_in_pclk_i (
.rst (mrst), // input
.rst (!en), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (trig_in), // input
......@@ -195,17 +198,19 @@ module sens_sync#(
);
// pclk -> mclk
pulse_cross_clock pulse_cross_clock_sof_out_i (
.rst (prst), // input
pulse_cross_clock_orst pulse_cross_clock_sof_out_i (
.rst (!en_pclk), // input
.src_clk (pclk), // input
.orst (!en), // input // should work even if pclk is not running
.dst_clk (mclk), // input
.in_pulse (pre_sof_out), // input
.out_pulse (sof_out), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_sof_late_i (
.rst (prst), // input
pulse_cross_clock_orst pulse_cross_clock_sof_late_i (
.rst (!en_pclk), // input
.src_clk (pclk), // input
.orst (!en), // input // should work even if pclk is not running
.dst_clk (mclk), // input
.in_pulse (pre_sof_late), // input
.out_pulse (sof_late), // output
......@@ -213,4 +218,3 @@ module sens_sync#(
);
endmodule
sensor/sensor_channel.v
View file @ 9145e396
......@@ -90,6 +90,7 @@ module sensor_channel#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_USE_EOF = 8, // [9:8] - 0: advance sequencer at SOF, 1 - advance sequencer at EOF
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
......@@ -416,6 +417,7 @@ module sensor_channel#(
wire hact; // line active @posedge ipclk
wire sof; // start of frame
wire eof; // end of frame
wire eof_mclk; // to be used by i2c sequencer
wire sof_out_sync; // sof filtetred, optionally decimated (for linescan mode)
......@@ -644,6 +646,7 @@ module sensor_channel#(
.SENSI2C_CMD_RESET (SENSI2C_CMD_RESET),
.SENSI2C_CMD_RUN (SENSI2C_CMD_RUN),
.SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS),
.SENSI2C_CMD_USE_EOF (SENSI2C_CMD_USE_EOF),
.SENSI2C_CMD_SOFT_SDA (SENSI2C_CMD_SOFT_SDA),
.SENSI2C_CMD_SOFT_SCL (SENSI2C_CMD_SOFT_SCL),
.SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD),
......@@ -676,6 +679,8 @@ module sensor_channel#(
.status_rq (sens_i2c_status_rq), // output
.status_start (sens_i2c_status_start), // input
.frame_sync (sof_out_mclk), // input
.eof_mclk (eof_mclk), // End of frame for i2c sequencer (will not work for linescan mode: either disable or make
// division as in sof_out_mclk
.frame_num_seq (frame_num_seq), // input[3:0]
.scl (sns_scl), // inout
.sda (sns_sda) // inout
......@@ -692,7 +697,7 @@ module sensor_channel#(
reg hist_gr0_r;
wire sol_mclk;
wire sof_mclk;
wire eof_mclk;
// wire eof_mclk;
wire alive_hist0_rq = hist_rq[0] && !hist_rq0_r;
wire alive_hist0_gr = hist_gr[0] && !hist_gr0_r;
// sof_out_mclk - already exists
......@@ -739,15 +744,6 @@ module sensor_channel#(
.busy() // output
);
pulse_cross_clock pulse_cross_clock_eof_mclk_i (
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (eof), // input
.out_pulse (eof_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_dout_valid_1cyc_mclk_i (
// .rst (prst), // input
......@@ -771,6 +767,14 @@ module sensor_channel#(
`endif
pulse_cross_clock pulse_cross_clock_eof_mclk_i (
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (eof), // input
.out_pulse (eof_mclk), // output
.busy() // output
);
......
sensor/sensor_i2c.v
View file @ 9145e396
......@@ -53,6 +53,7 @@ module sensor_i2c#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_USE_EOF = 8, // [9:8] - 0: advance sequencer at SOF, 1 - advance sequencer at EOF
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
......@@ -88,6 +89,7 @@ module sensor_i2c#(
input status_start,// Acknowledge of the first status packet byte (address)
input frame_sync, // @posedge mclk increment/reset frame number
input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer (to sync i2c)
input eof_mclk, // frame end (use as alternative i2c sequencer increment (disable for linescan mode)
input sda_in, // i2c SDA input
input scl_in, // i2c SCL input
output scl_out, // i2c SCL output
......@@ -185,11 +187,15 @@ module sensor_i2c#(
wire sda_hard;
wire sda_en_hard;
wire scl_hard;
reg use_eof; // advance sequencer with eof, not sof
`ifdef I2C_FRAME_INDEPENDENT
localparam sync_to_seq = 0;
localparam sync_to_eof = 0;
`else
reg sync_to_seq;
reg sync_to_eof;
`endif
reg [5:0] last_wp; // last written write pointer
reg [5:0] last_wp_d; // last written write pointer, delayed to match rpointer
......@@ -209,6 +215,7 @@ module sensor_i2c#(
assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0
assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0
assign pre_wpage0_inc = (!wen && !(|wen_r) && !wpage0_inc[0]) && (req_clr || reset_on) ;
/// assign pre_wpage0_inc = (!wen && !(|wen_r) && !(|wpage0_inc)) && (req_clr || reset_on) ;
assign fifo_wr_pointers_outw = fifo_wr_pointers_ram[wpage_wr[3:0]]; // valid next after command
......@@ -328,6 +335,10 @@ module sensor_i2c#(
if (i2c_enrun || mrst) sda_en_soft <= 0;
else if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SDA +:2]) sda_en_soft <= di[SENSI2C_CMD_SOFT_SDA +:2] != 3;
if (mrst) use_eof <= 0;
else if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && di[SENSI2C_CMD_USE_EOF + 1]) use_eof <= di[SENSI2C_CMD_USE_EOF];
if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SDA +:2]) sda_soft <= di[SENSI2C_CMD_SOFT_SDA + 1];
if (active_cmd) begin
......@@ -340,16 +351,18 @@ module sensor_i2c#(
// reset pointers in all 16 pages:
reset_on <= reset_cmd || (reset_on && !(wpage0_inc[0] && ( wpage0[3:0] == 4'hf)));
// request to clear pointer(s)? for one page - during reset or delayed frame sync (if previous was not finished)
req_clr <= frame_sync || (req_clr && !wpage0_inc[0]);
req_clr <= (use_eof ? eof_mclk : frame_sync) || (req_clr && !wpage0_inc[0]);
`ifndef I2C_FRAME_INDEPENDENT
sync_to_seq <= frame_sync || (reset_on && ( wpage0[3:0] == 4'hf));
sync_to_seq <= !use_eof && (frame_sync || (reset_on && ( wpage0[3:0] == 4'hf)));
sync_to_eof <= use_eof && (eof_mclk || (reset_on && ( wpage0[3:0] == 4'hf)));
`endif
if (reset_cmd) wpage0 <= 0;
else if (wpage0_inc[0]) wpage0 <= wpage0 + 1;
else if (sync_to_seq) wpage0 <= frame_num_seq;
if (reset_cmd) wpage0 <= 0;
else if (wpage0_inc[0]) wpage0 <= wpage0 + 1;
// else if (sync_to_seq || sync_to_eof) wpage0 <= sync_to_eof?(frame_num_seq-1):frame_num_seq;
else if (sync_to_seq || sync_to_eof) wpage0 <= frame_num_seq; // i2c frame is ahead of the frame sync one
if (reset_cmd) wpage_prev <= 4'hf;
else if (wpage0_inc[0]) wpage_prev <= wpage0;
......
sensor/sensor_i2c_io.v
View file @ 9145e396
......@@ -53,6 +53,7 @@ module sensor_i2c_io#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_USE_EOF = 8, // [9:8] - 0: advance sequencer at SOF, 1 - advance sequencer at EOF
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
......@@ -91,6 +92,7 @@ module sensor_i2c_io#(
output status_rq, // input request to send status downstream
input status_start,// Acknowledge of the first status packet byte (address)
input frame_sync, // increment/reset frame number
input eof_mclk, // End of frame for i2c sequencer (will not work for linescan mode: either disable or make division upsteram
input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer (to sync i2c)
inout scl,
inout sda
......@@ -116,6 +118,7 @@ module sensor_i2c_io#(
.SENSI2C_CMD_RESET (SENSI2C_CMD_RESET),
.SENSI2C_CMD_RUN (SENSI2C_CMD_RUN),
.SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS),
.SENSI2C_CMD_USE_EOF (SENSI2C_CMD_USE_EOF),
.SENSI2C_CMD_SOFT_SDA (SENSI2C_CMD_SOFT_SDA),
.SENSI2C_CMD_SOFT_SCL (SENSI2C_CMD_SOFT_SCL),
.SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD),
......@@ -144,7 +147,8 @@ module sensor_i2c_io#(
.status_rq (status_rq), // output
.status_start (status_start), // input
.frame_sync (frame_sync), // input
.frame_num_seq (frame_num_seq), // input[3:0]
.frame_num_seq (frame_num_seq), // input[3:0]
.eof_mclk (eof_mclk), // input
.scl_in (scl_in), // input
.sda_in (sda_in), // input
.scl_out (scl_out), // output
......
sensor/sensors393.v
View file @ 9145e396
......@@ -80,6 +80,7 @@ module sensors393 #(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_USE_EOF = 8, // [9:8] - 0: advance sequencer at SOF, 1 - advance sequencer at EOF
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
......@@ -508,6 +509,7 @@ module sensors393 #(
.SENSI2C_CMD_RESET (SENSI2C_CMD_RESET),
.SENSI2C_CMD_RUN (SENSI2C_CMD_RUN),
.SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS),
.SENSI2C_CMD_USE_EOF (SENSI2C_CMD_USE_EOF),
.SENSI2C_CMD_SOFT_SDA (SENSI2C_CMD_SOFT_SDA),
.SENSI2C_CMD_SOFT_SCL (SENSI2C_CMD_SOFT_SCL),
.SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD),
......
util_modules/pulse_cross_clock_orst.v 0 → 100644
View file @ 9145e396
/*!
* <b>Module:</b>pulse_cross_clock
* @file pulse_cross_clock_orst.v
* @date 2015-04-27
* @author Andrey Filippov
*
* @brief Propagate a single pulse through clock domain boundary
* For same frequencies input pulses can have 1:3 duty cycle EXTRA_DLY=0
* and 1:5 for EXTRA_DLY=1
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* pulse_cross_clock.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pulse_cross_clock.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module pulse_cross_clock_orst#(
parameter EXTRA_DLY=0 // for
)(
input rst,
input src_clk,
input orst, // output reset
input dst_clk,
input in_pulse, // single-cycle positive pulse
output out_pulse,
output busy
);
localparam EXTRA_DLY_SAFE=EXTRA_DLY ? 1 : 0;
`ifndef IGNORE_ATTR
(* KEEP = "TRUE" *)
`endif
reg in_reg = 0; // can not be ASYNC_REG as it can not be put together with out_reg
//WARNING: [Constraints 18-1079] Register sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_trig_in_pclk_i/in_reg_reg
// and sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_trig_in_pclk_i/out_reg_reg[0] are
//from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints
// or mismatched control signals on the registers.
`ifndef IGNORE_ATTR
(* ASYNC_REG = "TRUE" *)
`endif
reg [2:0] out_reg = 0;
`ifndef IGNORE_ATTR
(* ASYNC_REG = "TRUE" *)
`endif
reg busy_r = 0;
assign out_pulse=out_reg[2];
assign busy=busy_r; // in_reg;
always @(posedge src_clk or posedge rst) begin
if (rst) in_reg <= 0;
else in_reg <= in_pulse || (in_reg && !out_reg[EXTRA_DLY_SAFE]);
if (rst) busy_r <= 0;
else busy_r <= in_pulse || in_reg || (busy_r && (|out_reg[EXTRA_DLY_SAFE:0]));
end
// always @(posedge dst_clk or posedge rst) begin
always @(posedge dst_clk) begin
if (orst) out_reg <= 3'b0;
else out_reg <= {out_reg[0] & ~out_reg[1],out_reg[0],in_reg};
end
endmodule
x393_parallel.bit
View file @ 9145e396
No preview for this file type
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment