Commit cf5bee66 authored by Andrey Filippov's avatar Andrey Filippov

disabling SoF for disabled channels

parent 7445f6aa
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sat Oct 29 21:44:32 2016
[*] Mon Nov 7 00:04:33 2016
[*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161028224636205.fst"
[dumpfile_mtime] "Sat Oct 29 06:54:57 2016"
[dumpfile_size] 487758287
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161106163115099.fst"
[dumpfile_mtime] "Mon Nov 7 00:03:53 2016"
[dumpfile_size] 125174737
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav"
[timestart] 0
[size] 1814 1171
[pos] 0 0
*-25.418884 64300000 53094051 136169617 426878253 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-25.890059 103100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.simul_sensor12bits_2_i.
[treeopen] x393_dut.simul_sensor12bits_3_i.
......@@ -31,13 +31,14 @@
[treeopen] x393_dut.x393_i.sensors393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_parallel12_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
......@@ -45,7 +46,7 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.timing393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[sst_width] 307
[sst_width] 440
[signals_width] 319
[sst_expanded] 1
[sst_vpaned_height] 486
......@@ -775,13 +776,13 @@ x393_dut.x393_i.axiwr_wen
x393_dut.x393_i.axiwr_wdata[31:0]
@1401200
- cmd
@800200
@c00200
-i2c
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.rpointer[5:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wpage0[3:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.page_r[3:0]
@1000200
@1401200
-i2c
@c00200
-gpio
......@@ -1842,7 +1843,7 @@ x393_dut.IMU_SDA
x393_dut.IMU_TAPS[5:1]
@1401200
-IMU_
@800200
@c00200
-camsync_ext_int
@800022
x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
......@@ -1930,7 +1931,7 @@ x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
-group_end
-group_end
-group_end
@1000200
@1401200
-camsync_ext_int
@800200
-sequencers_0
......@@ -1955,7 +1956,6 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sync_to_seq
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sync_to_eof
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_num_seq[3:0]
......@@ -1967,14 +1967,72 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c
-i2c_seq_0
@800200
-sensor_channel0
@200
-
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_out_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof_out_r
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.en_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hact
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.frame_num_seq[3:0]
@800200
-sesns_sync
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_late
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_out_pclk
@200
-
@1000200
-sesns_sync
-sensor_channel0
-sequencers_0
@800200
-sensor_channel_a
@28
x393_dut.simul_sensor12bits_2_i.MRST
x393_dut.simul_sensor12bits_2_i.HACT
x393_dut.simul_sensor12bits_2_i.VACT
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sof_out_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.en_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.en_pclk
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.frame_num_seq[3:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.sof_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.sof_out_pclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.sof_late
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.frame_num_seq[3:0]
@200
-chn2
@28
x393_dut.simul_sensor12bits_3_i.MRST
x393_dut.simul_sensor12bits_3_i.HACT
x393_dut.simul_sensor12bits_3_i.VACT
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.en_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.en_pclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sof_out_mclk
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.eof_mclk
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.frame_num_seq[3:0]
@800200
-sens_sync2
@200
-
@1000200
-sens_sync2
-sensor_channel_a
@800022
x393_dut.x393_i.sof_out_mclk[3:0]
@28
(0)x393_dut.x393_i.sof_out_mclk[3:0]
(1)x393_dut.x393_i.sof_out_mclk[3:0]
(2)x393_dut.x393_i.sof_out_mclk[3:0]
(3)x393_dut.x393_i.sof_out_mclk[3:0]
@1001200
-group_end
[pattern_trace] 1
[pattern_trace] 0
......@@ -1613,7 +1613,7 @@ simul_axi_hp_wr #(
.new_bayer (0) //SENSOR12BITS_NEW_BAYER) was 1
) simul_sensor12bits_2_i (
.MCLK (PX2_MCLK), // input
.MRST (PX2_MRST), // input
.MRST (PX2_MRST & 0), // input // force reset !!!
.ARO (PX2_ARO), // input
.ARST (PX2_ARST), // input
.OE (1'b0), // input output enable active low
......
......@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300c6; //parallel - same -0.132 /31, 80.73%
parameter FPGA_VERSION = 32'h039300c7; //parallel - disable SoF when channel disabled
// parameter FPGA_VERSION = 32'h039300c6; //parallel - same -0.132 /31, 80.73%
// parameter FPGA_VERSION = 32'h039300c5; //parallel - made i2c ahead of system frame number for eof -0.027/12 , 82.08%
// parameter FPGA_VERSION = 32'h039300c4; //parallel - option to use EOF for i2c sequencer timing met, 79.66%
// parameter FPGA_VERSION = 32'h039300c3; //parallel - fixing timestamps -0.209/47, 79.86%
......
......@@ -2166,6 +2166,7 @@ measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 1 # enable software gpio pins and porta (camsync)
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
......@@ -2290,6 +2291,12 @@ set_gpio_pins 0 1 # pin 0 low, pin 1 - high
set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
write_control_register 0x480 0x400 # disable sensor chn 2
reset_camsync_inout 1 # reset all outputs
set_camsync_period 31 # set bit duration
set_camsync_period 8000 # 80 usec
......
......@@ -98,7 +98,7 @@ module sens_sync#(
reg trig_r;
reg [SENS_SYNC_MINBITS-1:0] period_cntr;
reg period_dly; // runnning counter to enforce > min period
reg en_pclk;
assign set_data_mclk = cmd_we && ((cmd_a == SENS_SYNC_MULT) || (cmd_a == SENS_SYNC_LATE));
assign zero_frames_left = !(|sub_frames_left);
assign hact_single = hact && !hact_r;
......@@ -113,6 +113,9 @@ module sens_sync#(
end
always @ (posedge pclk) begin
en_pclk <= en;
if (set_data_pclk && (cmd_a_r == SENS_SYNC_MULT))
sub_frames_pclk <= cmd_data_r[SENS_SYNC_FBITS-1:0];
......@@ -186,7 +189,7 @@ module sens_sync#(
);
pulse_cross_clock pulse_cross_clock_trig_in_pclk_i (
.rst (mrst), // input
.rst (!en), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (trig_in), // input
......@@ -195,17 +198,19 @@ module sens_sync#(
);
// pclk -> mclk
pulse_cross_clock pulse_cross_clock_sof_out_i (
.rst (prst), // input
pulse_cross_clock_orst pulse_cross_clock_sof_out_i (
.rst (!en_pclk), // input
.src_clk (pclk), // input
.orst (!en), // input // should work even if pclk is not running
.dst_clk (mclk), // input
.in_pulse (pre_sof_out), // input
.out_pulse (sof_out), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_sof_late_i (
.rst (prst), // input
pulse_cross_clock_orst pulse_cross_clock_sof_late_i (
.rst (!en_pclk), // input
.src_clk (pclk), // input
.orst (!en), // input // should work even if pclk is not running
.dst_clk (mclk), // input
.in_pulse (pre_sof_late), // input
.out_pulse (sof_late), // output
......@@ -213,4 +218,3 @@ module sens_sync#(
);
endmodule
/*!
* <b>Module:</b>pulse_cross_clock
* @file pulse_cross_clock_orst.v
* @date 2015-04-27
* @author Andrey Filippov
*
* @brief Propagate a single pulse through clock domain boundary
* For same frequencies input pulses can have 1:3 duty cycle EXTRA_DLY=0
* and 1:5 for EXTRA_DLY=1
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* pulse_cross_clock.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pulse_cross_clock.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module pulse_cross_clock_orst#(
parameter EXTRA_DLY=0 // for
)(
input rst,
input src_clk,
input orst, // output reset
input dst_clk,
input in_pulse, // single-cycle positive pulse
output out_pulse,
output busy
);
localparam EXTRA_DLY_SAFE=EXTRA_DLY ? 1 : 0;
`ifndef IGNORE_ATTR
(* KEEP = "TRUE" *)
`endif
reg in_reg = 0; // can not be ASYNC_REG as it can not be put together with out_reg
//WARNING: [Constraints 18-1079] Register sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_trig_in_pclk_i/in_reg_reg
// and sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_trig_in_pclk_i/out_reg_reg[0] are
//from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints
// or mismatched control signals on the registers.
`ifndef IGNORE_ATTR
(* ASYNC_REG = "TRUE" *)
`endif
reg [2:0] out_reg = 0;
`ifndef IGNORE_ATTR
(* ASYNC_REG = "TRUE" *)
`endif
reg busy_r = 0;
assign out_pulse=out_reg[2];
assign busy=busy_r; // in_reg;
always @(posedge src_clk or posedge rst) begin
if (rst) in_reg <= 0;
else in_reg <= in_pulse || (in_reg && !out_reg[EXTRA_DLY_SAFE]);
if (rst) busy_r <= 0;
else busy_r <= in_pulse || in_reg || (busy_r && (|out_reg[EXTRA_DLY_SAFE:0]));
end
// always @(posedge dst_clk or posedge rst) begin
always @(posedge dst_clk) begin
if (orst) out_reg <= 3'b0;
else out_reg <= {out_reg[0] & ~out_reg[1],out_reg[0],in_reg};
end
endmodule
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