merged with framepars, fixing internal/external timestamps (b02bac09) · Commits · Elphel / x393

cocotb/x393_cocotb_03.sav

+176 −19

Original line number	Diff line number	Diff line
		[*]
		[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
		[*] Mon Oct 24 00:30:16 2016
		[*] Thu Oct 27 01:40:51 2016
		[*]
		[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161023171014405.fst"
		[dumpfile_mtime] "Mon Oct 24 00:23:04 2016"
		[dumpfile_size] 364619214
		[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161026180017757.fst"
		[dumpfile_mtime] "Thu Oct 27 01:39:08 2016"
		[dumpfile_size] 418439836
		[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav"
		[timestart] 0
		[size] 1814 1171
		[pos] 0 0
		*-26.593010 46043333 53094051 136169617 216213845 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
		*-27.006804 350100000 53094051 136169617 216213845 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
		[treeopen] x393_dut.
		[treeopen] x393_dut.simul_sensor12bits_2_i.
		[treeopen] x393_dut.simul_sensor12bits_3_i.
		@@ -25,7 +25,6 @@
		[treeopen] x393_dut.x393_i.event_logger_i.i_logger_arbiter.
		[treeopen] x393_dut.x393_i.event_logger_i.i_nmea_decoder.
		[treeopen] x393_dut.x393_i.event_logger_i.i_rs232_rcv.
		[treeopen] x393_dut.x393_i.mult_saxi_wr_i.
		[treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
		@@ -40,9 +39,10 @@
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
		[treeopen] x393_dut.x393_i.timing393_i.
		[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
		[sst_width] 398
		[signals_width] 323
		[sst_width] 282
		[signals_width] 319
		[sst_expanded] 1
		[sst_vpaned_height] 486
		@820
		@@ -814,8 +814,18 @@ x393_dut.x393_i.gpio393_i.ext_pins[9:0]
		-group_end
		@1401200
		-gpio
		@800200
		@c00200
		-event_logger
		@22
		x393_dut.x393_i.event_logger_i.config_gps[3:0]
		@28
		x393_dut.x393_i.event_logger_i.gps_pulse1sec
		x393_dut.x393_i.event_logger_i.gps_ts_stb
		x393_dut.x393_i.event_logger_i.nmea_sent_start
		(2)x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
		x393_dut.x393_i.event_logger_i.gps_pulse1sec_single
		x393_dut.x393_i.event_logger_i.mclk
		x393_dut.x393_i.event_logger_i.mrst
		@200
		-x393
		@800022
		@@ -977,7 +987,7 @@ x393_dut.x393_i.event_logger_i.i_imu_spi.mclk
		@1401200
		-imu_spi393
		-group_end
		@c00200
		@800200
		-rs232_rcvr
		@28
		x393_dut.x393_i.axi_aclk
		@@ -1107,9 +1117,9 @@ x393_dut.x393_i.event_logger_i.i_rs232_rcv.restart[1:0]
		x393_dut.x393_i.event_logger_i.i_rs232_rcv.reset_bit_duration
		@22
		x393_dut.x393_i.event_logger_i.i_rs232_rcv.bitHalfPeriod[15:0]
		@1401200
		@1000200
		-rs232_rcvr
		@c00200
		@800200
		-nmea_decoder
		@28
		x393_dut.x393_i.event_logger_i.i_nmea_decoder.start
		@@ -1220,7 +1230,7 @@ x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_count[6:0]
		-group_end
		@22
		x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble[3:0]
		@1401200
		@1000200
		-nmea_decoder
		@c00200
		-imu_exttime
		@@ -1404,6 +1414,7 @@ x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.dout[7:0]
		-imu_exttime
		@c00200
		-imu_spi
		@800200
		-external
		@28
		x393_dut.IMU_CS
		@@ -1418,14 +1429,67 @@ x393_dut.IMU_SCLK_OUT
		@28
		(6)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
		(7)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
		@1401200
		@1000200
		-external
		@28
		x393_dut.x393_i.event_logger_i.i_imu_spi.xclk
		@c00022
		x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		@28
		(0)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(1)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(2)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(3)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(4)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(5)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(6)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(7)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(8)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(9)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(10)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(11)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(12)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(13)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(14)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		(15)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		@1401200
		-group_end
		@28
		(0)x393_dut.x393_i.event_logger_i.i_imu_spi.mosi_reg[15:0]
		@200
		-
		@28
		x393_dut.x393_i.event_logger_i.i_imu_spi.end_prepare
		@800028
		x393_dut.x393_i.event_logger_i.i_imu_spi.sngl_wire_stb[2:0]
		@28
		(0)x393_dut.x393_i.event_logger_i.i_imu_spi.sngl_wire_stb[2:0]
		(1)x393_dut.x393_i.event_logger_i.i_imu_spi.sngl_wire_stb[2:0]
		(2)x393_dut.x393_i.event_logger_i.i_imu_spi.sngl_wire_stb[2:0]
		@1001200
		-group_end
		@800028
		x393_dut.x393_i.event_logger_i.i_imu_spi.sngl_wire_r[1:0]
		@28
		(0)x393_dut.x393_i.event_logger_i.i_imu_spi.sngl_wire_r[1:0]
		(1)x393_dut.x393_i.event_logger_i.i_imu_spi.sngl_wire_r[1:0]
		@1001200
		-group_end
		@28
		x393_dut.x393_i.event_logger_i.i_imu_spi.mosi
		x393_dut.x393_i.event_logger_i.i_imu_spi.miso
		x393_dut.x393_i.event_logger_i.i_imu_spi.sda
		x393_dut.x393_i.event_logger_i.i_imu_spi.sda_en
		x393_dut.x393_i.event_logger_i.i_imu_spi.pre_scl
		x393_dut.x393_i.event_logger_i.i_imu_spi.scl
		@c00028
		x393_dut.x393_i.event_logger_i.i_imu_spi.scl_r[1:0]
		@28
		(0)x393_dut.x393_i.event_logger_i.i_imu_spi.scl_r[1:0]
		(1)x393_dut.x393_i.event_logger_i.i_imu_spi.scl_r[1:0]
		@1401200
		-group_end
		@28
		x393_dut.x393_i.event_logger_i.i_imu_spi.scl_en
		x393_dut.x393_i.event_logger_i.i_imu_spi.ts
		x393_dut.x393_i.event_logger_i.i_imu_spi.rdy
		@@ -1435,6 +1499,7 @@ x393_dut.x393_i.event_logger_i.i_imu_spi.raddr[4:0]
		x393_dut.x393_i.event_logger_i.i_imu_spi.rdata[15:0]
		@28
		x393_dut.x393_i.event_logger_i.i_imu_spi.stall
		x393_dut.x393_i.event_logger_i.i_imu_spi.set_stall
		@1401200
		-imu_spi
		@c00200
		@@ -1627,9 +1692,8 @@ x393_dut.x393_i.logger_out[15:0]
		x393_dut.x393_i.logger_stb
		@1401200
		-x393
		@1000200
		-event_logger
		@800200
		@c00200
		-mult_saxi_wr_inbuf
		@28
		x393_dut.x393_i.mult_saxi_wr_inbuf_i.mclk
		@@ -1642,9 +1706,9 @@ x393_dut.x393_i.mult_saxi_wr_inbuf_i.has_burst
		x393_dut.x393_i.mult_saxi_wr_inbuf_i.read_burst
		@22
		x393_dut.x393_i.mult_saxi_wr_inbuf_i.data_out[31:0]
		@1000200
		@1401200
		-mult_saxi_wr_inbuf
		@800200
		@c00200
		-mult_saxi_wr
		@22
		x393_dut.x393_i.mult_saxi_wr_i.cmd_ad[7:0]
		@@ -1734,7 +1798,7 @@ x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.sa_len_wa[2:0]
		x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.sa_len_di[29:0]
		@28
		x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.sa_len_ra[2:0]
		@23
		@22
		x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.sa_len_ram_out[29:0]
		@28
		x393_dut.x393_i.mult_saxi_wr_i.mrst
		@@ -1743,6 +1807,7 @@ x393_dut.x393_i.mult_saxi_wr_i.arst
		-
		@1000200
		-mult_saxi_wr_pointers
		@1401200
		-mult_saxi_wr
		@c00200
		-IMU_
		@@ -1773,5 +1838,97 @@ x393_dut.IMU_SDA
		x393_dut.IMU_TAPS[5:1]
		@1401200
		-IMU_
		@800200
		-camsync_ext_int
		@800022
		x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		@28
		(0)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		(1)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		(2)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		(3)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		(4)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		(5)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		(6)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		(7)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		(8)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		(9)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
		@1001200
		-group_end
		@c00022
		x393_dut.x393_i.timing393_i.frame_sync[3:0]
		@28
		(0)x393_dut.x393_i.timing393_i.frame_sync[3:0]
		(1)x393_dut.x393_i.timing393_i.frame_sync[3:0]
		(2)x393_dut.x393_i.timing393_i.frame_sync[3:0]
		(3)x393_dut.x393_i.timing393_i.frame_sync[3:0]
		@1401200
		-group_end
		@22
		x393_dut.x393_i.timing393_i.camsync393_i.cmd_a[2:0]
		@28
		x393_dut.x393_i.timing393_i.camsync393_i.cmd_we
		x393_dut.x393_i.timing393_i.camsync393_i.set_trig_dst_w
		x393_dut.x393_i.timing393_i.camsync393_i.en
		x393_dut.x393_i.timing393_i.camsync393_i.pclk
		@8022
		x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
		@800028
		x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr_run[1:0]
		@28
		(0)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr_run[1:0]
		(1)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr_run[1:0]
		x393_dut.x393_i.timing393_i.camsync393_i.start_en
		@800028
		x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
		@28
		(0)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
		(1)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
		(2)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
		@22
		x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en_r[9:0]
		@28
		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_mode_mclk
		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_mode_pclk
		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_trigger_condition
		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_trigger_condition_d
		@22
		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_trigger_filter_cntr[6:0]
		@28
		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_trigger_condition_filtered
		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_pre_pause
		@800028
		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]
		@28
		(0)x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]
		(1)x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]
		x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition
		x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_filtered
		@22
		x393_dut.x393_i.timing393_i.camsync393_i.input_pattern[9:0]
		@c00023
		x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		@29
		(0)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		(1)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		(2)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		(3)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		(4)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		(5)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		(6)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		(7)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		(8)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		(9)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
		@1401201
		-group_end
		@1001200
		-group_end
		-group_end
		-group_end
		@200
		-
		@1000200
		-camsync_ext_int
		[pattern_trace] 1
		[pattern_trace] 0

cocotb/x393_dut.v

+40 −3

Original line number	Diff line number	Diff line
		@@ -1762,8 +1762,12 @@ simul_axi_hp_wr #(
		assign x393_i.ps7_i.FCLKCLK= {4{CLK}};
		assign x393_i.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};

		`define TEST_IMU




		`define TEST_IMU
		`define TEST_EXT_INT
		assign #10 gpio_pins[7] = gpio_pins[8];
		`ifndef TEST_IMU
		assign #10 gpio_pins[9] = gpio_pins[6];
		@@ -1798,7 +1802,7 @@ assign #10 gpio_pins[7] = gpio_pins[8];
		//reg TEST_CPU_RD_OK;
		reg SERIAL_BIT = 1'b1;
		reg GPS1SEC = 1'b0;
		reg ODOMETER_PULSE= 1'b0;
		reg ODOMETER_PULSE= 1'b1;
		integer SERIAL_DATA_FD; // @SuppressThisWarning VEditor
		reg IMU_DATA_READY;

		@@ -1820,6 +1824,33 @@ assign #10 gpio_pins[7] = gpio_pins[8];
		reg RS232_SENDING_BYTE; // @SuppressThisWarning VEditor just for simulation
		reg RS232_SENDING_PAUSE; // @SuppressThisWarning VEditor just for simulation
		`endif
		`ifdef TEST_EXT_INT
		initial begin
		#350000;
		ODOMETER_PULSE=1'b0; // first pulse will be missed
		#5000;
		ODOMETER_PULSE=1'b1;
		#50000;
		ODOMETER_PULSE=1'b0;
		#5000;
		ODOMETER_PULSE=1'b1;
		#50000;
		ODOMETER_PULSE=1'b0;
		#5000;
		ODOMETER_PULSE=1'b1;
		/*
		#100000;
		ODOMETER_PULSE=1'b0;
		#5000;
		ODOMETER_PULSE=1'b1;
		#100000;
		ODOMETER_PULSE=1'b0;
		#5000;
		ODOMETER_PULSE=1'b1;
		*/
		end
		`endif



		`ifdef TEST_IMU
		@@ -1839,10 +1870,16 @@ assign #10 gpio_pins[7] = gpio_pins[8];
		send_serial_bit('h0a);
		send_serial_pause;
		send_serial_pause;

		`ifndef TEST_EXT_INT
		ODOMETER_PULSE=1'b1;
		`endif
		send_serial_pause;

		`ifndef TEST_EXT_INT
		ODOMETER_PULSE=1'b0;
		// repeat (20) send_serial_pause;
		`endif

		end
		end
		`endif

fpga_version.vh

+4 −2

Original line number	Diff line number	Diff line
		@@ -35,7 +35,9 @@
		* contains all the components and scripts required to completely simulate it
		* with at least one of the Free Software programs.
		*/
		parameter FPGA_VERSION = 32'h039300c1; //parallel - modified after troubleshooting simulation -0.069/41, 79.90 %
		parameter FPGA_VERSION = 32'h039300c3; //parallel - fixing timestamps
		// parameter FPGA_VERSION = 32'h039300c2; //parallel - external sync for Eyesis -0.160/71 79.84%
		// parameter FPGA_VERSION = 32'h039300c1; //parallel - modified after troubleshooting simulation -0.069/41, 79.90 %
		// parameter FPGA_VERSION = 32'h039300c0; //parallel - changing LOGGER_PAGE_IMU 3->0 (how it was in 353) -0.044/16, 79.59%
		// parameter FPGA_VERSION = 32'h039300bf; //parallel - mask extrenal timestamps mode -0.043/17 79.56%
		// parameter FPGA_VERSION = 32'h039300be; //parallel - adding odd/even pixels shift -0.066/12, 80.26%

includes/x393_parameters.vh

+6 −0

Original line number	Diff line number	Diff line
		@@ -797,6 +797,12 @@
		parameter CAMSYNC_PRE_MAGIC = 6'b110100,
		parameter CAMSYNC_POST_MAGIC = 6'b001101,

		// GPIO bits used for camera synchronization
		parameter CAMSYNC_GPIO_EXT_IN = 9,
		parameter CAMSYNC_GPIO_INT_IN = 7,
		parameter CAMSYNC_GPIO_EXT_OUT = 6,
		parameter CAMSYNC_GPIO_INT_OUT = 8,

		parameter RTC_MHZ= 25, // RTC input clock in MHz (should be interger number)
		parameter RTC_BITC_PREDIV = 5, // number of bits to generate 2 MHz pulses counting refclk
		parameter RTC_SET_USEC= 0, // 20-bit number of microseconds

py393/x393_jpeg.py

+117 −0

Original line number	Diff line number	Diff line
		@@ -2273,6 +2273,123 @@ jpeg_sim_multi 8





		################## Simulate Parallel 12 - external trigger ####################
		./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
		measure_all "*DI"
		setup_all_sensors True None 0xf
		set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
		#just testing
		set_gpio_ports 1 1 # enable software gpio pins and porta (camsync)
		set_gpio_pins 0 1 # pin 0 low, pin 1 - high

		set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"

		reset_camsync_inout 1 # reset all outputs
		set_camsync_period 31 # set bit duration
		set_camsync_period 8000 # 80 usec
		set_camsync_delay 0 400
		set_camsync_delay 1 100
		set_camsync_delay 2 200
		set_camsync_delay 3 300
		#set_camsync_inout <is_out> <bit_number> <active_positive>
		set_camsync_inout 1 8 0
		set_camsync_inout 0 7 0
		#reset_camsync_inout 0 # start with internal trigger


		#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
		set_camsync_mode 1 1 1 1 0 0xf




		set_sensor_histogram_window 0 0 4 4 25 21
		set_sensor_histogram_window 1 0 4 4 41 21
		set_sensor_histogram_window 2 0 4 4 25 41
		set_sensor_histogram_window 3 0 4 4 41 41




		r
		read_control_register 0x430
		read_control_register 0x431
		write_cmd_frame_sequencer 0 1 2 0x600 0x48 # compressor q page = 1 // too late for frame 2
		set_qtables 0 0 80
		set_qtables 0 1 70

		#irq coming, image not changing - yes
		write_cmd_frame_sequencer 0 1 1 0x686 0x280005 #save 4 more lines than sensor has
		write_cmd_frame_sequencer 0 1 1 0x680 0x5507 #enable abort
		#write_cmd_frame_sequencer 0 1 1 0x6c6 0x300006 #save 4 more lines that compressor has

		write_cmd_frame_sequencer 0 1 2 0x600 0x5 #stop compressor `
		write_cmd_frame_sequencer 0 1 2 0x680 0x5405 # stop sensor memory (+0) // sensor memory should be controlled first, (9 commands
		write_cmd_frame_sequencer 0 1 2 0x6c0 0x5c49 # stop compressor memory (+0)

		write_cmd_frame_sequencer 0 1 3 0x686 0x240005 # correct lines
		write_cmd_frame_sequencer 0 1 3 0x680 0x5507 # run sensor memory (+1) Can not be 0

		write_cmd_frame_sequencer 0 1 4 0x686 0x280005 #save 4 more lines than sensor has
		write_cmd_frame_sequencer 0 1 4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)
		write_cmd_frame_sequencer 0 1 4 0x6c0 0x7d4b # run compressor memory (+2)
		write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (+0)

		write_cmd_frame_sequencer 0 1 1 0x600 0x48 # compressor q page = 1
		write_cmd_frame_sequencer 0 1 4 0x600 0x40 # compressor q page = 0

		read_control_register 0x431
		read_control_register 0x430

		#testing histograms
		write_control_register 0x409 0xc0

		#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
		#set_sensor_io_ctl all None None None None None 1 None # load all delays?
		compressor_control all None None None None None 2
		compressor_interrupt_control all clr
		compressor_interrupt_control all en
		compressor_control all 3
		r
		read_status 0x21
		r
		jpeg_sim_multi 4
		r
		read_status 0x21
		r
		jpeg_sim_multi 3
		r
		read_status 0x21
		r

		write_cmd_frame_sequencer 0 1 1 0x686 0x240005 # correct lines
		write_cmd_frame_sequencer 0 1 1 0x6c6 0x200006 # correct lines
		write_cmd_frame_sequencer 0 1 1 0x680 0x5507 # run sensor memory, update frame#, reset buffers
		write_cmd_frame_sequencer 0 1 1 0x6c0 0x7d4b # run compressor memory
		write_cmd_frame_sequencer 0 1 1 0x600 0x7 # run compressor

		#switch to external (wired) trigger

		jpeg_sim_multi 4

		set_camsync_inout 0 9 0 # external/internal trigger mode


		###switch to external (wired) trigger
		##set_camsync_inout 0 7 0

		jpeg_sim_multi 4
		#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
		jpeg_sim_multi 8

		set_camsync_period 8000 # 80 usec - restart while waiting for external trigger
		jpeg_sim_multi 4

		jpeg_sim_multi 4


		################## Serial ####################
		cd /usr/local/verilog/; test_mcntrl.py @hargs
		bitstream_set_path /usr/local/verilog/x393_hispi.bit

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