Commit 69ef600d authored by Andrey Filippov's avatar Andrey Filippov

merged with framepars - code for dct-iv

parents 26dad413 a409d2b4
...@@ -16,6 +16,7 @@ x393.prj ...@@ -16,6 +16,7 @@ x393.prj
*.old *.old
*.new *.new
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*.pyc *.pyc
*.pickle *.pickle
*.tmp *.tmp
......
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FPGA_project_@_DUTTopModule=x393_dut FPGA_project_@_DUTTopModule=x393_dut
FPGA_project_@_ImplementationTopFile=x393.v FPGA_project_@_ImplementationTopFile=x393.v
FPGA_project_@_SimulationTopFile=x393_testbench03.tf FPGA_project_@_SimulationTopFile=dsp/dct_tests_01.tf
FPGA_project_@_SimulationTopModule=x393_testbench03 FPGA_project_@_SimulationTopModule=dct_tests_01
FPGA_project_@_part=xc7z030fbg484-1 FPGA_project_@_part=xc7z030fbg484-1
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......
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......
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[pattern_trace] 1
[pattern_trace] 0
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...@@ -224,7 +224,7 @@ module dsp_ma_preadd #( ...@@ -224,7 +224,7 @@ module dsp_ma_preadd #(
en_d_r <= en_d; en_d_r <= en_d;
sub_a_r <= sub_a; sub_a_r <= sub_a;
m_reg <= {{P_WIDTH - A_WIDTH - B_WIDTH{1'b0}}, m_wire}; m_reg <= {{P_WIDTH - A_WIDTH - B_WIDTH{m_wire[A_WIDTH+B_WIDTH-1]}}, m_wire};
p_reg <= p_reg_cond + m_reg_pm; p_reg <= p_reg_cond + m_reg_pm;
......
This diff is collapsed.
...@@ -2563,6 +2563,10 @@ set_camsync_inout 0 7 0 ...@@ -2563,6 +2563,10 @@ set_camsync_inout 0 7 0
#reset_camsync_inout 0 # start with internal trigger #reset_camsync_inout 0 # start with internal trigger
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None> #set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
set_camsync_mode 1 1 1 1 0 0xf set_camsync_mode 1 1 1 1 0 0xf
set_camsync_period 10000 # 100 usec # and start set_camsync_period 10000 # 100 usec # and start
...@@ -2621,6 +2625,7 @@ r ...@@ -2621,6 +2625,7 @@ r
read_status 0x21 read_status 0x21
r r
jpeg_sim_multi 4 jpeg_sim_multi 4
r r
read_status 0x21 read_status 0x21
r r
......
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