Commit 69ef600d authored by Andrey Filippov's avatar Andrey Filippov
Browse files

merged with framepars - code for dct-iv

parents 26dad413 a409d2b4

.gitignore

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@@ -16,6 +16,7 @@ x393.prj 
*.old

*.old

*.new

*.new

*.bad

*.bad

*.bak

*.pyc

*.pyc

*.pickle

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.settings/com.elphel.vdt.FPGA_project.prefs

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FPGA_project_@_DUTTopFile=cocotb/x393_dut.v

FPGA_project_@_DUTTopFile=cocotb/x393_dut.v

FPGA_project_@_DUTTopModule=x393_dut

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FPGA_project_@_SimulationTopFile=x393_testbench03.tf

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FPGA_project_@_part=xc7z030fbg484-1

FPGA_project_@_part=xc7z030fbg484-1

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com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->

com.elphel.store.version.FPGA_project=1.0

com.elphel.store.version.FPGA_project=1.0

.settings/com.elphel.vdt.iverilog.prefs

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com.elphel.store.context.iverilog=iverilog_@_ShowWarnings<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->

com.elphel.store.version.iverilog=1.1

com.elphel.store.version.iverilog=1.1

eclipse.preferences.version=1

eclipse.preferences.version=1

iverilog_@_ExtraFiles=glbl.v<-@\#\#@->

iverilog_@_ExtraFiles=glbl.v<-@\#\#@->

iverilog_@_GTKWaveSavFile=x393_testbench04.sav

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iverilog_@_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->

iverilog_@_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->

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iverilog_@_SaveLogsPreprocessor=false

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dct_tests_01.sav

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