Commit 500cf616 authored by Andrey Filippov's avatar Andrey Filippov

fixed axi simulation modules, added IRQ support

parent ea63654a
...@@ -62,52 +62,52 @@ ...@@ -62,52 +62,52 @@
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...@@ -127,7 +127,7 @@ ...@@ -127,7 +127,7 @@
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...@@ -67,7 +67,6 @@ module cmprs_afi_mux_ptr_wresp( ...@@ -67,7 +67,6 @@ module cmprs_afi_mux_ptr_wresp(
reg [26:0] len_ram[0:3]; // start chunk/num cunks in a buffer (write port @mclk) reg [26:0] len_ram[0:3]; // start chunk/num cunks in a buffer (write port @mclk)
reg [26:0] chunk_ptr_inc; // incremented by 1..4 chunk pointer reg [26:0] chunk_ptr_inc; // incremented by 1..4 chunk pointer
reg [27:0] chunk_ptr_rovr; // incremented chunk pointer, decremented by length (MSB - sign) reg [27:0] chunk_ptr_rovr; // incremented chunk pointer, decremented by length (MSB - sign)
/// reg [ 3:0] busy; // one-hot busy stages (usually end with [3]
reg [ 4:0] busy; // one-hot busy stages (usually end with [4] reg [ 4:0] busy; // one-hot busy stages (usually end with [4]
reg [ 4:0] id_r; // registered ID data - MSB is unused reg [ 4:0] id_r; // registered ID data - MSB is unused
...@@ -88,14 +87,9 @@ module cmprs_afi_mux_ptr_wresp( ...@@ -88,14 +87,9 @@ module cmprs_afi_mux_ptr_wresp(
assign ptr_wa = {eof,chn}; // valid @busy[2] assign ptr_wa = {eof,chn}; // valid @busy[2]
assign afi_bready = afi_bready_r; assign afi_bready = afi_bready_r;
/// assign pre_we= resetting[0] || // a pair of cycles to reset chunk pointer and frame chunk pointer
/// busy[2] || // always update chunk pointer
/// (busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
assign pre_we= resetting[0] || // a pair of cycles to reset chunk pointer and frame chunk pointer assign pre_we= resetting[0] || // a pair of cycles to reset chunk pointer and frame chunk pointer
busy[3] || // always update chunk pointer busy[3] || // always update chunk pointer
(busy[4] && last_burst_in_frame); // optionally update frame chunk pointer (same value) (busy[4] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
/// assign pre_busy= afi_bvalid_r && en && !(|busy[1:0]) && !pre_we;
/// assign start_resetting_w = !afi_bvalid_r && en && !(|busy[1:0]) && !pre_we && (|reset_rq);
assign pre_busy= afi_bvalid_r && en && !(|busy[2:0]) && !pre_we; assign pre_busy= afi_bvalid_r && en && !(|busy[2:0]) && !pre_we;
assign start_resetting_w = !afi_bvalid_r && en && !(|busy[2:0]) && !pre_we && (|reset_rq); assign start_resetting_w = !afi_bvalid_r && en && !(|busy[2:0]) && !pre_we && (|reset_rq);
...@@ -108,11 +102,10 @@ module cmprs_afi_mux_ptr_wresp( ...@@ -108,11 +102,10 @@ module cmprs_afi_mux_ptr_wresp(
afi_bvalid_r <= afi_bvalid; afi_bvalid_r <= afi_bvalid;
afi_bready_r <= !en || pre_busy; // (!busy[0] && !pre_busy && !resetting[0] && !start_resetting_w); afi_bready_r <= !en || pre_busy; // (!busy[0] && !pre_busy && !resetting[0] && !start_resetting_w);
// busy <= {busy[2:0], pre_busy}; // adjust bits
busy <= {busy[3:0], pre_busy}; // adjust bits busy <= {busy[3:0], pre_busy}; // adjust bits
// id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved // if (afi_bready && afi_bvalid) id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
if (afi_bready && afi_bvalid) id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved if (afi_bvalid && pre_busy) id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
if (start_resetting_w) reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]), if (start_resetting_w) reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),
reset_rq[2] & ~(|reset_rq[1:0]), reset_rq[2] & ~(|reset_rq[1:0]),
...@@ -126,10 +119,8 @@ module cmprs_afi_mux_ptr_wresp( ...@@ -126,10 +119,8 @@ module cmprs_afi_mux_ptr_wresp(
else resetting <= {resetting[0], start_resetting_w | (resetting[0] & ~resetting[1])}; else resetting <= {resetting[0], start_resetting_w | (resetting[0] & ~resetting[1])};
if (resetting == 2'b01) chn <= reset_rq_enc; if (resetting == 2'b01) chn <= reset_rq_enc;
/// else if (busy[0]) chn <= id_r[0 +: 2];
else if (busy[1]) chn <= id_r[0 +: 2]; else if (busy[1]) chn <= id_r[0 +: 2];
/// if (busy[0]) begin // first busy cycle
if (busy[1]) begin // first busy cycle if (busy[1]) begin // first busy cycle
last_burst_in_frame <= id_r[2]; last_burst_in_frame <= id_r[2];
chunk_inc <= {1'b0,id_r[3 +:2]} + 1; chunk_inc <= {1'b0,id_r[3 +:2]} + 1;
...@@ -140,9 +131,6 @@ module cmprs_afi_mux_ptr_wresp( ...@@ -140,9 +131,6 @@ module cmprs_afi_mux_ptr_wresp(
if ((resetting == 2'b01) || busy[0]) eof <= 0; if ((resetting == 2'b01) || busy[0]) eof <= 0;
else if (ptr_we) eof <= 1; // always second write cycle else if (ptr_we) eof <= 1; // always second write cycle
// @@@ delay by 1 clk
/// if (busy[1]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy
/// if (busy[2]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy
if (busy[2]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy if (busy[2]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy
if (busy[3]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy if (busy[3]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy
......
...@@ -34,25 +34,42 @@ ...@@ -34,25 +34,42 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module cmprs_status( module cmprs_status(
input mrst,
input mclk, // system clock input mclk, // system clock
input eof_written, input eof_written,
input stuffer_running, input stuffer_running,
input reading_frame, input reading_frame,
output [2:0] status input set_interrupts,
input [1:0] data_in,
output [4:0] status,
output irq
); );
reg stuffer_running_r; reg stuffer_running_r;
reg flushing_fifo; reg flushing_fifo;
reg is_r; // interrupt status (not masked)
reg im_r; // interrupt mask
assign status = {flushing_fifo, stuffer_running_r, reading_frame};
assign status = {flushing_fifo,
stuffer_running_r,
reading_frame,
im_r, is_r};
assign irq = is_r && im_r;
always @(posedge mclk) begin always @(posedge mclk) begin
if (mrst) im_r <= 0;
else if (set_interrupts && data_in[1]) im_r <= data_in[0];
if (mrst) is_r <= 0;
else if (eof_written) is_r <= 1;
else if (set_interrupts && (data_in == 1)) is_r <= 0;
stuffer_running_r <= stuffer_running; stuffer_running_r <= stuffer_running;
if (stuffer_running_r && !stuffer_running) flushing_fifo <= 1; if (stuffer_running_r && !stuffer_running) flushing_fifo <= 1;
else if (eof_written) flushing_fifo <= 0; else if (eof_written) flushing_fifo <= 0;
end end
endmodule endmodule
...@@ -54,6 +54,7 @@ module compressor393 # ( ...@@ -54,6 +54,7 @@ module compressor393 # (
parameter CMPRS_FORMAT= 2, parameter CMPRS_FORMAT= 2,
parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4, parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_INTERRUPTS= 5,
parameter CMPRS_TABLES= 6, // 6..7 parameter CMPRS_TABLES= 6, // 6..7
parameter TABLE_QUANTIZATION_INDEX = 0, parameter TABLE_QUANTIZATION_INDEX = 0,
parameter TABLE_CORING_INDEX = 1, parameter TABLE_CORING_INDEX = 1,
...@@ -141,12 +142,13 @@ module compressor393 # ( ...@@ -141,12 +142,13 @@ module compressor393 # (
input hrst, // @posedge hclk, sync reset input hrst, // @posedge hclk, sync reset
// programming interface // programming interface
input mclk, // global system/memory clock input mclk, // global system/memory clock
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25] output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address) input status_start, // Acknowledge of the first status packet byte (address)
output [3:0] cmprs_irq, // Compressor done interruupt
// Buffer interfaces, combined for 4 channels // Buffer interfaces, combined for 4 channels
input [3:0] xfer_reset_page_rd, // from mcntrl_tiled_rw ( input [3:0] xfer_reset_page_rd, // from mcntrl_tiled_rw (
...@@ -280,7 +282,6 @@ module compressor393 # ( ...@@ -280,7 +282,6 @@ module compressor393 # (
wire [3:0] flush_hclk; // before last data was written wire [3:0] flush_hclk; // before last data was written
wire [31:0] fifo_count; wire [31:0] fifo_count;
/* Instance template for module status_router8 */
status_router8 status_router8_i ( status_router8 status_router8_i (
.rst (1'b0), //rst), // input .rst (1'b0), //rst), // input
.clk (mclk), // input .clk (mclk), // input
...@@ -339,6 +340,7 @@ module compressor393 # ( ...@@ -339,6 +340,7 @@ module compressor393 # (
.CMPRS_FORMAT (CMPRS_FORMAT), .CMPRS_FORMAT (CMPRS_FORMAT),
.CMPRS_COLOR_SATURATION (CMPRS_COLOR_SATURATION), .CMPRS_COLOR_SATURATION (CMPRS_COLOR_SATURATION),
.CMPRS_CORING_MODE (CMPRS_CORING_MODE), .CMPRS_CORING_MODE (CMPRS_CORING_MODE),
.CMPRS_INTERRUPTS (CMPRS_INTERRUPTS),
.CMPRS_TABLES (CMPRS_TABLES), .CMPRS_TABLES (CMPRS_TABLES),
.TABLE_QUANTIZATION_INDEX (TABLE_QUANTIZATION_INDEX), .TABLE_QUANTIZATION_INDEX (TABLE_QUANTIZATION_INDEX),
.TABLE_CORING_INDEX (TABLE_CORING_INDEX), .TABLE_CORING_INDEX (TABLE_CORING_INDEX),
...@@ -414,6 +416,7 @@ module compressor393 # ( ...@@ -414,6 +416,7 @@ module compressor393 # (
.status_ad (status_ad_mux[8 * i +: 8]), // output[7:0] .status_ad (status_ad_mux[8 * i +: 8]), // output[7:0]
.status_rq (status_rq_mux[i]), // output .status_rq (status_rq_mux[i]), // output
.status_start (status_start_mux[i]), // input .status_start (status_start_mux[i]), // input
.irq (cmprs_irq[i]), // output
.xfer_reset_page_rd (xfer_reset_page_rd[i]), // input .xfer_reset_page_rd (xfer_reset_page_rd[i]), // input
.buf_wpage_nxt (buf_wpage_nxt[i]), // input .buf_wpage_nxt (buf_wpage_nxt[i]), // input
.buf_we (buf_we[i]), // input .buf_we (buf_we[i]), // input
......
...@@ -47,6 +47,7 @@ module jp_channel#( ...@@ -47,6 +47,7 @@ module jp_channel#(
parameter CMPRS_FORMAT= 2, parameter CMPRS_FORMAT= 2,
parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4, parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_INTERRUPTS= 5,
parameter CMPRS_TABLES= 6, // 6(data)..7(address) parameter CMPRS_TABLES= 6, // 6(data)..7(address)
parameter TABLE_QUANTIZATION_INDEX = 0, parameter TABLE_QUANTIZATION_INDEX = 0,
parameter TABLE_CORING_INDEX = 1, parameter TABLE_CORING_INDEX = 1,
...@@ -116,34 +117,30 @@ module jp_channel#( ...@@ -116,34 +117,30 @@ module jp_channel#(
`endif `endif
)( )(
// input rst, // global reset input xclk, // global clock input, compressor single clock rate
input xclk, // global clock input, compressor single clock rate
`ifdef USE_XCLK2X `ifdef USE_XCLK2X
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
`endif `endif
input mrst, // @posedge mclk, sync reset input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset input xrst, // @posedge xclk, sync reset
input hrst, // @posedge xclk, sync reset input hrst, // @posedge xclk, sync reset
// programming interface // programming interface
input mclk, // global system/memory clock input mclk, // global system/memory clock
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25] output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address) input status_start, // Acknowledge of the first status packet byte (address)
output irq, // processor interrupt
// Buffer interface (buffer to be a part of the memory controller - it is connected there by a 64-bit data, here - by an 9-bit one // Buffer interface (buffer to be a part of the memory controller - it is connected there by a 64-bit data, here - by an 9-bit one
input xfer_reset_page_rd, // from mcntrl_tiled_rw ( input xfer_reset_page_rd, // from mcntrl_tiled_rw (
input buf_wpage_nxt, // advance to next page memory interface writes to input buf_wpage_nxt, // advance to next page memory interface writes to
input buf_we, // @!mclk write buffer from memory, increment write input buf_we, // @!mclk write buffer from memory, increment write
input [63:0] buf_din, // data out input [63:0] buf_din, // data out
// output [11:0] buf_ra,
// output buf_ren,
// output buf_regen,
// input [ 7:0] buf_di,
input page_ready_chn, // single mclk (posedge) input page_ready_chn, // single mclk (posedge)
output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
...@@ -186,8 +183,8 @@ module jp_channel#( ...@@ -186,8 +183,8 @@ module jp_channel#(
input fifo_rst, // reset FIFO (set read address to write, reset count) input fifo_rst, // reset FIFO (set read address to write, reset count)
input fifo_ren, input fifo_ren,
output [63:0] fifo_rdata, output [63:0] fifo_rdata,
output fifo_eof, // single rclk pulse signalling EOF output fifo_eof, // single rclk pulse signaling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse) input eof_written, // confirm frame written over AFI to the system memory (single rclk pulse)
output fifo_flush, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read) output fifo_flush, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output flush_hclk, // output before writing last chunk - use it to suspend AFI to have output flush_hclk, // output before writing last chunk - use it to suspend AFI to have
// last burst marked as the last one (otherwise last may be empty if frame had %4==0 chunks) // last burst marked as the last one (otherwise last may be empty if frame had %4==0 chunks)
...@@ -313,16 +310,9 @@ module jp_channel#( ...@@ -313,16 +310,9 @@ module jp_channel#(
wire enc_dv; wire enc_dv;
//TODO: use next signals for status //TODO: use next signals for status
// wire eof_written_mclk;
// wire stuffer_done_mclk;
wire stuffer_running_mclk; wire stuffer_running_mclk;
wire reading_frame; wire reading_frame;
/// wire last_block; //huffman393
/// wire test_lbw;
`ifdef USE_XCLK2X `ifdef USE_XCLK2X
wire [15:0] huff_do; // output[15:0] reg wire [15:0] huff_do; // output[15:0] reg
wire [3:0] huff_dl; // output[3:0] reg wire [3:0] huff_dl; // output[3:0] reg
...@@ -342,6 +332,7 @@ module jp_channel#( ...@@ -342,6 +332,7 @@ module jp_channel#(
wire set_format_w; wire set_format_w;
wire set_color_saturation_w; wire set_color_saturation_w;
wire set_coring_w; wire set_coring_w;
wire set_interrupts_w;
wire set_tables_w; wire set_tables_w;
wire stuffer_running; // @negedge xclk2x from registering timestamp until done wire stuffer_running; // @negedge xclk2x from registering timestamp until done
...@@ -352,6 +343,7 @@ module jp_channel#( ...@@ -352,6 +343,7 @@ module jp_channel#(
wire [ 2:0] cmprs_qpage; wire [ 2:0] cmprs_qpage;
wire [ 2:0] coring_num; wire [ 2:0] coring_num;
reg dcc_en; reg dcc_en;
wire [15:0] dccdata; // was not used in late nc353 wire [15:0] dccdata; // was not used in late nc353
wire dccvld; // was not used in late nc353 wire dccvld; // was not used in late nc353
...@@ -361,8 +353,10 @@ module jp_channel#( ...@@ -361,8 +353,10 @@ module jp_channel#(
assign set_format_w = cmd_we && (cmd_a== CMPRS_FORMAT); assign set_format_w = cmd_we && (cmd_a== CMPRS_FORMAT);
assign set_color_saturation_w = cmd_we && (cmd_a== CMPRS_COLOR_SATURATION); assign set_color_saturation_w = cmd_we && (cmd_a== CMPRS_COLOR_SATURATION);
assign set_coring_w = cmd_we && (cmd_a== CMPRS_CORING_MODE); assign set_coring_w = cmd_we && (cmd_a== CMPRS_CORING_MODE);
assign set_interrupts_w = cmd_we && (cmd_a== CMPRS_INTERRUPTS);
assign set_tables_w = cmd_we && ((cmd_a & 6)== CMPRS_TABLES); assign set_tables_w = cmd_we && ((cmd_a & 6)== CMPRS_TABLES);
`ifdef USE_XCLK2X `ifdef USE_XCLK2X
// re-sync to posedge xclk2x // re-sync to posedge xclk2x
reg xrst2xn; reg xrst2xn;
...@@ -586,31 +580,36 @@ module jp_channel#( ...@@ -586,31 +580,36 @@ module jp_channel#(
.data (cmd_data), // output[31:0] .data (cmd_data), // output[31:0]
.we (cmd_we) // output .we (cmd_we) // output
); );
wire [2:0] status_data;
wire [4:0] status_data;
cmprs_status cmprs_status_i ( cmprs_status cmprs_status_i (
.mclk (mclk), // input .mrst (mrst), // input
.eof_written (eof_written_mclk), // input .mclk (mclk), // input
.stuffer_running (stuffer_running_mclk), // input .eof_written (eof_written_mclk), // input
.reading_frame (reading_frame), // input .stuffer_running (stuffer_running_mclk), // input
.status (status_data) // output[2:0] .reading_frame (reading_frame), // input
.set_interrupts (set_interrupts_w), // input
.data_in (cmd_data[1:0]), // input[1:0]
.status (status_data), // output[2:0]
.irq (irq) // output
); );
status_generate #( status_generate #(
.STATUS_REG_ADDR (CMPRS_STATUS_REG_ADDR), .STATUS_REG_ADDR (CMPRS_STATUS_REG_ADDR),
.PAYLOAD_BITS (3), .PAYLOAD_BITS (7),
.EXTRA_WORDS (1), .EXTRA_WORDS (1),
.EXTRA_REG_ADDR (CMPRS_HIFREQ_REG_ADDR) .EXTRA_REG_ADDR (CMPRS_HIFREQ_REG_ADDR)
) status_generate_i ( ) status_generate_i (
.rst (1'b0), //rst), // input .rst (1'b0), //rst), // input
.clk (mclk), // input .clk (mclk), // input
.srst (mrst), // input .srst (mrst), // input
.we (set_status_w), // input .we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0] .wd (cmd_data[7:0]), // input[7:0]
.status ({hifreq,status_data}), // input[2:0] .status ({hifreq,status_data,2'b0}), // input[2:0]
.ad (status_ad), // output[7:0] .ad (status_ad), // output[7:0]
.rq (status_rq), // output .rq (status_rq), // output
.start (status_start) // input .start (status_start) // input
); );
//hifreq //hifreq
// Not needed? // Not needed?
......
...@@ -31,7 +31,9 @@ ...@@ -31,7 +31,9 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*******************************************************************************/ *******************************************************************************/
parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%) parameter FPGA_VERSION = 32'h03930073; // Adding interrupts support
// parameter FPGA_VERSION = 32'h03930072; // Adding hact monitor bit 77.9%, failed timing
// parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
// parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%) // parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %) // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%) // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%)
......
...@@ -633,6 +633,7 @@ ...@@ -633,6 +633,7 @@
parameter CMPRS_FORMAT= 2, parameter CMPRS_FORMAT= 2,
parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4, parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_INTERRUPTS= 5,
parameter CMPRS_TABLES= 6, // 6..7 parameter CMPRS_TABLES= 6, // 6..7
parameter TABLE_QUANTIZATION_INDEX = 0, parameter TABLE_QUANTIZATION_INDEX = 0,
parameter TABLE_CORING_INDEX = 1, parameter TABLE_CORING_INDEX = 1,
...@@ -762,6 +763,7 @@ ...@@ -762,6 +763,7 @@
parameter CMDFRAMESEQ_CTRL = 31, parameter CMDFRAMESEQ_CTRL = 31,
parameter CMDFRAMESEQ_RST_BIT = 14, parameter CMDFRAMESEQ_RST_BIT = 14,
parameter CMDFRAMESEQ_RUN_BIT = 13, parameter CMDFRAMESEQ_RUN_BIT = 13,
parameter CMDFRAMESEQ_IRQ_BIT = 0,
parameter CMDSEQMUX_ADDR = 'h702, // only status control parameter CMDSEQMUX_ADDR = 'h702, // only status control
parameter CMDSEQMUX_MASK = 'h7ff, parameter CMDSEQMUX_MASK = 'h7ff,
......
This diff is collapsed.
...@@ -965,12 +965,89 @@ class X393Jpeg(object): ...@@ -965,12 +965,89 @@ class X393Jpeg(object):
ff d9 ff d9
""" """
""" """
cd /usr/local/verilog/; test_mcntrl.py @hargs
measure_all "*DI"
setup_all_sensors True None 0xf
#write_sensor_i2c 0 1 0 0x30700101
compressor_control all None None None None None 2
program_gamma all 0 0.57 0.04
write_sensor_i2c 0 1 0 0x030600b4
write_sensor_i2c 0 1 0 0x31c68400
write_sensor_i2c 0 1 0 0x306e9280
#write_sensor_i2c 0 1 0 0x30700002
write_sensor_i2c 0 1 0 0x301a001c
print_sensor_i2c 0 0x31c6 0xff 0x10 0
compressor_control 0 2
jpeg_write "img.jpeg" 0
jpeg_acquire_write
write_sensor_i2c 0 1 0 0x30700000
-------
setup_all_sensors True None 0xf
write_sensor_i2c 0 1 0 0x30700101
compressor_control all None None None None None 2
program_gamma all 0 0.57 0.04
write_sensor_i2c 0 1 0 0x030600b4
print_sensor_i2c 0 0x306 0xff 0x10 0
print_sensor_i2c 0 0x303a 0xff 0x10 0
print_sensor_i2c 0 0x301a 0xff 0x10 0
print_sensor_i2c 0 0x31c6 0xff 0x10 0
write_sensor_i2c 0 1 0 0x31c68400
print_sensor_i2c 0 0x31c6 0xff 0x10 0
print_sensor_i2c 0 0x306e 0xff 0x10 0
write_sensor_i2c 0 1 0 0x306e9280
write_sensor_i2c 0 1 0 0x30700002
write_sensor_i2c 0 1 0 0x301a001c
print_sensor_i2c 0 0x31c6 0xff 0x10 0
compressor_control 0 2
x393 +0.001s--> jpeg_write "img.jpeg" 0
http://192.168.0.7/imgsrv.py?y_quality=85&gamma=0.5&verbose=0&cmode=jpeg&bayer=2&expos=3000&flip_x=1&flip_y=1
JP46: demuxing... JP46: demuxing...
Corrupt JPEG data: bad Huffman code Corrupt JPEG data: bad Huffman code
Corrupt JPEG data: bad Huffman code Corrupt JPEG data: bad Huffman code
Corrupt JPEG data: bad Huffman code Corrupt JPEG data: bad Huffman code
def jpeg_acquire_write(self,
file_path = "img.jpeg",
channel = 0,
cmode = None, # vrlg.CMPRS_CBIT_CMODE_JPEG18, # read it from the saved
bayer = None,
y_quality = None,
c_quality = None,
portrait = None,
gamma = None, # 0.57,
black = None, # 0.04,
colorsat_blue = None, # 2.0, colorsat_blue, #0x180 # 0x90 for 1x
colorsat_red = None, # 2.0, colorsat_red, #0x16c, # 0xb6 for x1
server_root = "/www/pages/",
verbose = 1):
def print_sensor_i2c (self,
num_sensor,
reg_addr,
indx = 1,
sa7 = 0x48,
verbose = 1):
Read sequence of bytes available and print the result as a single hex number
@param num_sensor - sensor port number (0..3), or "all" - same to all sensors
@param reg_addr - register to read address 1/2 bytes (defined by previously set format)
@param indx - i2c command index in 1 256-entry table (defines here i2c delay, number of address bytes and number of data bytes)
@param sa7 - 7-bit i2c slave address
@param verbose - verbose level
print_sensor_i2c 0 0x306 0xff 0x10 0
#should be no MSB first (0x31c68400) #should be no MSB first (0x31c68400)
cd /usr/local/verilog/; test_mcntrl.py @hargs cd /usr/local/verilog/; test_mcntrl.py @hargs
......
...@@ -128,7 +128,8 @@ class X393Sensor(object): ...@@ -128,7 +128,8 @@ class X393Sensor(object):
""" """
status= self.get_status_sensor_io(num_sensor) status= self.get_status_sensor_io(num_sensor)
print ("print_status_sensor_io(%d):"%(num_sensor)) print ("print_status_sensor_io(%d):"%(num_sensor))
#last_in_line_1cyc_mclk, dout_valid_1cyc_mclk #last_in_line_1cyc_mclk, dout_valid_1cyc_mclk
"""
print (" last_in_line_1cyc_mclk = %d"%((status>>23) & 1)) print (" last_in_line_1cyc_mclk = %d"%((status>>23) & 1))
print (" dout_valid_1cyc_mclk = %d"%((status>>22) & 1)) print (" dout_valid_1cyc_mclk = %d"%((status>>22) & 1))
print (" alive_hist0_gr = %d"%((status>>21) & 1)) print (" alive_hist0_gr = %d"%((status>>21) & 1))
...@@ -140,10 +141,13 @@ class X393Sensor(object): ...@@ -140,10 +141,13 @@ class X393Sensor(object):
print (" vact_alive = %d"%((status>>15) & 1)) print (" vact_alive = %d"%((status>>15) & 1))
print (" hact_ext_alive = %d"%((status>>14) & 1)) print (" hact_ext_alive = %d"%((status>>14) & 1))
print (" hact_alive = %d"%((status>>13) & 1)) print (" hact_alive = %d"%((status>>13) & 1))
"""
print (" hact_run = %d"%((status>>13) & 1))
print (" locked_pxd_mmcm = %d"%((status>>12) & 1)) print (" locked_pxd_mmcm = %d"%((status>>12) & 1))
print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1)) print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1))
print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1)) print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1))
print (" ps_rdy = %d"%((status>> 9) & 1)) print (" xfpgadone = %d"%((status>> 9) & 1))
print (" ps_rdy = %d"%((status>> 8) & 1))
print (" ps_out = %d"%((status>> 0) & 0xff)) print (" ps_out = %d"%((status>> 0) & 0xff))
print (" xfpgatdo = %d"%((status>>25) & 1)) print (" xfpgatdo = %d"%((status>>25) & 1))
print (" senspgmin = %d"%((status>>24) & 1)) print (" senspgmin = %d"%((status>>24) & 1))
...@@ -787,6 +791,43 @@ class X393Sensor(object): ...@@ -787,6 +791,43 @@ class X393Sensor(object):
self.x393_axi_tasks.write_control_register(reg_addr + 3, dlys[3]) # {mmcm_phase, bpf, vact, hact} self.x393_axi_tasks.write_control_register(reg_addr + 3, dlys[3]) # {mmcm_phase, bpf, vact, hact}
self.set_sensor_io_ctl (num_sensor = num_sensor, self.set_sensor_io_ctl (num_sensor = num_sensor,
set_delays = True) set_delays = True)