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Commit ea63654a authored by Andrey Filippov's avatar Andrey Filippov
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Modified DDR memory calibration to reduce occasional failures

parent 18b781bc
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.project
View file @ ea63654a
......@@ -62,57 +62,52 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151117233307674.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160313161825094.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20151105233458943.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20151101221627109.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160313161825094.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150905102847882.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160313161825094.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -132,7 +127,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150905102847882.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160313161825094.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs
View file @ ea63654a
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary=true
VivadoTimimgSummaryReportSynthesis_122_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_122_DisableVivadoTimingSummary<-@\#\#@->
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs
View file @ ea63654a
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
VivadoTimingReportSynthesis_121_DisableVivadoTiming=true
VivadoTimingReportSynthesis_122_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_121_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_122_DisableVivadoTiming<-@\#\#@->
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_121_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.settings/org.eclipse.core.resources.prefs
View file @ ea63654a
......@@ -2,3 +2,4 @@ eclipse.preferences.version=1
encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8
encoding//py393/test_mcntrl.py=utf-8
py393/dbg/x393_mcntrl.pickle 100755 → 100644
View file @ ea63654a
This diff is collapsed.
py393/x393_axi_control_status.py
View file @ ea63654a
......@@ -163,22 +163,44 @@ class X393AxiControlStatus(object):
"""
Read current temperature and supply voltages
"""
HWMON_PATH = "/sys/devices/amba.0/f8007100.ps7-xadc/"
# HWMON_PATH = "/sys/devices/amba.0/f8007100.ps7-xadc/"
HWMON_PATH = '/sys/devices/soc0/amba@0/f8007100.ps7-xadc/iio:device0/'
FILE = "file"
ITEM = "item"
UNITS = "units"
SCALE = "scale"
HWMON_ITEMS= [{FILE:"temp", ITEM:"Temperature", UNITS:"C", SCALE: 1.0},
{FILE:"vccaux", ITEM:"VCCaux", UNITS:"V", SCALE: 0.001},
{FILE:"vccint", ITEM:"VCCint", UNITS:"V", SCALE: 0.001},
{FILE:"vccbram", ITEM:"VCCbram", UNITS:"V", SCALE: 0.001}]
HWMON_ITEMS= [{FILE:"in_temp0", ITEM:"Temperature", UNITS:"C", SCALE: 0.001},
{FILE:"in_voltage0_vccint", ITEM:"VCCint", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage1_vccaux", ITEM:"VCCaux", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage2_vccbram", ITEM:"VCCbram", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage3_vccpint", ITEM:"VCCPint", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage4_vccpaux", ITEM:"VCCPaux", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage5_vccoddr", ITEM:"VCCOddr", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage6_vrefp", ITEM:"VREFp", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage7_vrefn", ITEM:"VREFn", UNITS:"V", SCALE: 0.001},
]
print("hwmon:")
if self.DRY_MODE:
print ("Not defined for simulation mode")
return
for par in HWMON_ITEMS:
with open(HWMON_PATH + par[FILE]) as f:
d=int(f.read())
# with open(HWMON_PATH + par[FILE]) as f:
# d=int(f.read())
with open(HWMON_PATH + par[FILE]+"_raw") as f:
raw=float(f.read().strip())
with open(HWMON_PATH + par[FILE]+"_scale") as f:
scale=float(f.read().strip())
try:
with open(HWMON_PATH + par[FILE]+"_offset") as f:
offset=float(f.read().strip())
except:
offset = 0
#(guess)
# if (raw>2047) and (par[UNITS] == 'V'):
if (raw > 4000):
raw -= 4096
d= (raw + offset)*scale
num_digits=0
s = par[SCALE]
while s < 1:
......@@ -187,6 +209,7 @@ class X393AxiControlStatus(object):
w = 2+num_digits + (0,1)[num_digits > 0]
frmt = "%%12s = %%%d.%df %%s"%(w,num_digits)
print(frmt%(par[ITEM],(d*par[SCALE]),par[UNITS]))
def write_control_register(self, reg_addr, data):
"""
Write 32-bit word to the control register
......
py393/x393_mcntrl_adjust.py
View file @ ea63654a
This diff is collapsed.
py393/x393_mcntrl_membridge.py
View file @ ea63654a
......@@ -38,7 +38,8 @@ import x393_mcntrl_timing
import x393_mcntrl_buffers
#import verilog_utils
import x393_mcntrl
MEM_PATH='/sys/devices/elphel393-mem.2/'
#MEM_PATH='/sys/devices/elphel393-mem.2/'
MEM_PATH='/sys/devices/soc0/elphel393-mem@0/'
BUFFER_ADDRESS_NAME='buffer_address'
BUFFER_PAGES_NAME='buffer_pages'
BUFFER_ADDRESS=None
......
py393/x393_mem.py
View file @ ea63654a
......@@ -57,8 +57,8 @@ class X393Mem(object):
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
packedData=struct.pack(self.ENDIAN+"L",data)
d=struct.unpack(self.ENDIAN+"L",packedData)[0]
......@@ -87,8 +87,8 @@ class X393Mem(object):
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
data=struct.unpack(self.ENDIAN+"L",mm[page_offs:page_offs+4])
d=data[0]
......@@ -128,8 +128,8 @@ class X393Mem(object):
for addr in range (start_addr,end_addr+byte_mode,byte_mode):
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
data=struct.unpack_from(self.ENDIAN+frmt_bytes[byte_mode],mm, page_offs)
rslt.append(data[0])
......@@ -181,8 +181,8 @@ class X393Mem(object):
if page_num == last_page:
end_offset = start_addr + length - self.PAGE_SIZE * page_num
page_addr = page_num * self.PAGE_SIZE
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
bf.write(mm[start_offset:end_offset])
......@@ -208,8 +208,8 @@ class X393Mem(object):
if page_num == last_page:
end_offset = start_addr + length - self.PAGE_SIZE * page_num
page_addr = page_num * self.PAGE_SIZE
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
mm[start_offset:end_offset] = patt[start_offset:end_offset]
......@@ -243,8 +243,8 @@ class X393Mem(object):
data = (start_data + ((addr-start_addr) // byte_mode)*inc_data) & data_mask
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
print (("0x%08x: "+ data_frmt)%(addr,data))
else:
with open("/dev/mem", "r+b") as f:
......@@ -252,8 +252,8 @@ class X393Mem(object):
data = (start_data + ((addr-start_addr) // byte_mode)*inc_data) & data_mask
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
struct.pack_into(self.ENDIAN+frmt_bytes[byte_mode],mm, page_offs, data)
......
py393/x393_pio_sequences.py
View file @ ea63654a
......@@ -88,7 +88,7 @@ class X393PIOSequences(object):
((page & 3) << 10) |
(seq_addr & 0x3ff))
def wait_ps_pio_ready(self, #; // wait PS PIO module can accept comamnds (fifo half empty)
def wait_ps_pio_ready(self, #; // wait PS PIO module can accept commands (fifo half empty)
mode, # input [1:0] mode;
sync_seq, # input sync_seq; // synchronize sequences
timeout=2.0): # maximal timeout in seconds
......@@ -860,7 +860,8 @@ class X393PIOSequences(object):
0, # 1'h0, # mpr; # MPR mode: 0 - normal, 1 - dataflow from MPR
0) # 2'h0); # [1:0] mpr_rf; # MPR read function: 2'b00: predefined pattern 0101...
cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.INITIALIZE_OFFSET;
if self.DEBUG_MODE > 1:
# if self.DEBUG_MODE > 1:
if self.DEBUG_MODE > -1:
print("mr0=0x%05x"%mr0);
print("mr1=0x%05x"%mr1);
print("mr2=0x%05x"%mr2);
......@@ -1120,7 +1121,8 @@ class X393PIOSequences(object):
last_bad= 0
rslt=(first_bad, last_bad, data16[mid_index],mid_index)
if quiet < 3:
print ("non_consecutive leading/trailing: %d /%d, middle data=0x%x, index=0x%x"%rslt)
print ("non_consecutive leading/trailing: %d /%d, middle data=0x%x, index=0x%x"%rslt)
print(data16)
return rslt
......
py393/x393_sens_cmprs.py
View file @ ea63654a
......@@ -52,9 +52,14 @@ from verilog_utils import hx
PAGE_SIZE = 4096
SI5338_PATH = '/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070'
POWER393_PATH = '/sys/devices/elphel393-pwr.1'
MEM_PATH = '/sys/devices/elphel393-mem.2/'
#SI5338_PATH = '/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070'
#POWER393_PATH = '/sys/devices/elphel393-pwr.1'
#MEM_PATH = '/sys/devices/elphel393-mem.2/'
SI5338_PATH = '/sys/devices/soc0/amba@0/e0004000.ps7-i2c/i2c-0/0-0070'
POWER393_PATH = '/sys/devices/soc0/elphel393-pwr@0'
MEM_PATH = '/sys/devices/soc0/elphel393-mem@0/'
BUFFER_ADDRESS_NAME = 'buffer_address'
BUFFER_PAGES_NAME = 'buffer_pages'
BUFFER_ADDRESS = None # in bytes
......@@ -148,7 +153,7 @@ class X393SensCmprs(object):
Currently required clock frequency is 1/4 of the sensor clock, so it is 24MHz for 96MHz sensor
@param freq_MHz - input clock frequency (MHz). Currently for 96MHZ sensor clock it should be 24.0
@param iface - one of the supported interfaces
(see ls /sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070/output_drivers)
(see ls /sys/devices/soc0/amba@0/e0004000.ps7-i2c/i2c-0/0-0070/output_drivers)
@param quiet - reduce output
"""
if self.DRY_MODE:
......
py393/x393_utils.py
View file @ ea63654a
......@@ -97,7 +97,9 @@ class X393Utils(object):
if bitfile is None:
bitfile=DEFAULT_BITFILE
print ("Sensor ports power off")
POWER393_PATH = '/sys/devices/elphel393-pwr.1'
# POWER393_PATH = '/sys/devices/elphel393-pwr.1'
POWER393_PATH = '/sys/devices/soc0/elphel393-pwr@0'
with open (POWER393_PATH + "/channels_dis","w") as f:
print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
print ("FPGA clock OFF")
......
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