diff --git a/.settings/com.elphel.vdt.iverilog.prefs b/.settings/com.elphel.vdt.iverilog.prefs
index f33c69235a782907736ba5cd25a128e501a9cf6a..a08cfacc921f187774592e72c0a708582a4af123 100644
--- a/.settings/com.elphel.vdt.iverilog.prefs
+++ b/.settings/com.elphel.vdt.iverilog.prefs
@@ -1,5 +1,8 @@
-com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->
+com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->
eclipse.preferences.version=1
+iverilog_100_TopModulesOther=glbl<-@\#\#@->
+iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
+iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
diff --git a/axi/cmprs_afi_mux.v b/axi/cmprs_afi_mux.v
index fd726091a0416241f4a553721bdb31b4120135e3..c667ec26ef57b5de29d039bb068a107d84392208 100644
--- a/axi/cmprs_afi_mux.v
+++ b/axi/cmprs_afi_mux.v
@@ -32,7 +32,7 @@ module cmprs_afi_mux#(
parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid address
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3,
- parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
+ parameter AFI_MUX_BUF_LATENCY = 4'd2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
)(
// input rst,
input mclk, // for command/status
@@ -370,13 +370,13 @@ module cmprs_afi_mux#(
.din ({ wvalid, wlast, afi_awid}), // input[0:0]
.dout ({afi_wvalid, afi_wlast, afi_wid}) // output[0:0]
);
-
+ localparam [3:0] AFI_MUX_BUF_LATENCYM1 = AFI_MUX_BUF_LATENCY - 1;
dly_16 #(
.WIDTH(3)
) afi_wdata_i (
.clk (hclk), // input
.rst (!en), // input
- .dly (AFI_MUX_BUF_LATENCY-1), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
+ .dly (AFI_MUX_BUF_LATENCYM1), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
.din ({wvalid, cur_chn}), // input[0:0]
.dout ({wdata_en,wdata_sel}) // output[0:0]
);
diff --git a/compressor_jp/cmprs_buf_average.v b/compressor_jp/cmprs_buf_average.v
index 393fdb57fdab3104f67704e7ecabaea6d0036854..edf754d7769798fa1c44a1ab501c32b7017daa3b 100644
--- a/compressor_jp/cmprs_buf_average.v
+++ b/compressor_jp/cmprs_buf_average.v
@@ -295,10 +295,10 @@ module cmprs_buf_average#(
end
// delay from the start of data output from color converter to copy subtract_dc to be valid when average values are set
- dly_16 #(.WIDTH(1)) i_cs_first_out_late (.clk(xclk),.rst(1'b0), .dly(15), .din(cs_first_out), .dout(cs_first_out_late));
- dly_16 #(.WIDTH(1)) i_color_enable_d (.clk(xclk),.rst(1'b0), .dly( 1), .din(color_enable), .dout(color_enable_d));
- dly_16 #(.WIDTH(1)) i_dv (.clk(xclk),.rst(1'b0), .dly( 2), .din(dv_pre3), .dout(dv));
- dly_16 #(.WIDTH(1)) i_ds (.clk(xclk),.rst(1'b0), .dly( 2), .din(ds_pre3), .dout(ds));
+ dly_16 #(.WIDTH(1)) i_cs_first_out_late (.clk(xclk),.rst(1'b0), .dly(4'd15), .din(cs_first_out), .dout(cs_first_out_late));
+ dly_16 #(.WIDTH(1)) i_color_enable_d (.clk(xclk),.rst(1'b0), .dly( 4'd1), .din(color_enable), .dout(color_enable_d));
+ dly_16 #(.WIDTH(1)) i_dv (.clk(xclk),.rst(1'b0), .dly( 4'd2), .din(dv_pre3), .dout(dv));
+ dly_16 #(.WIDTH(1)) i_ds (.clk(xclk),.rst(1'b0), .dly( 4'd2), .din(ds_pre3), .dout(ds));
cmprs_tile_mode2_decode #(
.CMPRS_COLOR18 (CMPRS_COLOR18),
diff --git a/compressor_jp/compressor393.v b/compressor_jp/compressor393.v
index 2446207ba7be1f165f4da5bfdf016ebb5769d90d..d2e52e1e14dec8cf6242a5f14153332c28d04eef 100644
--- a/compressor_jp/compressor393.v
+++ b/compressor_jp/compressor393.v
@@ -110,7 +110,7 @@ module compressor393 # (
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3,
- parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
+ parameter AFI_MUX_BUF_LATENCY = 4'd2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
)(
// input rst, // global reset
@@ -275,12 +275,12 @@ module compressor393 # (
.rq_in5 (status_rq_mux[5]), // input
.start_in5 (status_start_mux[5]), // output
- .db_in6 (0), // input[7:0]
- .rq_in6 (0), // input
+ .db_in6 (8'b0), // input[7:0]
+ .rq_in6 (1'b0), // input
.start_in6 (), // output
- .db_in7 (0), // input[7:0]
- .rq_in7 (0), // input
+ .db_in7 (8'b0), // input[7:0]
+ .rq_in7 (1'b0), // input
.start_in7 (), // output
.db_out (status_ad), // output[7:0]
@@ -451,16 +451,16 @@ module compressor393 # (
.fifo_count1 (fifo_count[8 +: 8]), // input[7:0]
.fifo_rst2 (), // output
.fifo_ren2 (), // output
- .fifo_rdata2 (0), // input[63:0]
+ .fifo_rdata2 (64'b0), // input[63:0]
.eof_written2 (), // output
- .fifo_flush2 (0), // input
- .fifo_count2 (0), // input[7:0]
+ .fifo_flush2 (1'b0), // input
+ .fifo_count2 (8'b0), // input[7:0]
.fifo_rst3 (), // output
.fifo_ren3 (), // output
- .fifo_rdata3 (0), // input[63:0]
+ .fifo_rdata3 (64'b0), // input[63:0]
.eof_written3 (), // output
- .fifo_flush3 (0), // input
- .fifo_count3 (0), // input[7:0]
+ .fifo_flush3 (1'b0), // input
+ .fifo_count3 (8'b0), // input[7:0]
.afi_awaddr (afi0_awaddr), // output[31:0]
.afi_awvalid (afi0_awvalid), // output
.afi_awready (afi0_awready), // input
@@ -524,16 +524,16 @@ module compressor393 # (
.fifo_count1 (fifo_count[24 +: 8]), // input[7:0]
.fifo_rst2 (), // output
.fifo_ren2 (), // output
- .fifo_rdata2 (0), // input[63:0]
+ .fifo_rdata2 (64'b0), // input[63:0]
.eof_written2 (), // output
- .fifo_flush2 (0), // input
- .fifo_count2 (0), // input[7:0]
+ .fifo_flush2 (1'b0), // input
+ .fifo_count2 (8'b0), // input[7:0]
.fifo_rst3 (), // output
.fifo_ren3 (), // output
- .fifo_rdata3 (0), // input[63:0]
+ .fifo_rdata3 (64'b0), // input[63:0]
.eof_written3 (), // output
- .fifo_flush3 (0), // input
- .fifo_count3 (0), // input[7:0]
+ .fifo_flush3 (1'b0), // input
+ .fifo_count3 (8'b0), // input[7:0]
.afi_awaddr (afi1_awaddr), // output[31:0]
.afi_awvalid (afi1_awvalid), // output
.afi_awready (afi1_awready), // input
diff --git a/compressor_jp/csconvert18a.v b/compressor_jp/csconvert18a.v
index 35906aae5edddc3ffb15a4c6a6c2557fd05cf352..ca32b97b559855621bc43bfa0a5be811972b7f3f 100644
--- a/compressor_jp/csconvert18a.v
+++ b/compressor_jp/csconvert18a.v
@@ -272,15 +272,15 @@ module csconvert18a(
assign caddr = caddr_r;
assign cwe = cwe_r;
- dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(15), .din(pre_first_in), .dout(strt_dly[0]));
- dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(15), .din(strt_dly[0]), .dout(strt_dly[1]));
- dly_16 #(.WIDTH(1)) i_strt (.clk(CLK),.rst(1'b0), .dly( 4), .din(strt_dly[1]), .dout(strt));
+ dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(pre_first_in), .dout(strt_dly[0]));
+ dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(strt_dly[0]), .dout(strt_dly[1]));
+ dly_16 #(.WIDTH(1)) i_strt (.clk(CLK),.rst(1'b0), .dly( 4'd4), .din(strt_dly[1]), .dout(strt));
// SRL16 i_strt_dly0 (.Q(strt_dly[0]), .D(pre_first_in), .CLK(CLK), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1)); // dly=15+1
// SRL16 i_strt_dly1 (.Q(strt_dly[1]), .D(strt_dly[0]), .CLK(CLK), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1)); // dly=15+1
// SRL16 i_strt (.Q(strt), .D(strt_dly[1]), .CLK(CLK), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0)); // dly=4+1
- dly_16 #(.WIDTH(1)) i_ystrt (.clk(CLK),.rst(1'b0), .dly(5), .din(strt), .dout(ystrt));
- dly_16 #(.WIDTH(1)) i_nxtline (.clk(CLK),.rst(1'b0), .dly(1), .din(!RST && ywe_r && (yaddr_r[3:0]==4'hf) && (yaddr_r[7:4]!=4'hf)), .dout(nxtline));
+ dly_16 #(.WIDTH(1)) i_ystrt (.clk(CLK),.rst(1'b0), .dly(4'd5), .din(strt), .dout(ystrt));
+ dly_16 #(.WIDTH(1)) i_nxtline (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(!RST && ywe_r && (yaddr_r[3:0]==4'hf) && (yaddr_r[7:4]!=4'hf)), .dout(nxtline));
// SRL16 i_ystrt (.Q(ystrt), .D(strt), .CLK(CLK), .A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b0)); // dly=5+1
// SRL16 i_nxtline(.Q(nxtline),.D(!RST && ywe_r && (yaddr_r[3:0]==4'hf) && (yaddr_r[7:4]!=4'hf)), .CLK(CLK), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0)); // dly=1+1
@@ -595,7 +595,7 @@ end
// new, q is signed char
assign q[8:0]= ((cbcr[10]==cbcr[9]) && (!limit_diff || (cbcr[10]==cbcr[8])))? cbcr[9:1]: {cbcr[10],limit_diff?cbcr[10]:(~cbcr[10]),{7{~cbcr[10]}}};
-dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(1), .din(ywe_r), .dout(cwe0));
+dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(ywe_r), .dout(cwe0));
//SRL16 i_cwe0 (.D(ywe_r ), .Q(cwe0), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLK)); // dly=2=1+1
always @ (posedge CLK) begin
diff --git a/compressor_jp/focus_sharp393.v b/compressor_jp/focus_sharp393.v
index 07f2b6ff914144655b9de27bd0d54e0b98e0ab79..6ca4251084e9dc84c864a47bb353f007461fcf61 100644
--- a/compressor_jp/focus_sharp393.v
+++ b/compressor_jp/focus_sharp393.v
@@ -218,8 +218,8 @@ module focus_sharp393(
// SRL16 i_out_mono (.Q(out_mono), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(started_luma)); // timing not critical
// SRL16 i_out_window (.Q(out_window), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(in_woi)); // timing not critical
- dly_16 #(.WIDTH(1)) i_out_mono(.clk(clk), .rst(1'b0), .dly(15), .din(started_luma), .dout(out_mono)); // timing not critical
- dly_16 #(.WIDTH(1)) i_out_window(.clk(clk),.rst(1'b0), .dly(15), .din(in_woi), .dout(out_window)); // timing not critical
+ dly_16 #(.WIDTH(1)) i_out_mono(.clk(clk), .rst(1'b0), .dly(4'd15), .din(started_luma), .dout(out_mono)); // timing not critical
+ dly_16 #(.WIDTH(1)) i_out_window(.clk(clk),.rst(1'b0), .dly(4'd15), .din(in_woi), .dout(out_window)); // timing not critical
always @ (posedge clk) begin
if (start) started_luma <= !tn[2];
diff --git a/compressor_jp/jp_channel.v b/compressor_jp/jp_channel.v
index 1172d7fbada0cf589c87ce44c821aec24eb77d37..b36e4c103a6ce86fc00c5b3908a8a1fc504ac542 100644
--- a/compressor_jp/jp_channel.v
+++ b/compressor_jp/jp_channel.v
@@ -702,7 +702,7 @@ module jp_channel#(
.d_out (dct_out) // output[12:0]
);
wire quant_start;
- dly_16 #(.WIDTH(1)) i_quant_start (.clk(xclk),.rst(1'b0), .dly(0), .din(dct_pre_first_out), .dout(quant_start)); // dly=0+1
+ dly_16 #(.WIDTH(1)) i_quant_start (.clk(xclk),.rst(1'b0), .dly(4'd0), .din(dct_pre_first_out), .dout(quant_start)); // dly=0+1
always @ (posedge xclk) begin
diff --git a/compressor_jp/quantizer393.v b/compressor_jp/quantizer393.v
index 24fb161a853da7ad4eff726774b5e9cc0606d9aa..dbd9b72575b66254d41702042ee63dd66aa40855 100644
--- a/compressor_jp/quantizer393.v
+++ b/compressor_jp/quantizer393.v
@@ -253,7 +253,7 @@ module quantizer393(
dly_16 #(.WIDTH(1)) i_hfc_en (
.clk(clk),
.rst(1'b0),
- .dly(1),
+ .dly(4'd1),
.din(((tba[2:0]>hfc_sel[2:0]) || (tba[5:3]>hfc_sel[2:0])) && dcc_run && !ctype_prev[0]),
.dout(hfc_en)); // dly=1+1
diff --git a/compressor_jp/stuffer393.v b/compressor_jp/stuffer393.v
index 689c50563b62ff93cfc7ba7e9efd954762d9a357..64572b994511070d8c3d6772be704a5d11ab40cb 100644
--- a/compressor_jp/stuffer393.v
+++ b/compressor_jp/stuffer393.v
@@ -412,7 +412,7 @@ end
assign start_time_out= qv && trailer && (etrax_dma[3:0]== 4'h8) && !size_out_over;
assign start_sizeout= time_out && (etrax_dma[3:0]== 4'hc);
// SRL16_1 i_pre_flush_end_delayed (.D(size_out[1]),.Q(pre_flush_end_delayed), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk)); // dly=3+1 // rather arbitrary?
- dly_16 #(.WIDTH(1)) i_pre_flush_end_delayed(.clk(~clk),.rst(1'b0), .dly(14), .din(size_out[1]), .dout(pre_flush_end_delayed)); // dly=14+1 // rather arbitrary?
+ dly_16 #(.WIDTH(1)) i_pre_flush_end_delayed(.clk(~clk),.rst(1'b0), .dly(4'd14), .din(size_out[1]), .dout(pre_flush_end_delayed)); // dly=14+1 // rather arbitrary?
assign done = flush_end_delayed;
// extract strart of frame run from different clock, re-clock from the source
diff --git a/compressor_jp/xdct393.v b/compressor_jp/xdct393.v
index f82134802878342ed7ef8f401967ddc3156f9088..3c25b641d63d36cf5d582ebd5bb7658381dd7e5b 100644
--- a/compressor_jp/xdct393.v
+++ b/compressor_jp/xdct393.v
@@ -236,14 +236,14 @@ This value divided by 2raised to 8 is equivalent to ignoring the 8 lsb bits of t
wire sxregs_d8;
reg enable_toggle;
// SRL16_1 i_sxregs_d8 (.Q(sxregs_d8), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk),.D(sxregs)); // dly=7+1
- dly_16 #(.WIDTH(1)) i_sxregs_d8(.clk(nclk),.rst(1'b0), .dly(7), .din(sxregs), .dout(sxregs_d8)); // dly=7+1
+ dly_16 #(.WIDTH(1)) i_sxregs_d8(.clk(nclk),.rst(1'b0), .dly(4'd7), .din(sxregs), .dout(sxregs_d8)); // dly=7+1
// SRL16_1 i_pre_sxregs (.Q(pre_sxregs), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk), .D(start)); // dly=6+1
- dly_16 #(.WIDTH(1)) i_pre_sxregs(.clk(nclk),.rst(1'b0), .dly(6), .din(start), .dout(pre_sxregs)); // dly=6+1
+ dly_16 #(.WIDTH(1)) i_pre_sxregs(.clk(nclk),.rst(1'b0), .dly(4'd6), .din(start), .dout(pre_sxregs)); // dly=6+1
// SRL16_1 i_enwe (.Q(enwe), .A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(clk), .D(pre_sxregs)); // dly=5+1
- dly_16 #(.WIDTH(1)) i_enwe(.clk(nclk),.rst(1'b0), .dly(5), .din(pre_sxregs), .dout(enwe)); // dly=5+1
+ dly_16 #(.WIDTH(1)) i_enwe(.clk(nclk),.rst(1'b0), .dly(4'd5), .din(pre_sxregs), .dout(enwe)); // dly=5+1
always @ (posedge nclk) begin
enable_toggle <= en && (sxregs || (enable_toggle && !sxregs_d8));
@@ -463,16 +463,16 @@ module dct393_stage2 (
// SRL16 i_endv (.Q(endv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(start)); // dly=14+1
- dly_16 #(.WIDTH(1)) i_endv(.clk(clk),.rst(1'b0), .dly(14), .din(start), .dout(endv)); // dly=14+1
+ dly_16 #(.WIDTH(1)) i_endv(.clk(clk),.rst(1'b0), .dly(4'd14), .din(start), .dout(endv)); // dly=14+1
// SRL16 i_disdv (.Q(disdv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(rd_cntr[5:0]==6'h3f)); // dly=14+1
- dly_16 #(.WIDTH(1)) i_disdv(.clk(clk),.rst(1'b0), .dly(14), .din(rd_cntr[5:0]==6'h3f), .dout(disdv)); // dly=14+1
+ dly_16 #(.WIDTH(1)) i_disdv(.clk(clk),.rst(1'b0), .dly(4'd14), .din(rd_cntr[5:0]==6'h3f), .dout(disdv)); // dly=14+1
// SRL16 i_sxregs (.Q(sxregs), .A0(1'b0), .A1(1'b0), .A2(1'b0), .A3(1'b1), .CLK(clk),.D((rd_cntr[5:3]==3'h0) && en_started)); // dly=8+1
- dly_16 #(.WIDTH(1)) i_sxregs(.clk(clk),.rst(1'b0), .dly(8), .din((rd_cntr[5:3]==3'h0) && en_started), .dout(sxregs)); // dly=8+1
+ dly_16 #(.WIDTH(1)) i_sxregs(.clk(clk),.rst(1'b0), .dly(4'd8), .din((rd_cntr[5:3]==3'h0) && en_started), .dout(sxregs)); // dly=8+1
// SRL16 i_sxregs_d8 (.Q(sxregs_d8), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk),.D(sxregs && en_started)); // dly=7+1
- dly_16 #(.WIDTH(1)) i_sxregs_d8(.clk(clk),.rst(1'b0), .dly(7), .din(sxregs && en_started), .dout(sxregs_d8)); // dly=7+1
+ dly_16 #(.WIDTH(1)) i_sxregs_d8(.clk(clk),.rst(1'b0), .dly(4'd7), .din(sxregs && en_started), .dout(sxregs_d8)); // dly=7+1
always @ (posedge clk) begin
enable_toggle <= en && (sxregs || (enable_toggle && !sxregs_d8));
diff --git a/includes/x393_parameters.vh b/includes/x393_parameters.vh
index 18a5442e9028648165490199d54741c37ad3958f..ec3dce908387ed42ebc0d928882df0eb712baa5d 100644
--- a/includes/x393_parameters.vh
+++ b/includes/x393_parameters.vh
@@ -256,6 +256,17 @@
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter BUFFER_DEPTH32= 10, // Block rum buffer depth on a 32-bit port
+ // bits in mode control word
+ parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
+ parameter MCONTR_LINTILE_EN = 1, // enable requests
+ parameter MCONTR_LINTILE_WRITE = 2, // write to memory mode
+ parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
+ parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
+ parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
+ parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
+ parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
+ parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
+ parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h7f0,
@@ -389,7 +400,7 @@
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
- parameter SENSOR_FIFO_DELAY = 7,
+ parameter SENSOR_FIFO_DELAY = 4'd7,
// other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_WIDTH = 8,
@@ -542,9 +553,9 @@
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3,
- parameter AFI_MUX_BUF_LATENCY = 2, // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
+ parameter AFI_MUX_BUF_LATENCY = 4'd2, // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
// GPIO control : 'h700..'h701, status: 'h30
- parameter integer GPIO_DRIVE = 12,
+ parameter integer GPIO_DRIVE = 12,
parameter GPIO_ADDR = 'h700, // .701
parameter GPIO_MASK = 'h7fe,
parameter GPIO_STATUS_REG_ADDR = 'h30, // address where status can be read out (10 GPIO inputs)
diff --git a/includes/x393_simulation_parameters.vh b/includes/x393_simulation_parameters.vh
index 5bb12c47f3453d49b7f03d0789daf3855bd60bd6..d96dd7e934c5c76cb331ca7c63f7123a7f10a234 100644
--- a/includes/x393_simulation_parameters.vh
+++ b/includes/x393_simulation_parameters.vh
@@ -25,4 +25,9 @@
parameter integer AXI_TASK_HOLD=1.0,
// parameter [1:0] DEFAULT_STATUS_MODE=3,
- parameter SIMUL_AXI_READ_WIDTH=16
\ No newline at end of file
+ parameter SIMUL_AXI_READ_WIDTH=16,
+
+ parameter MEMCLK_PERIOD = 5.0,
+ parameter FCLK0_PERIOD = 10.417,
+ parameter FCLK1_PERIOD = 0.0
+
\ No newline at end of file
diff --git a/includes/x393_tasks_mcntrl_buffers.vh b/includes/x393_tasks_mcntrl_buffers.vh
index 3f3e0a30ca1889787cb2891e45cf732c39499a77..26cd946ddf615c9c84f51911cff250626b382bba 100644
--- a/includes/x393_tasks_mcntrl_buffers.vh
+++ b/includes/x393_tasks_mcntrl_buffers.vh
@@ -69,7 +69,7 @@ task write_block_incremtal;
i, // id
start_value+i+j,
4'hf, // wstrb
- (j == 15) ? 1 : 0 // last
+ (j == 15) ? 1'b1 : 1'b0 // last
);
$display(" Write block incremental (addr:data): 0x%08x:0x%x @%t", (i + j), start_value+i+j, $time);
end
@@ -122,7 +122,7 @@ task write_block_buf;
i, // id
(i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24),
4'hf, // wstrb
- (j == 15) ? 1 : 0 // last
+ (j == 15) ? 1'b1 : 1'b0 // last
);
$display(" Write block data (addr:data): 0x%08x:0x%x @%t", (i + j),
(i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24), $time);
diff --git a/input_data/focus_filt.dat b/input_data/focus_filt.dat
new file mode 100644
index 0000000000000000000000000000000000000000..e080d870fc616b4c26338b587b5b25b8a9d8a92f
--- /dev/null
+++ b/input_data/focus_filt.dat
@@ -0,0 +1,17 @@
+ 0000 0111 0444 0888 0fff 0fff 0888 0000
+ 0111 0111 0444 0888 0fff 0fff 0888 0000
+ 0444 0444 0888 0fff 0fff 0888 0444 0000
+ 0888 0888 0fff 0fff 0888 0444 0222 0000
+ 0fff 0fff 0fff 0888 0444 0222 0111 0000
+ 0fff 0fff 0888 0444 0222 0111 0000 0000
+ 0888 0888 0444 0222 0111 0000 0000 0000
+ 0000 0000 0000 0000 0000 0000 0000 0000
+
+ 0000 1111 4444 8888 ffff ffff 8888 0000
+ 1111 1111 4444 8888 ffff ffff 8888 0000
+ 4444 4444 8888 ffff ffff 8888 4444 0000
+ 8888 8888 ffff ffff 8888 4444 2222 0000
+ ffff ffff ffff 8888 4444 2222 1111 0000
+ ffff ffff 8888 4444 2222 1111 0000 0000
+ 8888 8888 4444 2222 1111 0000 0000 0000
+ 0000 0000 0000 0000 0000 0000 0000 0000
diff --git a/input_data/gps_data.dat b/input_data/gps_data.dat
new file mode 100644
index 0000000000000000000000000000000000000000..41dc48753ac453a1abc6d49aa8506f36268634b7
--- /dev/null
+++ b/input_data/gps_data.dat
@@ -0,0 +1,21 @@
+$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45
+$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B
+$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
+$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
+$GPRMC,042931.2,A,4043.39929,N,11155.92705,W,000.01,283.8,250411,013.2,E*45
+$GPGGA,042931.2,4043.39929,N,11155.92705,W,1,09,0.8,1280.5,M,-13.8,M,,*5A
+$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
+$GPVTG,283.8,T,270.5,M,000.01,N,0000.01,K*7F
+$GPRMC,042931.4,A,4043.39929,N,11155.92705,W,000.01,283.8,250411,013.2,E*43
+$GPGGA,042931.4,4043.39929,N,11155.92705,W,1,09,0.8,1280.5,M,-13.8,M,,*5C
+$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
+$GPVTG,283.8,T,270.5,M,000.01,N,0000.02,K*7C
+$GPRMC,042931.6,A,4043.39929,N,11155.92705,W,000.00,283.8,250411,013.2,E*40
+$GPGGA,042931.6,4043.39929,N,11155.92705,W,1,09,0.8,1280.5,M,-13.8,M,,*5E
+$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
+$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
+$GPRMC,042931.8,A,4043.39929,N,11155.92705,W,000.01,283.8,250411,013.2,E*4F
+$GPGGA,042931.8,4043.39929,N,11155.92705,W,1,09,0.8,1280.5,M,-13.8,M,,*50
+$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
+$GPVTG,283.8,T,270.5,M,000.01,N,0000.01,K*7F
+
diff --git a/input_data/huffman.dat b/input_data/huffman.dat
new file mode 100644
index 0000000000000000000000000000000000000000..9dd1a4e7912f84dfd11ddb83df3efbcef074e207
--- /dev/null
+++ b/input_data/huffman.dat
@@ -0,0 +1,33 @@
+ 04000a 020000 020001 030004 04000b 05001a 070078 0800f8 0a03f6 10ff82 10ff83 000000 000000 000000 000000 020000
+ 000000 04000c 05001b 070079 0901f6 0b07f6 10ff84 10ff85 10ff86 10ff87 10ff88 000000 000000 000000 000000 030002
+ 000000 05001c 0800f9 0a03f7 0c0ff4 10ff89 10ff8a 10ff8b 10ff8c 10ff8d 10ff8e 000000 000000 000000 000000 030003
+ 000000 06003a 0901f7 0c0ff5 10ff8f 10ff90 10ff91 10ff92 10ff93 10ff94 10ff95 000000 000000 000000 000000 030004
+ 000000 06003b 0a03f8 10ff96 10ff97 10ff98 10ff99 10ff9a 10ff9b 10ff9c 10ff9d 000000 000000 000000 000000 030005
+ 000000 07007a 0b07f7 10ff9e 10ff9f 10ffa0 10ffa1 10ffa2 10ffa3 10ffa4 10ffa5 000000 000000 000000 000000 030006
+ 000000 07007b 0c0ff6 10ffa6 10ffa7 10ffa8 10ffa9 10ffaa 10ffab 10ffac 10ffad 000000 000000 000000 000000 04000e
+ 000000 0800fa 0c0ff7 10ffae 10ffaf 10ffb0 10ffb1 10ffb2 10ffb3 10ffb4 10ffb5 000000 000000 000000 000000 05001e
+ 000000 0901f8 0f7fc0 10ffb6 10ffb7 10ffb8 10ffb9 10ffba 10ffbb 10ffbc 10ffbd 000000 000000 000000 000000 06003e
+ 000000 0901f9 10ffbe 10ffbf 10ffc0 10ffc1 10ffc2 10ffc3 10ffc4 10ffc5 10ffc6 000000 000000 000000 000000 07007e
+ 000000 0901fa 10ffc7 10ffc8 10ffc9 10ffca 10ffcb 10ffcc 10ffcd 10ffce 10ffcf 000000 000000 000000 000000 0800fe
+ 000000 0a03f9 10ffd0 10ffd1 10ffd2 10ffd3 10ffd4 10ffd5 10ffd6 10ffd7 10ffd8 000000 000000 000000 000000 0901fe
+ 000000 0a03fa 10ffd9 10ffda 10ffdb 10ffdc 10ffdd 10ffde 10ffdf 10ffe0 10ffe1 000000 000000 000000 000000 000000
+ 000000 0b07f8 10ffe2 10ffe3 10ffe4 10ffe5 10ffe6 10ffe7 10ffe8 10ffe9 10ffea 000000 000000 000000 000000 000000
+ 000000 10ffeb 10ffec 10ffed 10ffee 10ffef 10fff0 10fff1 10fff2 10fff3 10fff4 000000 000000 000000 000000 000000
+ 0b07f9 10fff5 10fff6 10fff7 10fff8 10fff9 10fffa 10fffb 10fffc 10fffd 10fffe 000000 000000 000000 000000 000000
+ 020000 020001 030004 04000a 050018 050019 060038 070078 0901f4 0a03f6 0c0ff4 000000 000000 000000 000000 020000
+ 000000 04000b 060039 0800f6 0901f5 0b07f6 0c0ff5 10ff88 10ff89 10ff8a 10ff8b 000000 000000 000000 000000 020001
+ 000000 05001a 0800f7 0a03f7 0c0ff6 0f7fc2 10ff8c 10ff8d 10ff8e 10ff8f 10ff90 000000 000000 000000 000000 020002
+ 000000 05001b 0800f8 0a03f8 0c0ff7 10ff91 10ff92 10ff93 10ff94 10ff95 10ff96 000000 000000 000000 000000 030006
+ 000000 06003a 0901f6 10ff97 10ff98 10ff99 10ff9a 10ff9b 10ff9c 10ff9d 10ff9e 000000 000000 000000 000000 04000e
+ 000000 06003b 0a03f9 10ff9f 10ffa0 10ffa1 10ffa2 10ffa3 10ffa4 10ffa5 10ffa6 000000 000000 000000 000000 05001e
+ 000000 070079 0b07f7 10ffa7 10ffa8 10ffa9 10ffaa 10ffab 10ffac 10ffad 10ffae 000000 000000 000000 000000 06003e
+ 000000 07007a 0b07f8 10ffaf 10ffb0 10ffb1 10ffb2 10ffb3 10ffb4 10ffb5 10ffb6 000000 000000 000000 000000 07007e
+ 000000 0800f9 10ffb7 10ffb8 10ffb9 10ffba 10ffbb 10ffbc 10ffbd 10ffbe 10ffbf 000000 000000 000000 000000 0800fe
+ 000000 0901f7 10ffc0 10ffc1 10ffc2 10ffc3 10ffc4 10ffc5 10ffc6 10ffc7 10ffc8 000000 000000 000000 000000 0901fe
+ 000000 0901f8 10ffc9 10ffca 10ffcb 10ffcc 10ffcd 10ffce 10ffcf 10ffd0 10ffd1 000000 000000 000000 000000 0a03fe
+ 000000 0901f9 10ffd2 10ffd3 10ffd4 10ffd5 10ffd6 10ffd7 10ffd8 10ffd9 10ffda 000000 000000 000000 000000 0b07fe
+ 000000 0901fa 10ffdb 10ffdc 10ffdd 10ffde 10ffdf 10ffe0 10ffe1 10ffe2 10ffe3 000000 000000 000000 000000 000000
+ 000000 0b07f9 10ffe4 10ffe5 10ffe6 10ffe7 10ffe8 10ffe9 10ffea 10ffeb 10ffec 000000 000000 000000 000000 000000
+ 000000 0e3fe0 10ffed 10ffee 10ffef 10fff0 10fff1 10fff2 10fff3 10fff4 10fff5 000000 000000 000000 000000 000000
+ 0a03fa 0f7fc3 10fff6 10fff7 10fff8 10fff9 10fffa 10fffb 10fffc 10fffd 10fffe 000000 000000 000000 000000 000000
+
diff --git a/input_data/linear1028rgb.dat b/input_data/linear1028rgb.dat
new file mode 100644
index 0000000000000000000000000000000000000000..53ac32ae57b58c925e8d76bf6ca4dda16e930c7d
--- /dev/null
+++ b/input_data/linear1028rgb.dat
@@ -0,0 +1,72 @@
+ 000 004 008 00c 010 014 018 01c 020 024 028 02c 030 034 038 03c
+ 040 044 048 04c 050 054 058 05c 060 064 068 06c 070 074 078 07c
+ 080 084 088 08c 090 094 098 09c 0a0 0a4 0a8 0ac 0b0 0b4 0b8 0bc
+ 0c0 0c4 0c8 0cc 0d0 0d4 0d8 0dc 0e0 0e4 0e8 0ec 0f0 0f4 0f8 0fc
+ 100 104 108 10c 110 114 118 11c 120 124 128 12c 130 134 138 13c
+ 140 144 148 14c 150 154 158 15c 160 164 168 16c 170 174 178 17c
+ 180 184 188 18c 190 194 198 19c 1a0 1a4 1a8 1ac 1b0 1b4 1b8 1bc
+ 1c0 1c4 1c8 1cc 1d0 1d4 1d8 1dc 1e0 1e4 1e8 1ec 1f0 1f4 1f8 1fc
+ 200 204 208 20c 210 214 218 21c 220 224 228 22c 230 234 238 23c
+ 240 244 248 24c 250 254 258 25c 260 264 268 26c 270 274 278 27c
+ 280 284 288 28c 290 294 298 29c 2a0 2a4 2a8 2ac 2b0 2b4 2b8 2bc
+ 2c0 2c4 2c8 2cc 2d0 2d4 2d8 2dc 2e0 2e4 2e8 2ec 2f0 2f4 2f8 2fc
+ 300 304 308 30c 310 314 318 31c 320 324 328 32c 330 334 338 33c
+ 340 344 348 34c 350 354 358 35c 360 364 368 36c 370 374 378 37c
+ 380 384 388 38c 390 394 398 39c 3a0 3a4 3a8 3ac 3b0 3b4 3b8 3bc
+ 3c0 3c4 3c8 3cc 3d0 3d4 3d8 3dc 3e0 3e4 3e8 3ec 3f0 3f4 3f8 3fc
+ 3ff
+
+ 000 004 008 00c 010 014 018 01c 020 024 028 02c 030 034 038 03c
+ 040 044 048 04c 050 054 058 05c 060 064 068 06c 070 074 078 07c
+ 080 084 088 08c 090 094 098 09c 0a0 0a4 0a8 0ac 0b0 0b4 0b8 0bc
+ 0c0 0c4 0c8 0cc 0d0 0d4 0d8 0dc 0e0 0e4 0e8 0ec 0f0 0f4 0f8 0fc
+ 100 104 108 10c 110 114 118 11c 120 124 128 12c 130 134 138 13c
+ 140 144 148 14c 150 154 158 15c 160 164 168 16c 170 174 178 17c
+ 180 184 188 18c 190 194 198 19c 1a0 1a4 1a8 1ac 1b0 1b4 1b8 1bc
+ 1c0 1c4 1c8 1cc 1d0 1d4 1d8 1dc 1e0 1e4 1e8 1ec 1f0 1f4 1f8 1fc
+ 200 204 208 20c 210 214 218 21c 220 224 228 22c 230 234 238 23c
+ 240 244 248 24c 250 254 258 25c 260 264 268 26c 270 274 278 27c
+ 280 284 288 28c 290 294 298 29c 2a0 2a4 2a8 2ac 2b0 2b4 2b8 2bc
+ 2c0 2c4 2c8 2cc 2d0 2d4 2d8 2dc 2e0 2e4 2e8 2ec 2f0 2f4 2f8 2fc
+ 300 304 308 30c 310 314 318 31c 320 324 328 32c 330 334 338 33c
+ 340 344 348 34c 350 354 358 35c 360 364 368 36c 370 374 378 37c
+ 380 384 388 38c 390 394 398 39c 3a0 3a4 3a8 3ac 3b0 3b4 3b8 3bc
+ 3c0 3c4 3c8 3cc 3d0 3d4 3d8 3dc 3e0 3e4 3e8 3ec 3f0 3f4 3f8 3fc
+ 3ff
+
+ 000 004 008 00c 010 014 018 01c 020 024 028 02c 030 034 038 03c
+ 040 044 048 04c 050 054 058 05c 060 064 068 06c 070 074 078 07c
+ 080 084 088 08c 090 094 098 09c 0a0 0a4 0a8 0ac 0b0 0b4 0b8 0bc
+ 0c0 0c4 0c8 0cc 0d0 0d4 0d8 0dc 0e0 0e4 0e8 0ec 0f0 0f4 0f8 0fc
+ 100 104 108 10c 110 114 118 11c 120 124 128 12c 130 134 138 13c
+ 140 144 148 14c 150 154 158 15c 160 164 168 16c 170 174 178 17c
+ 180 184 188 18c 190 194 198 19c 1a0 1a4 1a8 1ac 1b0 1b4 1b8 1bc
+ 1c0 1c4 1c8 1cc 1d0 1d4 1d8 1dc 1e0 1e4 1e8 1ec 1f0 1f4 1f8 1fc
+ 200 204 208 20c 210 214 218 21c 220 224 228 22c 230 234 238 23c
+ 240 244 248 24c 250 254 258 25c 260 264 268 26c 270 274 278 27c
+ 280 284 288 28c 290 294 298 29c 2a0 2a4 2a8 2ac 2b0 2b4 2b8 2bc
+ 2c0 2c4 2c8 2cc 2d0 2d4 2d8 2dc 2e0 2e4 2e8 2ec 2f0 2f4 2f8 2fc
+ 300 304 308 30c 310 314 318 31c 320 324 328 32c 330 334 338 33c
+ 340 344 348 34c 350 354 358 35c 360 364 368 36c 370 374 378 37c
+ 380 384 388 38c 390 394 398 39c 3a0 3a4 3a8 3ac 3b0 3b4 3b8 3bc
+ 3c0 3c4 3c8 3cc 3d0 3d4 3d8 3dc 3e0 3e4 3e8 3ec 3f0 3f4 3f8 3fc
+ 3ff
+
+ 000 004 008 00c 010 014 018 01c 020 024 028 02c 030 034 038 03c
+ 040 044 048 04c 050 054 058 05c 060 064 068 06c 070 074 078 07c
+ 080 084 088 08c 090 094 098 09c 0a0 0a4 0a8 0ac 0b0 0b4 0b8 0bc
+ 0c0 0c4 0c8 0cc 0d0 0d4 0d8 0dc 0e0 0e4 0e8 0ec 0f0 0f4 0f8 0fc
+ 100 104 108 10c 110 114 118 11c 120 124 128 12c 130 134 138 13c
+ 140 144 148 14c 150 154 158 15c 160 164 168 16c 170 174 178 17c
+ 180 184 188 18c 190 194 198 19c 1a0 1a4 1a8 1ac 1b0 1b4 1b8 1bc
+ 1c0 1c4 1c8 1cc 1d0 1d4 1d8 1dc 1e0 1e4 1e8 1ec 1f0 1f4 1f8 1fc
+ 200 204 208 20c 210 214 218 21c 220 224 228 22c 230 234 238 23c
+ 240 244 248 24c 250 254 258 25c 260 264 268 26c 270 274 278 27c
+ 280 284 288 28c 290 294 298 29c 2a0 2a4 2a8 2ac 2b0 2b4 2b8 2bc
+ 2c0 2c4 2c8 2cc 2d0 2d4 2d8 2dc 2e0 2e4 2e8 2ec 2f0 2f4 2f8 2fc
+ 300 304 308 30c 310 314 318 31c 320 324 328 32c 330 334 338 33c
+ 340 344 348 34c 350 354 358 35c 360 364 368 36c 370 374 378 37c
+ 380 384 388 38c 390 394 398 39c 3a0 3a4 3a8 3ac 3b0 3b4 3b8 3bc
+ 3c0 3c4 3c8 3cc 3d0 3d4 3d8 3dc 3e0 3e4 3e8 3ec 3f0 3f4 3f8 3fc
+ 3ff
+
\ No newline at end of file
diff --git a/input_data/motor.dat b/input_data/motor.dat
new file mode 100644
index 0000000000000000000000000000000000000000..e3b33b45dc86a0243526ee953bfed4337527d279
--- /dev/null
+++ b/input_data/motor.dat
@@ -0,0 +1,64 @@
+88888888 88888888 88888888 88888888 88888888 88888888 88888888 88888888
+ffffffff ffffffff eeeeeeef fdddddde 11257777 bbbaa990 dddccccc fddddddd
+ffffffff ffffffff ffffffff ffffffff 99126777 eeddccba fffffffe ffffffff
+ffffffff ffffffff ffffffff ffffffff ba914777 ffffeedc ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff dba03777 fffffffd ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff edb91777 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff feda1777 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffeb0777 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffd9577 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffea477 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffb377 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffc277 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffc277 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffd177 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffe177 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffff077 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffff977 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffff977 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffff977 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffffa77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffffb77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffffb77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffffc77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffffd77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffffd77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff fffffe77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffff77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffff77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffff77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffff77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffff77 ffffffff ffffffff ffffffff
+ffffffff ffffffff ffffffff ffffffff ffffff77 ffffffff ffffffff ffffffff
+88888888 88888888 88888888 88888888 88888888 88888888 88888888 88888888
+99adffff 33322110 55544444 75555555 77777777 77777777 66666667 75555556
+119aefff 66554432 77777776 77777777 77777777 77777777 77777777 77777777
+3219cfff 77776654 77777777 77777777 77777777 77777777 77777777 77777777
+5320bfff 77777775 77777777 77777777 77777777 77777777 77777777 77777777
+65319fff 77777777 77777777 77777777 77777777 77777777 77777777 77777777
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diff --git a/input_data/quantization_100.dat b/input_data/quantization_100.dat
new file mode 100644
index 0000000000000000000000000000000000000000..19abce88fa0a8676690f1b38aed55b2a630c3438
--- /dev/null
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diff --git a/input_data/sensor.dat b/input_data/sensor.dat
new file mode 100644
index 0000000000000000000000000000000000000000..eddb199c564a986786a15ec682a687a2e4b05f2c
--- /dev/null
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+2ca 3f9 350 2b9 2da 31d 122 06a 14b 23e 165 3ae 057 390 30a 2f3 30a 2f3 141 3e2 26a 354 3ce 273 109 179 055 0fc 217 155 0aa 13d 0aa 13d 224 276 2f7 0d1 1e9 071 22a 0cb 240 397 12f 353 0e4 1fe 0e4 1fe 24d 179 376 2b7 206 2a6 3e2 298 3fb 103 113 32c 2ca 3f9
+3af 27e 30f 0ef 3dc 12c 3ba 258 265 243 35a 3c5 237 385 270 2f3 270 2f3 2bf 1dd 11c 152 398 1ca 2e8 032 330 360 20f 001 0eb 3af 0eb 3af 0b0 246 129 14e 335 041 39d 1c7 351 058 310 146 04f 3f1 04f 3f1 137 12f 2f9 044 124 200 3b9 167 092 032 0ac 0f6 3af 27e
+19d 1e7 1a7 29a 27f 258 0fa 04b 371 275 0c7 171 358 1b6 320 319 320 319 055 38d 0af 0ad 34a 167 3f7 157 2c3 399 088 32a 3b5 286 3b5 286 095 20c 37c 169 1aa 096 381 36f 25b 32e 2b1 1f6 383 289 383 289 2ba 119 1dc 3ae 2ab 21f 141 323 063 1b5 145 3bd 19d 1e7
+194 335 018 0ba 3c2 3a1 1e3 343 16d 3d5 2ae 1b1 0ba 325 218 063 218 063 305 1f3 222 265 3e6 248 138 1e9 010 2a7 283 3d0 208 2c2 208 2c2 2d2 2c6 2f1 220 247 271 2d5 2c5 05e 11a 113 263 380 2c6 380 2c6 3d6 239 121 1f4 39b 002 17a 0cc 06c 28e 3e0 081 194 335
+095 369 363 050 0a7 207 376 040 15a 361 20d 187 35d 0d0 05a 3d3 05a 3d3 3cd 20d 277 37b 26b 16e 3a9 2e9 016 18a 0fe 2f2 0e3 162 0e3 162 069 176 086 074 20e 2d0 29b 0c8 25a 31a 337 38d 146 1a8 146 1a8 18b 18e 1c6 018 0f4 0ab 164 362 1ae 3bb 17c 043 095 369
+39e 381 086 25a 22d 289 2b1 042 038 21a 3e5 1f2 041 3b9 2e4 267 2e4 267 3af 0dc 2ad 0ed 3d8 3d9 04c 155 3d4 142 0fa 192 148 368 148 368 259 31b 13c 166 1fe 2b5 3d2 278 14f 22f 21b 274 1d5 02f 1d5 02f 0d9 018 0cd 319 3b6 119 1ff 3e4 129 23e 318 001 39e 381
+3b0 07e 082 3d9 154 229 095 049 308 100 137 3f2 065 0de 2b8 121 2b8 121 3a9 361 3c4 3bc 12f 289 01f 22f 04c 2cf 377 0af 036 1d3 036 1d3 1a2 0b4 213 1f4 317 31e 37a 0d4 23d 359 2c0 018 22d 35b 22d 35b 2c0 2d7 334 3f6 0e2 24b 04b 354 3dd 315 1b6 0bc 3b0 07e
+1cb 360 058 1cd 31b 1e6 223 155 2c8 113 301 086 0cb 141 0d4 0ff 0d4 0ff 0bd 29a 2bc 0e8 36f 27e 024 275 27d 331 175 149 2ad 1a3 2ad 1a3 344 343 00b 320 259 10d 292 0de 224 399 227 179 34e 02c 34e 02c 040 2cb 1fd 3b1 176 143 148 2b1 2cb 342 254 374 1cb 360
+2f0 128 106 136 084 2c0 059 066 079 354 245 0b0 272 1e0 23a 303 23a 303 3e9 388 095 171 397 0b9 159 329 367 368 3f4 060 1ac 3d7 1ac 3d7 03e 3c6 025 1e8 0c4 180 21c 395 204 3ed 14e 397 238 3a2 238 3a2 259 0f4 226 349 273 300 1f6 2fb 2f1 3c3 1f4 12a 2f0 128
+01d 2d4 38d 314 28e 1b7 039 27c 11b 0c1 001 16f 25a 3bd 3e8 02b 3e8 02b 22f 32c 24f 257 2a9 238 0c0 149 009 074 3f4 2f3 235 171 235 171 192 33f 35f 34d 358 178 317 1f8 2dd 156 136 372 3eb 2bd 3eb 2bd 20b 251 0b1 3bd 0d9 081 355 132 150 19a 194 2dc 01d 2d4
+253 165 0ee 067 238 3cb 2c1 096 1af 25b 137 3c2 183 3d6 2e0 179 2e0 179 08e 284 0ea 09a 1a3 3fc 357 1d7 165 355 275 204 147 370 147 370 03f 2ad 2ba 050 314 1f6 283 109 1af 0d4 2e0 20a 167 27e 167 27e 056 3e4 29c 20f 1a8 2c8 265 256 2e8 1c5 236 18b 253 165
+292 1dc 227 22f 084 1fc 0f2 3b6 333 122 2e5 0ab 0ed 32d 020 3eb 020 3eb 005 292 166 13a 187 305 220 1d1 07a 10b 077 292 3e2 2d4 3e2 2d4 145 30f 336 1ef 0fa 3f8 160 1c7 37a 367 34a 05f 3ac 3e3 3ac 3e3 23a 2ac 0e9 33d 1e0 2d4 026 367 0b9 146 0d9 238 292 1dc
+
+
+
diff --git a/memctrl/mcntrl393.v b/memctrl/mcntrl393.v
index 7dba3e7bed6b908de24ce027cc3b27034404adc5..04916efd8d0da9118c00525d5e8b8936d67c3913 100644
--- a/memctrl/mcntrl393.v
+++ b/memctrl/mcntrl393.v
@@ -224,7 +224,19 @@ module mcntrl393 #(
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter BUFFER_DEPTH32= 10, // Block RAM buffer depth on a 32-bit port
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
- parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
+ parameter WSEL= 1'b0, // late/early WRITE commands (to adjust timing by 1 SDCLK period)
+ // bits in mode control word
+ parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
+ parameter MCONTR_LINTILE_EN = 1, // enable requests
+ parameter MCONTR_LINTILE_WRITE = 2, // write to memory mode
+ parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
+ parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
+ parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
+ parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
+ parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
+ parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
+ parameter MCONTR_LINTILE_REPEAT = 10 // read/write pages until disabled
+
) (
input rst_in,
input clk_in,
@@ -1030,7 +1042,15 @@ module mcntrl393 #(
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCONTR_SENS_STATUS_BASE + MCONTR_SENS_STATUS_INC * i),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
- .MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
+ .MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
+ .MCONTR_LINTILE_NRESET (MCONTR_LINTILE_NRESET),
+ .MCONTR_LINTILE_EN (MCONTR_LINTILE_EN),
+ .MCONTR_LINTILE_WRITE (MCONTR_LINTILE_WRITE),
+ .MCONTR_LINTILE_EXTRAPG (MCONTR_LINTILE_EXTRAPG),
+ .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
+ .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
+ .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
+ .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
) mcntrl_linear_wr_sensor_i (
.mrst (mrst), // input
.mclk (mclk), // input
@@ -1082,7 +1102,17 @@ module mcntrl393 #(
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCONTR_CMPRS_STATUS_BASE + MCONTR_CMPRS_STATUS_INC * i),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
- .MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
+ .MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
+ .MCONTR_LINTILE_NRESET (MCONTR_LINTILE_NRESET),
+ .MCONTR_LINTILE_EN (MCONTR_LINTILE_EN),
+ .MCONTR_LINTILE_WRITE (MCONTR_LINTILE_WRITE),
+ .MCONTR_LINTILE_EXTRAPG (MCONTR_LINTILE_EXTRAPG),
+ .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
+ .MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN),
+ .MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
+ .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
+ .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
+ .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
) mcntrl_tiled_rd_compressor_i (
.mrst (mrst), // input
.mclk (mclk), // input
@@ -1143,7 +1173,15 @@ module mcntrl393 #(
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
- .MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
+ .MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
+ .MCONTR_LINTILE_NRESET (MCONTR_LINTILE_NRESET),
+ .MCONTR_LINTILE_EN (MCONTR_LINTILE_EN),
+ .MCONTR_LINTILE_WRITE (MCONTR_LINTILE_WRITE),
+ .MCONTR_LINTILE_EXTRAPG (MCONTR_LINTILE_EXTRAPG),
+ .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
+ .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
+ .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
+ .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
) mcntrl_linear_rw_chn1_i (
.mrst (mrst), // input
.mclk (mclk), // input
@@ -1193,7 +1231,15 @@ module mcntrl393 #(
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
- .MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
+ .MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
+ .MCONTR_LINTILE_NRESET (MCONTR_LINTILE_NRESET),
+ .MCONTR_LINTILE_EN (MCONTR_LINTILE_EN),
+ .MCONTR_LINTILE_WRITE (MCONTR_LINTILE_WRITE),
+ .MCONTR_LINTILE_EXTRAPG (MCONTR_LINTILE_EXTRAPG),
+ .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
+ .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
+ .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
+ .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
) mcntrl_linear_rw_chn3_i (
.mrst (mrst), // input
.mclk (mclk), // input
@@ -1245,7 +1291,16 @@ module mcntrl393 #(
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_CHN2_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
- .MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
+ .MCONTR_LINTILE_NRESET (MCONTR_LINTILE_NRESET),
+ .MCONTR_LINTILE_EN (MCONTR_LINTILE_EN),
+ .MCONTR_LINTILE_WRITE (MCONTR_LINTILE_WRITE),
+ .MCONTR_LINTILE_EXTRAPG (MCONTR_LINTILE_EXTRAPG),
+ .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
+ .MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN),
+ .MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
+ .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
+ .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
+ .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
) mcntrl_tiled_rw_chn2_i (
.mrst (mrst), // input
.mclk (mclk), // input
@@ -1301,7 +1356,16 @@ module mcntrl393 #(
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
- .MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
+ .MCONTR_LINTILE_NRESET (MCONTR_LINTILE_NRESET),
+ .MCONTR_LINTILE_EN (MCONTR_LINTILE_EN),
+ .MCONTR_LINTILE_WRITE (MCONTR_LINTILE_WRITE),
+ .MCONTR_LINTILE_EXTRAPG (MCONTR_LINTILE_EXTRAPG),
+ .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
+ .MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN),
+ .MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
+ .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
+ .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
+ .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
) mcntrl_tiled_rw_chn4_i (
.mrst (mrst), // input
.mclk (mclk), // input
diff --git a/memctrl/mcntrl_linear_rw.v b/memctrl/mcntrl_linear_rw.v
index cbd0ea03dae2f930c27a121492fed1163361ccf6..cda2e4c2b0ef6bfce833d619997a7b559372e197 100644
--- a/memctrl/mcntrl_linear_rw.v
+++ b/memctrl/mcntrl_linear_rw.v
@@ -47,8 +47,16 @@ module mcntrl_linear_rw #(
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
- parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)
-// parameter MCNTRL_SCANLINE_WRITE_MODE = 1'b0 // module is configured to write tiles to external memory (false - read tiles)
+ parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
+ // bits in mode control word
+ parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
+ parameter MCONTR_LINTILE_EN = 1, // enable requests
+ parameter MCONTR_LINTILE_WRITE = 2, // write to memory mode
+ parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
+ parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
+ parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
+ parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
+ parameter MCONTR_LINTILE_REPEAT = 10 // read/write pages until disabled
)(
input mrst,
input mclk,
@@ -214,8 +222,8 @@ module mcntrl_linear_rw #(
assign set_window_x0y0_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_X0Y0);
assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_STARTXY);
- assign single_frame_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[9];
- assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[8];
+ assign single_frame_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_SINGLE];
+ assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
// Set parameter registers
always @(posedge mclk) begin
@@ -318,11 +326,11 @@ module mcntrl_linear_rw #(
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished=line_unfinished_r[1];
- assign chn_en = &mode_reg[1:0]; // enable requests by channel (continue ones in progress)
- assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
- assign cmd_wrmem = mode_reg[2];// 0: read from memory, 1:write to memory
- assign cmd_extra_pages = mode_reg[4:3]; // external module needs more than 1 page
- assign repeat_frames= mode_reg[10];
+ assign chn_en = mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN]; // enable requests by channel (continue ones in progress)
+ assign chn_rst = ~mode_reg[MCONTR_LINTILE_NRESET]; // resets command, including fifo;
+ assign cmd_wrmem = mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory
+ assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
+ assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we;
diff --git a/memctrl/mcntrl_tiled_rw.v b/memctrl/mcntrl_tiled_rw.v
index 5311c83063fa37a7706c379b1fddcac90c5a9c0e..2c747da0439e7ff29cc92924e3b6a3d31a168a9d 100644
--- a/memctrl/mcntrl_tiled_rw.v
+++ b/memctrl/mcntrl_tiled_rw.v
@@ -52,8 +52,18 @@ module mcntrl_tiled_rw#(
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
- parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)
-// parameter MCNTRL_TILED_WRITE_MODE = 1'b0 // module is configured to write tiles to external memory (false - read tiles)
+ parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
+ // bits in mode control word
+ parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
+ parameter MCONTR_LINTILE_EN = 1, // enable requests
+ parameter MCONTR_LINTILE_WRITE = 2, // write to memory mode
+ parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
+ parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
+ parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
+ parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
+ parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
+ parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
+ parameter MCONTR_LINTILE_REPEAT = 10 // read/write pages until disabled
)(
input mrst,
input mclk,
@@ -244,8 +254,8 @@ module mcntrl_tiled_rw#(
assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_STARTXY);
assign set_tile_whs_w = cmd_we && (cmd_a== MCNTRL_TILED_TILE_WHS);
- assign single_frame_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[9];
- assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[8];
+ assign single_frame_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_SINGLE];
+ assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
//
@@ -359,14 +369,14 @@ module mcntrl_tiled_rw#(
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished=line_unfinished_r[1];
- assign chn_en = &mode_reg[1:0]; // enable requests by channel (continue ones in progress)
- assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
- assign cmd_wrmem = mode_reg[2];// 0: read from memory, 1:write to memory
- assign cmd_extra_pages = mode_reg[4:3]; // external module needs more than 1 page
- assign keep_open= mode_reg[5]; // keep banks open (will be used only if number of rows <= 8
- assign byte32= mode_reg[6]; // use 32-byte wide columns in each tile (false - 16-byte)
- assign repeat_frames= mode_reg[10];
-
+
+ assign chn_en = mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN]; // enable requests by channel (continue ones in progress)
+ assign chn_rst = ~mode_reg[MCONTR_LINTILE_NRESET]; // resets command, including fifo;
+ assign cmd_wrmem = mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory
+ assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
+ assign keep_open= mode_reg[MCONTR_LINTILE_KEEP_OPEN]; // keep banks open (will be used only if number of rows <= 8
+ assign byte32= mode_reg[MCONTR_LINTILE_BYTE32]; // use 32-byte wide columns in each tile (false - 16-byte)
+ assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign status_data= {frame_finished_r, busy_r};
assign pgm_param_w= cmd_we;
diff --git a/sensor/sens_gamma.v b/sensor/sens_gamma.v
index 3c2c59c6b967e23f7bd1a21f9d18bb5dcbba53dc..9740a6ed8971422223aa20250ca3fd88ce25fe3e 100644
--- a/sensor/sens_gamma.v
+++ b/sensor/sens_gamma.v
@@ -295,7 +295,7 @@ module sens_gamma #(
) dly_16_pxd_i (
.clk (pclk), // input
.rst (prst), // input
- .dly (3), // input[3:0]
+ .dly (4'd3), // input[3:0]
.din (pxd_in[7:0]), // input[0:0]
.dout(pxd_in_d3) // output[0:0]
);
@@ -305,7 +305,7 @@ module sens_gamma #(
) dly_16_sof_eof_i (
.clk (pclk), // input
.rst (prst), // input
- .dly (4), // input[3:0]
+ .dly (4'd4), // input[3:0]
.din ({eof_in, sof_masked}), // input[0:0]
.dout({eof_out,sof_out}) // output[0:0]
);
diff --git a/simulation_modules/simul_axi_hp_rd.v b/simulation_modules/simul_axi_hp_rd.v
index e21256be7bc848c6c213ca814a34392ca5b5302b..9017ac20cdb0d09a054b64d6d3b64d9e771f1146 100644
--- a/simulation_modules/simul_axi_hp_rd.v
+++ b/simulation_modules/simul_axi_hp_rd.v
@@ -36,7 +36,7 @@ module simul_axi_hp_rd #(
input [ 3:0] arcache,
input [ 2:0] arprot,
input [ 3:0] arlen,
- input [ 2:0] arsize,
+ input [ 1:0] arsize,
input [ 1:0] arburst,
input [ 3:0] arqos,
// read data
@@ -104,7 +104,7 @@ module simul_axi_hp_rd #(
wire [5:0] arid_out; // verify it matches wid_out when outputting data
wire [1:0] arburst_out;
- wire [2:0] arsize_out; // verify it is 3'h3
+ wire [1:0] arsize_out; // verify it is 3'h3
wire [3:0] arlen_out;
wire [31:0] araddr_out;
wire ar_nempty;
@@ -197,7 +197,7 @@ module simul_axi_hp_rd #(
always @ (posedge aclk) begin
if (start_read_burst_w) begin
- if (arsize_out != 3'h3) begin
+ if (arsize_out != 2'h3) begin
$display ("%m: at time %t ERROR: arsize_out=%h, currently only 'h3 (8 bytes) is valid",$time,arsize_out);
$stop;
end
@@ -254,15 +254,15 @@ module simul_axi_hp_rd #(
end
-fifo_same_clock_fill #( .DATA_WIDTH(51),.DATA_DEPTH(2)) // read - 4, write - 32?
+fifo_same_clock_fill #( .DATA_WIDTH(50),.DATA_DEPTH(2)) // read - 4, write - 32?
raddr_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (arvalid && arready),
.re (start_read_burst_w),
- .data_in ({arid[5:0], arburst[1:0], arsize[2:0], arlen[3:0], araddr[31:0], rd_qos_in[3:0]}),
- .data_out ({arid_out[5:0], arburst_out[1:0],arsize_out[2:0],arlen_out[3:0],araddr_out[31:0], rd_qos_out[3:0]}),
+ .data_in ({arid[5:0], arburst[1:0], arsize[1:0], arlen[3:0], araddr[31:0], rd_qos_in[3:0]}),
+ .data_out ({arid_out[5:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[31:0], rd_qos_out[3:0]}),
.nempty (ar_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
diff --git a/simulation_modules/simul_axi_hp_wr.v b/simulation_modules/simul_axi_hp_wr.v
index 12216ea887a192cd7a9e741b8ed148d2f6fa5f02..4fd152f582c1eb90266fa98ef83385e22a42eaed 100644
--- a/simulation_modules/simul_axi_hp_wr.v
+++ b/simulation_modules/simul_axi_hp_wr.v
@@ -36,7 +36,7 @@ module simul_axi_hp_wr#(
input [ 3:0] awcache, // verify the corerct values are here
input [ 2:0] awprot, // verify the corerct values are here
input [ 3:0] awlen,
- input [ 2:0] awsize,
+ input [ 1:0] awsize,
input [ 1:0] awburst,
input [ 3:0] awqos, // verify the correct values are here
// write data
@@ -117,7 +117,7 @@ Alex
wire [5:0] awid_out; // verify it matches wid_out when outputting data
wire [1:0] awburst_out;
- wire [2:0] awsize_out; // verify it is 3'h3
+ wire [1:0] awsize_out; // verify it is 3'h3
wire [3:0] awlen_out;
wire [31:0] awaddr_out;
wire [5:0] wid_out;
@@ -235,7 +235,7 @@ Alex
$stop;
end
- if (awsize_out != 3'h3) begin
+ if (awsize_out != 2'h3) begin
$display ("%m: at time %t ERROR: awsize_out=%h, currently only 'h3 (8 bytes) is valid",$time,awsize_out);
$stop;
end
@@ -280,15 +280,15 @@ Alex
-fifo_same_clock_fill #( .DATA_WIDTH(51),.DATA_DEPTH(5)) // read - 4, write - 32?
+fifo_same_clock_fill #( .DATA_WIDTH(50),.DATA_DEPTH(5)) // read - 4, write - 32?
waddr_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (awvalid && awready),
.re (start_write_burst_w),
- .data_in ({awid[5:0], awburst[1:0], awsize[2:0], awlen[3:0], awaddr[31:0], wr_qos_in[3:0]}),
- .data_out ({awid_out[5:0], awburst_out[1:0],awsize_out[2:0],awlen_out[3:0],awaddr_out[31:0], wr_qos_out[3:0]}),
+ .data_in ({awid[5:0], awburst[1:0], awsize[1:0], awlen[3:0], awaddr[31:0], wr_qos_in[3:0]}),
+ .data_out ({awid_out[5:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[31:0], wr_qos_out[3:0]}),
.nempty (aw_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
diff --git a/simulation_modules/simul_clk.v b/simulation_modules/simul_clk.v
new file mode 100644
index 0000000000000000000000000000000000000000..65d3de5d35037a35377176f6976b043491b55e15
--- /dev/null
+++ b/simulation_modules/simul_clk.v
@@ -0,0 +1,79 @@
+/*******************************************************************************
+ * Module: simul_clk
+ * Date:2015-07-29
+ * Author: andrey
+ * Description: Generate clocks for simulation
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * simul_clk.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * simul_clk.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module simul_clk#(
+ parameter CLKIN_PERIOD = 5.0,
+ parameter MEMCLK_PERIOD = 5.0,
+ parameter FCLK0_PERIOD = 10.417,
+ parameter FCLK1_PERIOD = 0.0
+)(
+ input rst,
+ output clk,
+ output memclk,
+ output [1:0] ffclk0,
+ output [1:0] ffclk1
+);
+
+ wire ffclk0_w;
+ wire ffclk1_w;
+ assign ffclk0 = {~ffclk0_w,ffclk0_w};
+ assign ffclk1 = {~ffclk1_w,ffclk1_w};
+ generate
+ if (CLKIN_PERIOD > 0.0)
+ simul_clk_single #(.PERIOD(CLKIN_PERIOD)) simul_clk_i (.rst(rst), .clk(clk));
+ else
+ assign clk = 0;
+ endgenerate
+
+ generate
+ if (MEMCLK_PERIOD > 0.0)
+ simul_clk_single #(.PERIOD(MEMCLK_PERIOD)) simul_memclk_i (.rst(rst), .clk(memclk));
+ else
+ assign memclk = 0;
+ endgenerate
+
+ generate
+ if (FCLK0_PERIOD > 0.0)
+ simul_clk_single #(.PERIOD(FCLK0_PERIOD)) simul_ffclk0_i (.rst(rst), .clk(ffclk0_w));
+ else
+ assign ffclk0_w = 0;
+ endgenerate
+
+ generate
+ if (FCLK1_PERIOD > 0.0)
+ simul_clk_single #(.PERIOD(FCLK1_PERIOD)) simul_ffclk1_i (.rst(rst), .clk(ffclk1_w));
+ else
+ assign ffclk1_w = 0;
+ endgenerate
+
+endmodule
+
+module simul_clk_single #(
+ parameter PERIOD = 1000.0
+ ) (
+ input rst,
+ output clk
+ );
+ reg clk_r = 0;
+ assign clk = clk_r;
+ always #(PERIOD/2) clk_r <= rst ? 1'b0: ~clk_r;
+endmodule
diff --git a/simulation_modules/simul_sensor12bits.v b/simulation_modules/simul_sensor12bits.v
new file mode 100644
index 0000000000000000000000000000000000000000..9e1a61ce9fd2fd303540e51593c70b65b748a175
--- /dev/null
+++ b/simulation_modules/simul_sensor12bits.v
@@ -0,0 +1,274 @@
+/*******************************************************************************
+ * Module: simul_sensor12bits
+ * Date:2015-07-29
+ * Author: Andrey Filippov
+ * Description: Generate sensor data
+ *
+ * Copyright (c) 2002-2015 Elphel, Inc.
+ * simul_sensor12bits.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * simul_sensor12bits.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ *******************************************************************************/
+
+module simul_sensor12bits # (
+ parameter lline = 192, // 1664;// line duration in clocks
+ parameter ncols = 66, //58; //56; // 129; //128; //1288;
+ parameter nrows = 18, // 16; // 1032;
+ parameter nrowb = 1, // number of "blank rows" from vact to 1-st hact
+ parameter nrowa = 1, // number of "blank rows" from last hact to end of vact
+// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
+ parameter nbpf = 20, //16; // bpf length
+ parameter ngp1 = 8, // bpf to hact
+ parameter nVLO = 1, // VACT=0 in video mode (clocks)
+ //parameter tMD = 14; //
+ //parameter tDDO = 10; // some confusion here - let's assume that it is from DCLK to Data out
+ parameter tMD = 4, //
+ parameter tDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out
+ parameter tDDO1 = 5, //
+ parameter trigdly = 8, // delay between trigger input and start of output (VACT) in lines
+ parameter ramp = 1 // 1 - ramp, 0 - random (now - sensor.dat)
+
+) (
+ input MCLK, // Master clock
+ input MRST, // Master Reset - active low
+ input ARO, // Array read Out.
+ input ARST, // Array Reset. Active low
+ input OE, // output Elphel, Inc.ock
+ input SCL, // I2C data // SuppressThisWarning VEditor - not used
+ inout SDA, // I2C data// SuppressThisWarning VEditor - not used/assigned
+ input OFST, // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
+ output [11:0] D, // [11:0] data output
+ output DCLK, // Data output clock
+ output BPF, // Black Pixel Flag
+ output HACT, // Horizontal Active
+ output VACT, // Vertical Active
+ output VACT1);
+
+
+ localparam s_stop= 0;
+ localparam s_preVACT= 1;
+ localparam s_firstline= 2;
+ localparam s_BPF= 3;
+ localparam s_preHACT= 4;
+ localparam s_HACT= 5;
+ localparam s_afterHACT= 6;
+ localparam s_lastline= 7;
+ localparam s_frame_done=8;
+
+ localparam t_preVACT= lline* trigdly;
+ localparam t_firstline=nrowb*lline+1; // 1664
+ localparam t_BPF= nbpf; // 16
+ localparam t_preHACT= ngp1; // 8
+ localparam t_HACT= ncols; // 1288
+ localparam t_afterHACT=lline-nbpf-ngp1-ncols; // 352
+ localparam t_lastline= nrowa*lline+1; // 1664
+
+reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
+// $readmemh("sensor.dat",sensor_data);
+
+
+
+reg c; // internal data out clock
+//reg [9:0] id; // internal pixel data (sync do DCLK)
+//wire [9:0] nxt_d; // will be calculated later - next pixel data
+reg stopped;
+wire #1 stoppedd=stopped;
+reg ibpf, ihact, ivact, ivact1;
+reg arst1; //
+reg [11:0] col; // current row
+reg [11:0] row; // current column;
+reg [3:0] state;
+reg [15:0] cntr;
+wire [11:0] cold;
+wire [11:0] rowd;
+wire [3:0] stated;
+wire [15:0] cntrd;
+wire NMRST=!MRST;
+
+parameter new_bayer=0; // 0 - old (16x16), 1 - new (18x18)
+
+wire [5:0] row_index=row[5:0]-new_bayer;
+wire [5:0] col_index=col[5:0]-new_bayer;
+
+
+// random
+integer seed;
+integer r;
+reg c_rand;
+reg [11:0] d_rand;
+
+
+
+assign #1 cold= col;
+assign #1 rowd= row;
+assign #1 stated= state;
+assign #1 cntrd= cntr;
+
+
+
+//assign #tDDO D = OE? {10{1'bz}}: ((ihact || ibpf)? ((ramp)?(col[9:0] + row[9:0]):(d_rand)): 10'b0); // just test pattern
+//assign #tDDO D = OE? {10{1'bz}}: ((ihact || ibpf)? ((ramp)?(col[9:0] + row[9:0]):(sensor_data[{row_index[5:0],col_index[5:0]}])): 10'b0); // just test pattern
+//assign #tDDO D = OE? {12{1'bz}}: ((ihact || ibpf)? ((ramp)?(col[11:0] + row[11:0]):(sensor_data[{row_index[5:0],col_index[5:0]}])): 12'b0); // just test pattern
+assign #tDDO D = OE? {12{1'bz}}: ((ihact || ibpf)? ((ramp)?({row[11:8],8'h0} + col[11:0]):(sensor_data[{row_index[5:0],col_index[5:0]}])): 12'b0); // just test pattern
+//assign #tDDO BPF = ibpf;
+//assign #tDDO HACT= ihact;
+//assign #tDDO VACT= ivact;
+assign #tDDO1 BPF = ibpf;
+assign #tDDO1 HACT= ihact;
+assign #tDDO1 VACT= ivact;
+assign #tDDO1 VACT1= ivact && !ivact1;
+assign DCLK= c;
+
+initial begin
+//parameter ramp = 1; // 0 - ramp, 1 - random
+//parameter lline = 192; // 1664;// line duration in clocks
+//parameter ncols = 58; //56; // 129; //128; //1288;
+//parameter nrows = 16; // 1032;
+
+ $display ("sensor parameters");
+ $display (" -- ramp = %d (0 - random, 1 - ramp)",ramp);
+ $display (" -- lline = %d (line duration in clocks)",lline);
+ $display (" -- ncols = %d (numer of clocks in HACT)",ncols);
+ $display (" -- nrows = %d (number of rows)",nrows);
+ $display (" -- t_afterHACT = %d ",t_afterHACT);
+ $display (" -- t_preHACT = %d ",t_preHACT);
+ $display (" -- new_bayer = %d ",new_bayer);
+
+// reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
+ $readmemh("input_data/sensor.dat",sensor_data);
+ c=0;
+// {ibpf,ihact,ivact}=0;
+ stopped=1;
+ arst1= 0;
+ seed= 1;
+ d_rand= 0;
+// row=0;
+// col=0;
+
+end
+always @ (NMRST) begin
+ c=0;
+// {ibpf,ihact,ivact}=0;
+ stopped=1;
+ arst1=0;
+// row=0;
+// col=0;
+end
+
+always begin
+ @ (posedge MCLK) begin
+ #tMD c = !stoppedd;
+ end
+ @ (negedge MCLK) begin
+ #tMD c = 1'b0;
+ end
+end
+
+always @ (posedge MCLK) begin
+// #1 stopped= !arst1 || (stoppedd && !ARO) ;
+ #1 stopped= !arst1 || ((stoppedd || (state== s_frame_done)) && ARO) ; /// ARO tow TRIGGER, ective low
+ #1 arst1=ARST;
+end
+
+always @ (posedge c) ivact1 = ivact;
+always @ (posedge stoppedd or posedge c) begin
+ if (stoppedd) begin
+ {ibpf,ihact,ivact}=0;
+ row=0;
+ col=0;
+// id=0;
+ state=0;
+ cntr=0;
+ end else if (|cntrd != 0) begin
+ #1 cntr=cntrd-1;
+ if (BPF || HACT) col=cold+1;
+ end else begin
+ case (stated)
+ s_stop: begin
+ cntr= t_preVACT-1;
+ state= s_preVACT;
+ end
+ s_preVACT: begin
+ ivact= 1'b1;
+ cntr= t_firstline-1;
+ state= s_firstline;
+ end
+ s_firstline: begin
+ col= 0;
+ row= 0;
+ if (t_BPF>=1) begin
+ ibpf= 1'b1;
+ cntr= t_BPF-1;
+ state= s_BPF;
+ end else begin
+ ihact= 1'b1;
+ cntr= t_HACT-1;
+ state= s_HACT;
+ end
+ end
+ s_BPF: begin
+ ibpf= 1'b0;
+ cntr= t_preHACT-1;
+ state= s_preHACT;
+ end
+ s_preHACT: begin
+ ihact= 1'b1;
+ col= 0;
+ cntr= t_HACT-1;
+ state= s_HACT;
+ end
+ s_HACT: begin
+ ihact= 1'b0;
+ row= rowd+1;
+ cntr= t_afterHACT-1;
+ state= s_afterHACT;
+ end
+ s_afterHACT:
+ if (rowd == nrows) begin
+ cntr= t_lastline-1;
+ state= s_lastline;
+ end else begin
+ col= 0;
+ if (t_BPF>=1) begin
+ ibpf= 1'b1;
+ cntr= t_BPF-1;
+ state= s_BPF;
+ end else begin
+ ihact= 1'b1;
+ cntr= t_HACT-1;
+ state= s_HACT;
+ end
+ end
+ s_lastline: begin
+ ivact= 1'b0;
+ state= s_frame_done;
+ cntr=nVLO;
+ end
+ s_frame_done: if (OFST) begin
+ ivact= 1'b1;
+ cntr= t_firstline-1;
+ state= s_firstline;
+ end
+ endcase
+
+ end
+// random data
+ seed = $random(seed);
+ r = (seed & 'h7fff);
+ r= (r * r) >> 20; // 10 bits
+ c_rand = seed[16]; // >>16; // sign
+ d_rand=c_rand?(D+(((1023-d_rand)*r)>>10)):(d_rand-((d_rand*r)>>10));
+end
+
+
+
+endmodule
diff --git a/timing/camsync393.v b/timing/camsync393.v
index 5c56b13fc394c9ee845d78a63aee45c25f942a34..78f2e14c719cf961f832058cfca0fe9c6a0be34c 100644
--- a/timing/camsync393.v
+++ b/timing/camsync393.v
@@ -75,11 +75,11 @@ module camsync393 #(
// 256>=d - repetitive trigger
// 4..7 - input trigger delay (in pclk periods)
- input pclk, // pixel clock (global) - switch it to 100MHz (mclk/2)?
- input prst, // @ posedge pclk - sync reset
- input [9:0] gpio_in, // 12-bit input from GPIO pins -> 10 bit
- output [9:0] gpio_out,// 12-bit output to GPIO pins
- output reg [9:0] gpio_out_en,// 12-bit output enable to GPIO pins
+ input pclk, // pixel clock (global) - switch it to 100MHz (mclk/2)?
+ input prst, // @ posedge pclk - sync reset
+ input [9:0] gpio_in, // 10-bit input from GPIO pins -> 10 bit
+ output [9:0] gpio_out, // 10-bit output to GPIO pins
+ output reg [9:0] gpio_out_en, // 10-bit output enable to GPIO pins
output triggered_mode, // use triggered mode (0 - sensors are free-running) @mclk
diff --git a/timing/timing393.v b/timing/timing393.v
index df854f9b4aae455ce58e9badae80f8ca4adcdf0b..5e02f20f8b4295ce0846d21211e303c47f092066 100644
--- a/timing/timing393.v
+++ b/timing/timing393.v
@@ -66,16 +66,16 @@ module timing393 #(
input status_start, // Acknowledge of the first status packet byte (address)
// connection to the general purpose I/O control
- input [9:0] gpio_in, // 12-bit input from GPIO pins -> 10 bit
- output [9:0] gpio_out,// 12-bit output to GPIO pins
- output [9:0] gpio_out_en,// 12-bit output enable to GPIO pins
+ input [9:0] gpio_in, // 10-bit input from GPIO pins -> 10 bit
+ output [9:0] gpio_out, // 10-bit output to GPIO pins
+ output [9:0] gpio_out_en, // 10-bit output enable to GPIO pins
// common for all sensors - use triggered mode (as opposed to a free-running mode)
output triggered_mode, // use triggered mode (0 - sensors are free-running) @mclk - common to all sensors
// per-channel frame sync inputs and trigger outputs. Both single-cycle mclk pulses
- input frsync_chn0, // @mclk trigrst, // single-clock start of frame input (resets trigger output) posedge (@pclk)
- output trig_chn0, // @mclk 1 cycle-long trigger output
+ input frsync_chn0, // @mclk trigrst, // single-clock start of frame input (resets trigger output) posedge (@pclk)
+ output trig_chn0, // @mclk 1 cycle-long trigger output
input frsync_chn1, // @mclk trigrst, // single-clock start of frame input (resets trigger output) posedge (@pclk)
output trig_chn1, // 1 cycle-long trigger output
diff --git a/util_modules/level_cross_clocks.v b/util_modules/level_cross_clocks.v
index 46c3a5d228d0f2d39aad31456801a000b06d8dbb..361dfcf0f62e9662dfe9bcab01ed67320b619740 100644
--- a/util_modules/level_cross_clocks.v
+++ b/util_modules/level_cross_clocks.v
@@ -56,17 +56,18 @@ module level_cross_clocks#(
endmodule
module level_cross_clocks_single_bit#(
- parameter REGISTER = 3 // number of registers (>3)
+ parameter REGISTER = 3 // number of registers (>=3)
)(
input clk,
input d_in,
output d_out
);
- reg [REGISTER - 3 : 0] regs;
- wire d_sync; // after a 2-bit synchronizer
+ reg [REGISTER - 3 : 0] regs = 0;
+ wire d_sync; // after a 2-bit synchronizer
+ wire [REGISTER - 2 : 0] regs_next = {regs, d_sync};
assign d_out = regs[REGISTER -3];
always @ (posedge clk) begin
- regs <= (regs << 1) + d_sync; // | d_in complains about widths mismatch
+ regs <= regs_next[REGISTER - 3 : 0]; // | d_in complains about widths mismatch
end
level_cross_clocks_sync_bit level_cross_clocks_sync_bit_i (
.clk (clk), // input
diff --git a/util_modules/sync_resets.v b/util_modules/sync_resets.v
index 0f29a9029cc022ed1990f2c15f23a6e94b431abd..426a0cbddc1486131da28ce7b69294e7e47c5743 100644
--- a/util_modules/sync_resets.v
+++ b/util_modules/sync_resets.v
@@ -30,13 +30,18 @@ module sync_resets#(
input [WIDTH-1:0] clk, // clk[0] - master clock generation should not depend on resets)
output [WIDTH-1:0] rst // resets matching input clocks
);
+ reg en_locked=0; // mostly for simulation, locked[0] is 1'bx until the first clock[0] pulse
wire [WIDTH-1:0] rst_w; // resets matching input clocks
wire rst_early_master;
assign rst = rst_w;
reg mrst = 1;
always @ (posedge arst or posedge clk[0]) begin
+
+ if (arst) en_locked <= 0;
+ else en_locked <= 1;
+
if (arst) mrst <= 1;
- else mrst <= ~locked[0];
+ else mrst <= ~(locked[0] && en_locked);
end
level_cross_clocks #(
.WIDTH (1),
diff --git a/util_modules/table_ad_transmit.v b/util_modules/table_ad_transmit.v
index 4ecd8394a70ff00b7bb3c072c5c3d86d32cfbe1f..0dcdbf7d29a23805536819f39b3819d6a4dca2cb 100644
--- a/util_modules/table_ad_transmit.v
+++ b/util_modules/table_ad_transmit.v
@@ -60,7 +60,7 @@ module table_ad_transmit#(
if (we && a_not_d_in) sel_a <= din[24+:ADDR_BITS];
end
- dly_16 #(.WIDTH(1)) i_end_burst(.clk(clk),.rst(1'b0), .dly(2), .din(we), .dout(we3)); // dly=2+1=3
+ dly_16 #(.WIDTH(1)) i_end_burst(.clk(clk),.rst(1'b0), .dly(4'd2), .din(we), .dout(we3)); // dly=2+1=3
genvar i;
generate
diff --git a/wrap/oserdes_mem.v b/wrap/oserdes_mem.v
index 12dff128410ad0fad5c15cd68148055e98fd674a..79451edb827c65942cc09a1fba73c87a99ac68c2 100644
--- a/wrap/oserdes_mem.v
+++ b/wrap/oserdes_mem.v
@@ -46,7 +46,7 @@ localparam integer DATA_WIDTH_TRI= (MODE_DDR=="TRUE")?4:1;
seems to be OK.
*/
-`ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )
+`ifndef OPEN_SOURCE_ONLY // Not using simulator - instanciate actual ISERDESE2 (can not be simulated because of encrypted )
OSERDESE2 #(
.DATA_RATE_OQ (DATA_RATE),
.DATA_RATE_TQ (DATA_RATE),
diff --git a/x393.v b/x393.v
index 225dad39464688fd2349e2048ca1a131ee796c1f..d961b348d8bbebb29e75a87885d962522b2eec0c 100644
--- a/x393.v
+++ b/x393.v
@@ -1050,6 +1050,16 @@ assign axi_grst = axi_rst_pre;
.MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS (MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
+ .MCONTR_LINTILE_NRESET (MCONTR_LINTILE_NRESET),
+ .MCONTR_LINTILE_EN (MCONTR_LINTILE_EN),
+ .MCONTR_LINTILE_WRITE (MCONTR_LINTILE_WRITE),
+ .MCONTR_LINTILE_EXTRAPG (MCONTR_LINTILE_EXTRAPG),
+ .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
+ .MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN),
+ .MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
+ .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
+ .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
+ .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.BUFFER_DEPTH32 (BUFFER_DEPTH32),
.RSEL (RSEL),
.WSEL (WSEL)
@@ -1833,7 +1843,7 @@ assign axi_grst = axi_rst_pre;
.status_rq (status_timing_rq), // output
.status_start (status_timing_start), // input
.gpio_in (gpio_rd), // input[9:0]
- .gpio_out (gpio_camsync), // output[9:0]
+ .gpio_out (gpio_camsync), // output[9:0] ([6]-synco0,[7]-syncio0,[8]-synco1,[9]-syncio1)
.gpio_out_en (gpio_camsync_en), // output[9:0]
.triggered_mode (trigger_mode), // output
.frsync_chn0 (sof_out_mclk[0]), // input
diff --git a/x393_testbench01.sav b/x393_testbench01.sav
index 86729749f282650c643e81313b7333d87a1969a8..3352302162ace7324d66d9f20df5aeb2b2b3bed1 100644
--- a/x393_testbench01.sav
+++ b/x393_testbench01.sav
@@ -1,29 +1,34 @@
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
-[*] Wed May 6 00:35:07 2015
+[*] Sat Aug 1 01:57:02 2015
[*]
-[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150505182137719.lxt"
-[dumpfile_mtime] "Wed May 6 00:29:43 2015"
-[dumpfile_size] 496570537
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150731124427127.lxt"
+[dumpfile_mtime] "Fri Jul 31 19:02:35 2015"
+[dumpfile_size] 1073757835
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
-[timestart] 38860800
+[timestart] 38799000
[size] 1823 1180
[pos] 1919 0
-*-16.063198 39110000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-18.877661 39967388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.ddr3_i.
-[treeopen] x393_testbench01.simul_axi_hp_wr_i.
[treeopen] x393_testbench01.x393_i.
-[treeopen] x393_testbench01.x393_i.axibram_write_i.
-[treeopen] x393_testbench01.x393_i.cmd_mux_i.
-[treeopen] x393_testbench01.x393_i.membridge_i.
+[treeopen] x393_testbench01.x393_i.mcntrl393_i.
+[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
+[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
+[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
+[treeopen] x393_testbench01.x393_i.sync_resets_i.
+[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.
+[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].
+[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.
+[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.
[sst_width] 363
[signals_width] 446
[sst_expanded] 1
[sst_vpaned_height] 550
@820
x393_testbench01.TEST_TITLE[639:0]
-@c00200
+@800200
-DDR3
@28
x393_testbench01.SDRST[0]
@@ -40,15 +45,17 @@ x393_testbench01.DQSL[0]
x393_testbench01.DQSU[0]
@22
x393_testbench01.SDD[15:0]
-@1401200
+@1000200
-DDR3
-@800200
+@c00200
-top
@28
+x393_testbench01.CLK[0]
x393_testbench01.RST[0]
x393_testbench01.HCLK[0]
-x393_testbench01.CLK[0]
-@1000200
+x393_testbench01.memclk[0]
+x393_testbench01.ffclk0p[0]
+@1401200
-top
@800200
-PS
@@ -102,8 +109,6 @@ x393_testbench01.simul_axi_hp_wr_i.awprot[2:0]
x393_testbench01.simul_axi_hp_wr_i.awqos[3:0]
@28
x393_testbench01.simul_axi_hp_wr_i.awready[0]
-x393_testbench01.simul_axi_hp_wr_i.awsize[2:0]
-x393_testbench01.simul_axi_hp_wr_i.awsize_out[2:0]
x393_testbench01.simul_axi_hp_wr_i.awvalid[0]
@22
x393_testbench01.simul_axi_hp_wr_i.bid[5:0]
@@ -222,8 +227,6 @@ x393_testbench01.simul_axi_hp_rd_i.arprot[2:0]
x393_testbench01.simul_axi_hp_rd_i.arqos[3:0]
@28
x393_testbench01.simul_axi_hp_rd_i.arready[0]
-x393_testbench01.simul_axi_hp_rd_i.arsize[2:0]
-x393_testbench01.simul_axi_hp_rd_i.arsize_out[2:0]
x393_testbench01.simul_axi_hp_rd_i.arvalid[0]
@22
x393_testbench01.simul_axi_hp_rd_i.fifo_data_rd[0]
@@ -302,7 +305,7 @@ x393_testbench01.simul_axi_hp_rd_i.was_data_fifo_read[0]
x393_testbench01.simul_axi_hp_rd_i.was_data_fifo_write[0]
@1401200
-simul_afi_rd
-@800200
+@c00200
-membridge
@28
x393_testbench01.x393_i.membridge_i.afi_rvalid[0]
@@ -312,11 +315,11 @@ x393_testbench01.x393_i.membridge_i.afi_rd_safe_not_empty[0]
x393_testbench01.x393_i.membridge_i.afi_rcount[7:0]
@28
x393_testbench01.x393_i.membridge_i.bufwr_we_w[0]
-@23
+@22
x393_testbench01.x393_i.membridge_i.bufwr_we[3:0]
-@800200
+@c00200
-x393_testbench01.x393_i.membridge_i.bufwr_we
-@1001200
+@1401200
-group_end
@200
-
@@ -356,9 +359,9 @@ x393_testbench01.x393_i.membridge_i.afi_arlen[3:0]
x393_testbench01.x393_i.membridge_i.afi_arvalid[0]
x393_testbench01.x393_i.membridge_i.afi_rvalid[0]
x393_testbench01.x393_i.membridge_i.afi_rready[0]
-@800200
+@c00200
-x393_testbench01.x393_i.membridge_i.bufwr_we
-@1001200
+@1401200
-group_end
@28
x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_we[0]
@@ -469,7 +472,6 @@ x393_testbench01.x393_i.membridge_i.afi_arprot[2:0]
x393_testbench01.x393_i.membridge_i.afi_arqos[3:0]
@28
x393_testbench01.x393_i.membridge_i.afi_arready[0]
-x393_testbench01.x393_i.membridge_i.afi_arsize[2:0]
x393_testbench01.x393_i.membridge_i.afi_arvalid[0]
@22
x393_testbench01.x393_i.membridge_i.afi_awaddr[31:0]
@@ -486,7 +488,6 @@ x393_testbench01.x393_i.membridge_i.afi_awprot[2:0]
x393_testbench01.x393_i.membridge_i.afi_awqos[3:0]
@28
x393_testbench01.x393_i.membridge_i.afi_awready[0]
-x393_testbench01.x393_i.membridge_i.afi_awsize[2:0]
x393_testbench01.x393_i.membridge_i.afi_awvalid[0]
@22
x393_testbench01.x393_i.membridge_i.afi_bid[5:0]
@@ -633,7 +634,6 @@ x393_testbench01.x393_i.membridge_i.rel_addr64[28:0]
x393_testbench01.x393_i.membridge_i.reset_page_rd[0]
x393_testbench01.x393_i.membridge_i.reset_page_wr[0]
x393_testbench01.x393_i.membridge_i.rollover[0]
-x393_testbench01.x393_i.membridge_i.rst[0]
x393_testbench01.x393_i.membridge_i.rw_in_progress[0]
x393_testbench01.x393_i.membridge_i.set_ctrl_w[0]
x393_testbench01.x393_i.membridge_i.set_len64_w[0]
@@ -684,32 +684,305 @@ x393_testbench01.x393_i.membridge_i.set_status_w[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.ad[7:0]
@28
x393_testbench01.x393_i.membridge_i.status_generate_i.clk[0]
-x393_testbench01.x393_i.membridge_i.status_generate_i.cmd_pend[0]
-x393_testbench01.x393_i.membridge_i.status_generate_i.mode[1:0]
-x393_testbench01.x393_i.membridge_i.status_generate_i.mode_w[1:0]
-x393_testbench01.x393_i.membridge_i.status_generate_i.need_to_send[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.rq[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.rst[0]
-@22
-x393_testbench01.x393_i.membridge_i.status_generate_i.seq[5:0]
-@28
-x393_testbench01.x393_i.membridge_i.status_generate_i.snd_rest[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.start[0]
-x393_testbench01.x393_i.membridge_i.status_generate_i.status_changed_r[0]
@22
x393_testbench01.x393_i.membridge_i.status_generate_i.wd[7:0]
@28
x393_testbench01.x393_i.membridge_i.status_generate_i.we[0]
@1401200
-membridge_status
-@1000200
-membridge
+@c00200
+-debug_01
+@28
+x393_testbench01.enable_memcntrl.en[0]
+@22
+x393_testbench01.axi_set_wbuf_delay.delay[3:0]
+x393_testbench01.read_status.address[7:0]
+x393_testbench01.read_and_wait_w.address[29:0]
+x393_testbench01.read_and_wait.address[31:0]
+@800200
+-axi_read_addr
+@22
+x393_testbench01.axi_read_addr.addr[31:0]
+@28
+x393_testbench01.axi_read_addr.burst[1:0]
+@22
+x393_testbench01.axi_read_addr.id[11:0]
+x393_testbench01.axi_read_addr.len[3:0]
+@28
+x393_testbench01.AR_SET_CMD[0]
+@1000200
+-axi_read_addr
+@28
+x393_testbench01.rvalid[0]
+x393_testbench01.rready[0]
+x393_testbench01.enable_cmda.en[0]
+@1401200
+-debug_01
+@800200
+-debug_o2
+@28
+x393_testbench01.x393_i.mclk[0]
+@c00200
+-cmd0_buf
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.data_in[31:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.data_out[31:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.raddr[9:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.rclk[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.regen[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.ren[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.waddr[9:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.wclk[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.web[3:0]
+@1401200
+-cmd0_buf
@200
-
+@800200
+-mcntrl16_sel
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mrst[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_0bit_we[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_0bit_addr[2:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_en[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_reset[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_enabled[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_fill[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_full[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_need[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_set[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0]
+@1000200
+-mcntrl16_sel
+@c00200
+-sheduler16
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.chn_en[15:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.clk[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.en_schedul[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn[3:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn_r[3:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_r[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_sent[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_w[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.index[3:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.index_valid[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.mrst[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_conf[15:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_r2[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_r[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_set[15:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_some[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf[15:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf_d[15:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf_w[15:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.next_need_conf[15:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.next_want_conf[15:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_addr[3:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_data[15:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_en[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pri_reg[255:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_conf[15:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_need_set_r[15:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
+@1401200
+-sheduler16
+@c00200
+-mcontr_common_chnbuf_reg0
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.buf_chn_sel[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.buf_done[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.buf_run[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.clk[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_page_nxt[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_rchn[3:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_rrefresh[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_run[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.page_nxt[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.rst[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.seq_done[0]
+@1401200
+-mcontr_common_chnbuf_reg0
+@22
+x393_testbench01.set_mrs.cmd_addr[29:0]
+x393_testbench01.set_mrs.data[31:0]
+x393_testbench01.set_mrs.mr0[17:0]
+x393_testbench01.set_mrs.mr1[17:0]
+x393_testbench01.set_mrs.mr2[17:0]
+x393_testbench01.set_mrs.mr3[17:0]
+@28
+x393_testbench01.set_mrs.reset_dll[0]
+@200
+-
+@1000200
+-debug_o2
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mrst[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dly_rst[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst[0]
+x393_testbench01.x393_i.idelay_ctrl_reset[0]
+x393_testbench01.x393_i.idelay_ctrl_rdy[0]
+@200
+-
+@28
+x393_testbench01.x393_i.mrst[0]
+@800200
+-sync_resets
+@28
+x393_testbench01.x393_i.sync_resets_i.arst[0]
+@c00022
+x393_testbench01.x393_i.sync_resets_i.clk[6:0]
+@28
+(0)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
+(1)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
+(2)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
+(3)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
+(4)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
+(5)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
+(6)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
+@1401200
+-group_end
+@800022
+x393_testbench01.x393_i.sync_resets_i.locked[6:0]
+@28
+(0)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
+(1)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
+(2)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
+(3)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
+(4)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
+(5)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
+(6)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
+@1001200
+-group_end
+@28
+x393_testbench01.x393_i.sync_resets_i.mrst[0]
+@800022
+x393_testbench01.x393_i.sync_resets_i.rst[6:0]
+@28
+(0)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
+(1)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
+(2)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
+(3)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
+(4)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
+(5)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
+(6)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
+@1001200
+-group_end
+@28
+x393_testbench01.x393_i.sync_resets_i.rst_early_master[0]
+@22
+x393_testbench01.x393_i.sync_resets_i.rst_w[6:0]
+@200
+-
+@28
+x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.clk[0]
+x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.d_in[0]
+x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.d_out[0]
+x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.d_sync[0]
+x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.regs[1:0]
+@200
+-
+@c00200
+-level_cross_clocks_sync_bit
+@28
+x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.clk[0]
+x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.d_in[0]
+x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.d_out[0]
+x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.sync_zer[1:0]
+@1401200
+-level_cross_clocks_sync_bit
+@1000200
+-sync_resets
+@c00200
+-clocks393
+@28
+x393_testbench01.x393_i.clocks393_i.aclk[0]
+x393_testbench01.x393_i.clocks393_i.async_rst[0]
+x393_testbench01.x393_i.clocks393_i.cmd_a[0]
+@22
+x393_testbench01.x393_i.clocks393_i.cmd_ad[7:0]
+x393_testbench01.x393_i.clocks393_i.cmd_data[10:0]
+@28
+x393_testbench01.x393_i.clocks393_i.cmd_stb[0]
+x393_testbench01.x393_i.clocks393_i.cmd_we[0]
+x393_testbench01.x393_i.clocks393_i.extra_status[1:0]
+@22
+x393_testbench01.x393_i.clocks393_i.fclk[3:0]
+@28
+x393_testbench01.x393_i.clocks393_i.ffclk0[0]
+x393_testbench01.x393_i.clocks393_i.ffclk0_rst[0]
+x393_testbench01.x393_i.clocks393_i.ffclk0n_pad[0]
+x393_testbench01.x393_i.clocks393_i.ffclk0p_pad[0]
+x393_testbench01.x393_i.clocks393_i.ffclk1[0]
+x393_testbench01.x393_i.clocks393_i.ffclk1_rst[0]
+x393_testbench01.x393_i.clocks393_i.ffclk1n_pad[0]
+x393_testbench01.x393_i.clocks393_i.ffclk1p_pad[0]
+x393_testbench01.x393_i.clocks393_i.hclk[0]
+@22
+x393_testbench01.x393_i.clocks393_i.locked[3:0]
+@28
+x393_testbench01.x393_i.clocks393_i.locked_hclk[0]
+x393_testbench01.x393_i.clocks393_i.locked_pclk[0]
+x393_testbench01.x393_i.clocks393_i.locked_sync_clk[0]
+x393_testbench01.x393_i.clocks393_i.locked_xclk[0]
+x393_testbench01.x393_i.clocks393_i.mclk[0]
+x393_testbench01.x393_i.clocks393_i.memclk[0]
+x393_testbench01.x393_i.clocks393_i.memclk_pad[0]
+x393_testbench01.x393_i.clocks393_i.memclk_rst[0]
+x393_testbench01.x393_i.clocks393_i.mrst[0]
+x393_testbench01.x393_i.clocks393_i.pclk2x[0]
+x393_testbench01.x393_i.clocks393_i.pclk[0]
+@22
+x393_testbench01.x393_i.clocks393_i.pwrdwn_clk[3:0]
+x393_testbench01.x393_i.clocks393_i.reset_clk[6:0]
+@28
+x393_testbench01.x393_i.clocks393_i.set_ctrl_w[0]
+x393_testbench01.x393_i.clocks393_i.set_status_w[0]
+@22
+x393_testbench01.x393_i.clocks393_i.status_ad[7:0]
+x393_testbench01.x393_i.clocks393_i.status_data[8:0]
+@28
+x393_testbench01.x393_i.clocks393_i.status_rq[0]
+x393_testbench01.x393_i.clocks393_i.status_start[0]
+x393_testbench01.x393_i.clocks393_i.sync_clk[0]
+x393_testbench01.x393_i.clocks393_i.test_clk[2:0]
+x393_testbench01.x393_i.clocks393_i.time_ref[0]
+x393_testbench01.x393_i.clocks393_i.time_ref_r[2:0]
+x393_testbench01.x393_i.clocks393_i.xclk2x[0]
+x393_testbench01.x393_i.clocks393_i.xclk[0]
+@1401200
+-clocks393
@22
x393_testbench01.x393_i.membridge_i.status_generate_i.status[17:0]
@28
-x393_testbench01.x393_i.membridge_i.status_generate_i.status_changed_r[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.rq[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.start[0]
@22
@@ -771,7 +1044,6 @@ x393_testbench01.x393_i.ps7_i.SAXIHP0ARPROT[2:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0ARQOS[3:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0ARREADY[0]
-x393_testbench01.x393_i.ps7_i.SAXIHP0ARSIZE[2:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0ARVALID[0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0AWADDR[31:0]
@@ -788,9 +1060,6 @@ x393_testbench01.x393_i.ps7_i.SAXIHP0AWPROT[2:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0AWQOS[3:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0AWREADY[0]
-@22
-x393_testbench01.x393_i.ps7_i.SAXIHP0AWSIZE[2:0]
-@28
x393_testbench01.x393_i.ps7_i.SAXIHP0AWVALID[0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0BID[5:0]
@@ -826,7 +1095,7 @@ x393_testbench01.x393_i.ps7_i.SAXIHP0WSTRB[7:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0WVALID[0]
@1401200
-SAXIHP0
-@c00200
+@800200
-linear_rw_chn1
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.busy_r[0]
@@ -856,8 +1125,10 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_finished_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_full_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_full_width_r[13:0]
@28
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_start[0]
@22
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_start_r[4:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_y8_r[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_y[15:0]
@@ -878,14 +1149,17 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.lsw13_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mclk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mem_page_left[7:0]
-x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mode_reg[4:0]
@28
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mrst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.msw_zero[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mul_rslt[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mul_rslt_w[26:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.need_r[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_frame_start_addr[21:0]
+@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_page[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_y[16:0]
@@ -900,10 +1174,12 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pre_want[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.remainder_in_xfer[7:0]
+@29
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.repeat_frames[0]
+@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.row_col_r[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.row_left[13:0]
@28
-x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_frame_width_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_mode_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_start_addr_w[0]
@@ -911,6 +1187,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_status_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_window_start_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_window_wh_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_window_x0y0_w[0]
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.single_frame_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_addr_r[21:0]
@@ -961,7 +1238,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want[0]
-@1401200
+@1000200
-linear_rw_chn1
@c00200
-axibram_write
@@ -1045,7 +1322,6 @@ x393_testbench01.x393_i.axibram_write_i.dev_ready_r[0]
x393_testbench01.x393_i.axibram_write_i.next_wr_address_w[13:0]
x393_testbench01.x393_i.axibram_write_i.pre_awaddr[13:0]
@28
-x393_testbench01.x393_i.axibram_write_i.rst[0]
x393_testbench01.x393_i.axibram_write_i.start_burst[0]
x393_testbench01.x393_i.axibram_write_i.start_write_burst_w[0]
x393_testbench01.x393_i.axibram_write_i.w_half_full[0]
@@ -1116,13 +1392,11 @@ x393_testbench01.x393_i.cmd_mux_i.par_data[31:0]
x393_testbench01.x393_i.cmd_mux_i.par_waddr[13:0]
x393_testbench01.x393_i.cmd_mux_i.pre_waddr[13:0]
@28
-x393_testbench01.x393_i.cmd_mux_i.rst[0]
x393_testbench01.x393_i.cmd_mux_i.selected[0]
x393_testbench01.x393_i.cmd_mux_i.selected_w[0]
@22
x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0]
x393_testbench01.x393_i.cmd_mux_i.seq_length[3:0]
-x393_testbench01.x393_i.cmd_mux_i.seq_length_rom_a[3:0]
@28
x393_testbench01.x393_i.cmd_mux_i.ss[0]
x393_testbench01.x393_i.cmd_mux_i.start_axi_w[0]
@@ -1162,7 +1436,6 @@ x393_testbench01.x393_i.status_read_i.rd[0]
x393_testbench01.x393_i.status_read_i.regen[0]
x393_testbench01.x393_i.status_read_i.rq[0]
x393_testbench01.x393_i.status_read_i.rq_r[0]
-x393_testbench01.x393_i.status_read_i.rst[0]
x393_testbench01.x393_i.status_read_i.select_d[0]
x393_testbench01.x393_i.status_read_i.select_r[0]
x393_testbench01.x393_i.status_read_i.select_w[0]
@@ -1185,7 +1458,6 @@ x393_testbench01.x393_i.cmd_readback_i.axi_clk[0]
x393_testbench01.x393_i.cmd_readback_i.axi_rback_rdata[31:0]
x393_testbench01.x393_i.cmd_readback_i.axi_rback_rdata_r[31:0]
x393_testbench01.x393_i.cmd_readback_i.axird_pre_araddr[13:0]
-x393_testbench01.x393_i.cmd_readback_i.axird_raddr[9:0]
x393_testbench01.x393_i.cmd_readback_i.axird_rdata[31:0]
@28
x393_testbench01.x393_i.cmd_readback_i.axird_regen[0]
@@ -1199,12 +1471,10 @@ x393_testbench01.x393_i.cmd_readback_i.par_waddr[13:0]
@28
x393_testbench01.x393_i.cmd_readback_i.rd[0]
x393_testbench01.x393_i.cmd_readback_i.regen[0]
-x393_testbench01.x393_i.cmd_readback_i.rst[0]
x393_testbench01.x393_i.cmd_readback_i.select_d[0]
x393_testbench01.x393_i.cmd_readback_i.select_r[0]
x393_testbench01.x393_i.cmd_readback_i.select_w[0]
@22
-x393_testbench01.x393_i.cmd_readback_i.waddr[9:0]
x393_testbench01.x393_i.cmd_readback_i.wdata[31:0]
@28
x393_testbench01.x393_i.cmd_readback_i.we[0]
diff --git a/x393_testbench01.tf b/x393_testbench01.tf
index 74b44487d71b3e669c04459a52c4950a89b22a30..f4c576bed155461829eafe2f4c6fdc11e54dde40 100644
--- a/x393_testbench01.tf
+++ b/x393_testbench01.tf
@@ -76,76 +76,148 @@ module x393_testbench01 #(
//`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh
`include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh
`include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used
+
+// Sensor signals - as on sensor pads
+ wire PX1_MCLK; // input sensor input clock
+ wire PX1_MRST; // input
+ wire PX1_ARO; // input
+ wire PX1_ARST; // input
+ wire PX1_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
+ wire [11:0] PX1_D; // output[11:0]
+ wire PX1_DCLK; // output sensor output clock (connect to sensor BPF output )
+ wire PX1_HACT; // output
+ wire PX1_VACT; // output
+
+// Sensor signals - as on FPGA pads
+ wire [ 7:0] sns1_dp; // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
+ wire [ 7:0] sns1_dn; // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
+ wire sns1_clkp; // inout CNVCLK/TDO
+ wire sns1_clkn; // inout CNVSYNC/TDI
+ wire sns1_scl; // inout PX_SCL
+ wire sns1_sda; // inout PX_SDA
+ wire sns1_ctl; // inout PX_ARO/TCK
+ wire sns1_pg; // inout SENSPGM
+
+//connect sensor to sensor port 1
+assign sns1_dp[6:1] = {PX1_D[10], PX1_D[8], PX1_D[6], PX1_D[4], PX1_D[2], PX1_HACT};
+assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor
+assign PX1_MCLK = sns1_dp[0]; // from FPGA to sensor
+assign sns1_dn[6:0] = {PX1_D[11], PX1_D[9], PX1_D[7], PX1_D[5], PX1_D[3], PX1_VACT, PX1_DCLK};
+assign PX1_ARST = sns1_dn[7];
+assign sns1_clkn = PX1_D[0]; // inout CNVSYNC/TDI
+assign sns1_scl = PX1_D[1]; // inout PX_SCL
+assign PX1_ARO = sns1_ctl; // from FPGA to sensor
+
+
+ wire [ 7:0] sns2_dp; // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
+ wire [ 7:0] sns2_dn; // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
+ wire sns2_clkp; // inout CNVCLK/TDO
+ wire sns2_clkn; // inout CNVSYNC/TDI
+ wire sns2_scl; // inout PX_SCL
+ wire sns2_sda; // inout PX_SDA
+ wire sns2_ctl; // inout PX_ARO/TCK
+ wire sns2_pg; // inout SENSPGM
+
+ wire [ 7:0] sns3_dp; // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
+ wire [ 7:0] sns3_dn; // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
+ wire sns3_clkp; // inout CNVCLK/TDO
+ wire sns3_clkn; // inout CNVSYNC/TDI
+ wire sns3_scl; // inout PX_SCL
+ wire sns3_sda; // inout PX_SDA
+ wire sns3_ctl; // inout PX_ARO/TCK
+ wire sns3_pg; // inout SENSPGM
+
+ wire [ 7:0] sns4_dp; // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
+ wire [ 7:0] sns4_dn; // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
+ wire sns4_clkp; // inout CNVCLK/TDO
+ wire sns4_clkn; // inout CNVSYNC/TDI
+ wire sns4_scl; // inout PX_SCL
+ wire sns4_sda; // inout PX_SDA
+ wire sns4_ctl; // inout PX_ARO/TCK
+ wire sns4_pg; // inout SENSPGM
+
+ wire [ 9:0] gpio_pins; // inout[9:0] ([6]-synco0,[7]-syncio0,[8]-synco1,[9]-syncio1)
+// Connect trigger outs to triggets in (#10 needed for Icarus)
+assign #10 gpio_pins[7] = gpio_pins[6];
+assign #10 gpio_pins[9] = gpio_pins[8];
+
// DDR3 signals
- wire SDRST;
- wire SDCLK; // output
- wire SDNCLK; // output
- wire [ADDRESS_NUMBER-1:0] SDA; // output[14:0]
- wire [ 2:0] SDBA; // output[2:0]
- wire SDWE; // output
- wire SDRAS; // output
- wire SDCAS; // output
- wire SDCKE; // output
- wire SDODT; // output
- wire [15:0] SDD; // inout[15:0]
- wire SDDML; // inout
- wire DQSL; // inout
- wire NDQSL; // inout
- wire SDDMU; // inout
- wire DQSU; // inout
- wire NDQSU; // inout
- wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
-// wire MEMCLK;
+ wire SDRST;
+ wire SDCLK; // output
+ wire SDNCLK; // output
+ wire [ADDRESS_NUMBER-1:0] SDA; // output[14:0]
+ wire [ 2:0] SDBA; // output[2:0]
+ wire SDWE; // output
+ wire SDRAS; // output
+ wire SDCAS; // output
+ wire SDCKE; // output
+ wire SDODT; // output
+ wire [15:0] SDD; // inout[15:0]
+ wire SDDML; // inout
+ wire DQSL; // inout
+ wire NDQSL; // inout
+ wire SDDMU; // inout
+ wire DQSU; // inout
+ wire NDQSU; // inout
+ wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
+ wire memclk;
+
+ wire ffclk0p; // input
+ wire ffclk0n; // input
+ wire ffclk1p; // input
+ wire ffclk1n; // input
+
+
// axi_hp simulation signals
- wire HCLK;
- wire [31:0] afi_sim_rd_address; // output[31:0]
- wire [ 5:0] afi_sim_rid; // output[5:0] SuppressThisWarning VEditor - not used - just view
+ wire HCLK;
+ wire [31:0] afi_sim_rd_address; // output[31:0]
+ wire [ 5:0] afi_sim_rid; // output[5:0] SuppressThisWarning VEditor - not used - just view
// reg afi_sim_rd_valid; // input
- wire afi_sim_rd_valid; // input
- wire afi_sim_rd_ready; // output
+ wire afi_sim_rd_valid; // input
+ wire afi_sim_rd_ready; // output
// reg [63:0] afi_sim_rd_data; // input[63:0]
- wire [63:0] afi_sim_rd_data; // input[63:0]
- wire [ 2:0] afi_sim_rd_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
- wire [ 3:0] afi_sim_rd_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
- wire [ 1:0] afi_sim_rd_resp; // input[1:0]
+ wire [63:0] afi_sim_rd_data; // input[63:0]
+ wire [ 2:0] afi_sim_rd_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
+ wire [ 3:0] afi_sim_rd_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
+ wire [ 1:0] afi_sim_rd_resp; // input[1:0]
// reg [ 1:0] afi_sim_rd_resp; // input[1:0]
- wire [31:0] afi_sim_wr_address; // output[31:0] SuppressThisWarning VEditor - not used - just view
- wire [ 5:0] afi_sim_wid; // output[5:0] SuppressThisWarning VEditor - not used - just view
- wire afi_sim_wr_valid; // output
- wire afi_sim_wr_ready; // input
+ wire [31:0] afi_sim_wr_address; // output[31:0] SuppressThisWarning VEditor - not used - just view
+ wire [ 5:0] afi_sim_wid; // output[5:0] SuppressThisWarning VEditor - not used - just view
+ wire afi_sim_wr_valid; // output
+ wire afi_sim_wr_ready; // input
// reg afi_sim_wr_ready; // input
- wire [63:0] afi_sim_wr_data; // output[63:0] SuppressThisWarning VEditor - not used - just view
- wire [ 7:0] afi_sim_wr_stb; // output[7:0] SuppressThisWarning VEditor - not used - just view
- wire [ 3:0] afi_sim_bresp_latency; // input[3:0]
+ wire [63:0] afi_sim_wr_data; // output[63:0] SuppressThisWarning VEditor - not used - just view
+ wire [ 7:0] afi_sim_wr_stb; // output[7:0] SuppressThisWarning VEditor - not used - just view
+ wire [ 3:0] afi_sim_bresp_latency; // input[3:0]
// reg [ 3:0] afi_sim_bresp_latency; // input[3:0]
- wire [ 2:0] afi_sim_wr_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
- wire [ 3:0] afi_sim_wr_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
+ wire [ 2:0] afi_sim_wr_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
+ wire [ 3:0] afi_sim_wr_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
- assign HCLK = x393_i.ps7_i.SAXIHP0ACLK; // shortcut name
+ assign HCLK = x393_i.ps7_i.SAXIHP0ACLK; // shortcut name
// afi loopback
- assign #1 afi_sim_rd_data= afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1, 2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;
- assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
- assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
- assign #1 afi_sim_wr_ready = afi_sim_wr_valid;
- assign #1 afi_sim_bresp_latency=4'h5;
+ assign #1 afi_sim_rd_data= afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1, 2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;
+ assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
+ assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
+ assign #1 afi_sim_wr_ready = afi_sim_wr_valid;
+ assign #1 afi_sim_bresp_latency=4'h5;
// axi_hp register access
// PS memory mapped registers to read/write over a separate simulation bus running at HCLK, no waits
- reg [31:0] PS_REG_ADDR;
- reg PS_REG_WR;
- reg PS_REG_RD;
- reg [31:0] PS_REG_DIN;
- wire [31:0] PS_REG_DOUT;
- reg [31:0] PS_RDATA; // SuppressThisWarning VEditor - not used - just view
+ reg [31:0] PS_REG_ADDR;
+ reg PS_REG_WR;
+ reg PS_REG_RD;
+ reg [31:0] PS_REG_DIN;
+ wire [31:0] PS_REG_DOUT;
+ reg [31:0] PS_RDATA; // SuppressThisWarning VEditor - not used - just view
/*
- reg [31:0] afi_reg_addr;
- reg afi_reg_wr;
- reg afi_reg_rd;
- reg [31:0] afi_reg_din;
+ reg [31:0] afi_reg_addr;
+ reg afi_reg_wr;
+ reg afi_reg_rd;
+ reg [31:0] afi_reg_din;
wire [31:0] afi_reg_dout;
- reg [31:0] AFI_REG_RD; // SuppressThisWarning VEditor - not used - just view
+ reg [31:0] AFI_REG_RD; // SuppressThisWarning VEditor - not used - just view
*/
initial begin
PS_REG_ADDR <= 'bx;
@@ -156,127 +228,127 @@ module x393_testbench01 #(
end
always @ (posedge HCLK) if (PS_REG_RD) PS_RDATA <= PS_REG_DOUT;
- reg [639:0] TEST_TITLE;
+ reg [639:0] TEST_TITLE;
// Simulation signals
- reg [11:0] ARID_IN_r;
- reg [31:0] ARADDR_IN_r;
- reg [3:0] ARLEN_IN_r;
- reg [2:0] ARSIZE_IN_r;
- reg [1:0] ARBURST_IN_r;
- reg [11:0] AWID_IN_r;
- reg [31:0] AWADDR_IN_r;
- reg [3:0] AWLEN_IN_r;
- reg [2:0] AWSIZE_IN_r;
- reg [1:0] AWBURST_IN_r;
-
- reg [11:0] WID_IN_r;
- reg [31:0] WDATA_IN_r;
- reg [ 3:0] WSTRB_IN_r;
- reg WLAST_IN_r;
+ reg [11:0] ARID_IN_r;
+ reg [31:0] ARADDR_IN_r;
+ reg [3:0] ARLEN_IN_r;
+ reg [2:0] ARSIZE_IN_r;
+ reg [1:0] ARBURST_IN_r;
+ reg [11:0] AWID_IN_r;
+ reg [31:0] AWADDR_IN_r;
+ reg [3:0] AWLEN_IN_r;
+ reg [2:0] AWSIZE_IN_r;
+ reg [1:0] AWBURST_IN_r;
+
+ reg [11:0] WID_IN_r;
+ reg [31:0] WDATA_IN_r;
+ reg [ 3:0] WSTRB_IN_r;
+ reg WLAST_IN_r;
- reg [11:0] LAST_ARID; // last issued ARID
+ reg [11:0] LAST_ARID; // last issued ARID
// SuppressWarnings VEditor : assigned in $readmem() system task
- wire [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR_W;
+ wire [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR_W;
// SuppressWarnings VEditor
- wire SIMUL_AXI_MISMATCH;
+ wire SIMUL_AXI_MISMATCH;
// SuppressWarnings VEditor
- reg [31:0] SIMUL_AXI_READ;
+ reg [31:0] SIMUL_AXI_READ;
// SuppressWarnings VEditor
- reg [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR;
+ reg [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR;
// SuppressWarnings VEditor
- reg SIMUL_AXI_FULL; // some data available
- wire SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWarning VEditor : may be unused, just for simulation // use it to wait for?
- reg [31:0] registered_rdata; // here read data from tasks goes
+ reg SIMUL_AXI_FULL; // some data available
+ wire SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWarning VEditor : may be unused, just for simulation // use it to wait for?
+ reg [31:0] registered_rdata; // here read data from tasks goes
// SuppressWarnings VEditor
- reg WAITING_STATUS; // tasks are waiting for status
-
- reg CLK;
- reg RST;
- reg AR_SET_CMD_r;
- wire AR_READY;
-
- reg AW_SET_CMD_r;
- wire AW_READY;
-
- reg W_SET_CMD_r;
- wire W_READY;
-
- wire [11:0] #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r;
- wire [31:0] #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r;
- wire [3:0] #(AXI_TASK_HOLD) ARLEN_IN = ARLEN_IN_r;
- wire [2:0] #(AXI_TASK_HOLD) ARSIZE_IN = ARSIZE_IN_r;
- wire [1:0] #(AXI_TASK_HOLD) ARBURST_IN = ARBURST_IN_r;
- wire [11:0] #(AXI_TASK_HOLD) AWID_IN = AWID_IN_r;
- wire [31:0] #(AXI_TASK_HOLD) AWADDR_IN = AWADDR_IN_r;
- wire [3:0] #(AXI_TASK_HOLD) AWLEN_IN = AWLEN_IN_r;
- wire [2:0] #(AXI_TASK_HOLD) AWSIZE_IN = AWSIZE_IN_r;
- wire [1:0] #(AXI_TASK_HOLD) AWBURST_IN = AWBURST_IN_r;
- wire [11:0] #(AXI_TASK_HOLD) WID_IN = WID_IN_r;
- wire [31:0] #(AXI_TASK_HOLD) WDATA_IN = WDATA_IN_r;
- wire [ 3:0] #(AXI_TASK_HOLD) WSTRB_IN = WSTRB_IN_r;
- wire #(AXI_TASK_HOLD) WLAST_IN = WLAST_IN_r;
- wire #(AXI_TASK_HOLD) AR_SET_CMD = AR_SET_CMD_r;
- wire #(AXI_TASK_HOLD) AW_SET_CMD = AW_SET_CMD_r;
- wire #(AXI_TASK_HOLD) W_SET_CMD = W_SET_CMD_r;
-
- reg [3:0] RD_LAG; // ready signal lag in axi read channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
- reg [3:0] B_LAG; // ready signal lag in axi arete response channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
+ reg WAITING_STATUS; // tasks are waiting for status
+
+ wire CLK;
+ reg RST;
+ reg AR_SET_CMD_r;
+ wire AR_READY;
+
+ reg AW_SET_CMD_r;
+ wire AW_READY;
+
+ reg W_SET_CMD_r;
+ wire W_READY;
+
+ wire [11:0] #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r;
+ wire [31:0] #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r;
+ wire [3:0] #(AXI_TASK_HOLD) ARLEN_IN = ARLEN_IN_r;
+ wire [2:0] #(AXI_TASK_HOLD) ARSIZE_IN = ARSIZE_IN_r;
+ wire [1:0] #(AXI_TASK_HOLD) ARBURST_IN = ARBURST_IN_r;
+ wire [11:0] #(AXI_TASK_HOLD) AWID_IN = AWID_IN_r;
+ wire [31:0] #(AXI_TASK_HOLD) AWADDR_IN = AWADDR_IN_r;
+ wire [3:0] #(AXI_TASK_HOLD) AWLEN_IN = AWLEN_IN_r;
+ wire [2:0] #(AXI_TASK_HOLD) AWSIZE_IN = AWSIZE_IN_r;
+ wire [1:0] #(AXI_TASK_HOLD) AWBURST_IN = AWBURST_IN_r;
+ wire [11:0] #(AXI_TASK_HOLD) WID_IN = WID_IN_r;
+ wire [31:0] #(AXI_TASK_HOLD) WDATA_IN = WDATA_IN_r;
+ wire [ 3:0] #(AXI_TASK_HOLD) WSTRB_IN = WSTRB_IN_r;
+ wire #(AXI_TASK_HOLD) WLAST_IN = WLAST_IN_r;
+ wire #(AXI_TASK_HOLD) AR_SET_CMD = AR_SET_CMD_r;
+ wire #(AXI_TASK_HOLD) AW_SET_CMD = AW_SET_CMD_r;
+ wire #(AXI_TASK_HOLD) W_SET_CMD = W_SET_CMD_r;
+
+ reg [3:0] RD_LAG; // ready signal lag in axi read channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
+ reg [3:0] B_LAG; // ready signal lag in axi arete response channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
// Simulation modules interconnection
- wire [11:0] arid;
- wire [31:0] araddr;
- wire [3:0] arlen;
- wire [2:0] arsize;
- wire [1:0] arburst;
+ wire [11:0] arid;
+ wire [31:0] araddr;
+ wire [3:0] arlen;
+ wire [2:0] arsize;
+ wire [1:0] arburst;
// SuppressWarnings VEditor : assigned in $readmem(14) system task
- wire [3:0] arcache;
+ wire [3:0] arcache;
// SuppressWarnings VEditor : assigned in $readmem() system task
- wire [2:0] arprot;
- wire arvalid;
- wire arready;
-
- wire [11:0] awid;
- wire [31:0] awaddr;
- wire [3:0] awlen;
- wire [2:0] awsize;
- wire [1:0] awburst;
+ wire [2:0] arprot;
+ wire arvalid;
+ wire arready;
+
+ wire [11:0] awid;
+ wire [31:0] awaddr;
+ wire [3:0] awlen;
+ wire [2:0] awsize;
+ wire [1:0] awburst;
// SuppressWarnings VEditor : assigned in $readmem() system task
- wire [3:0] awcache;
+ wire [3:0] awcache;
// SuppressWarnings VEditor : assigned in $readmem() system task
- wire [2:0] awprot;
- wire awvalid;
- wire awready;
-
- wire [11:0] wid;
- wire [31:0] wdata;
- wire [3:0] wstrb;
- wire wlast;
- wire wvalid;
- wire wready;
+ wire [2:0] awprot;
+ wire awvalid;
+ wire awready;
+
+ wire [11:0] wid;
+ wire [31:0] wdata;
+ wire [3:0] wstrb;
+ wire wlast;
+ wire wvalid;
+ wire wready;
- wire [31:0] rdata;
+ wire [31:0] rdata;
// SuppressWarnings VEditor : assigned in $readmem() system task
- wire [11:0] rid;
- wire rlast;
+ wire [11:0] rid;
+ wire rlast;
// SuppressWarnings VEditor : assigned in $readmem() system task
- wire [1:0] rresp;
- wire rvalid;
- wire rready;
- wire rstb=rvalid && rready;
+ wire [1:0] rresp;
+ wire rvalid;
+ wire rready;
+ wire rstb=rvalid && rready;
// SuppressWarnings VEditor : assigned in $readmem() system task
- wire [1:0] bresp;
+ wire [1:0] bresp;
// SuppressWarnings VEditor : assigned in $readmem() system task
- wire [11:0] bid;
- wire bvalid;
- wire bready;
- integer NUM_WORDS_READ;
- integer NUM_WORDS_EXPECTED;
- reg [15:0] ENABLED_CHANNELS = 0; // currently enabled memory channels
+ wire [11:0] bid;
+ wire bvalid;
+ wire bready;
+ integer NUM_WORDS_READ;
+ integer NUM_WORDS_EXPECTED;
+ reg [15:0] ENABLED_CHANNELS = 0; // currently enabled memory channels
// integer SCANLINE_CUR_X;
// integer SCANLINE_CUR_Y;
- wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
+ wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
@@ -293,7 +365,8 @@ module x393_testbench01 #(
// integer ii;
// integer SCANLINE_XFER_SIZE;
-always #(CLKIN_PERIOD/2) CLK = ~CLK;
+
+
initial begin
`ifdef IVERILOG
$display("IVERILOG is defined");
@@ -307,9 +380,11 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
$display("ICARUS is not defined");
`endif
$dumpfile(lxtname);
+
+
// SuppressWarnings VEditor : assigned in $readmem() system task
$dumpvars(0,x393_testbench01);
- CLK =1'b0;
+// CLK =1'b0;
RST = 1'bx;
AR_SET_CMD_r = 1'b0;
AW_SET_CMD_r = 1'b0;
@@ -323,6 +398,8 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
#9000; // same as glbl
repeat (20) @(posedge CLK) ;
RST =1'b0;
+ while (x393_i.mrst) @(posedge CLK) ;
+// repeat (4) @(posedge CLK) ;
//set simulation-only parameters
axi_set_b_lag(0); //(1);
axi_set_rd_lag(0);
@@ -334,7 +411,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
axi_set_wbuf_delay(WBUF_DLY_DFLT); //DFLT_WBUF_DELAY - used in synth. code
wait_phase_shifter_ready;
- read_all_status;
+ read_all_status; //stuck here
// enable output for address/commands to DDR chip
enable_cmda(1);
@@ -838,25 +915,67 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
) x393_i (
- .SDRST (SDRST), // DDR3 reset (active low)
- .SDCLK (SDCLK), // output
- .SDNCLK (SDNCLK), // outputread_and_wait(BASEADDR_STATUS)
- .SDA (SDA[14:0]), // output[14:0]
- .SDBA (SDBA[2:0]), // output[2:0]
- .SDWE (SDWE), // output
- .SDRAS (SDRAS), // output
- .SDCAS (SDCAS), // output
- .SDCKE (SDCKE), // output
- .SDODT (SDODT), // output
- .SDD (SDD[15:0]), // inout[15:0]
- .SDDML (SDDML), // inout
- .DQSL (DQSL), // inout
- .NDQSL (NDQSL), // inout
- .SDDMU (SDDMU), // inout
- .DQSU (DQSU), // inout
- .NDQSU (NDQSU), // inout
+ .sns1_dp (sns1_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
+ .sns1_dn (sns1_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
+ .sns1_clkp (sns1_clkp), // inout CNVCLK/TDO
+ .sns1_clkn (sns1_clkn), // inout CNVSYNC/TDI
+ .sns1_scl (sns1_scl), // inout PX_SCL
+ .sns1_sda (sns1_sda), // inout PX_SDA
+ .sns1_ctl (sns1_ctl), // inout PX_ARO/TCK
+ .sns1_pg (sns1_pg), // inout SENSPGM
+
+ .sns2_dp (sns2_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
+ .sns2_dn (sns2_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
+ .sns2_clkp (sns2_clkp), // inout CNVCLK/TDO
+ .sns2_clkn (sns2_clkn), // inout CNVSYNC/TDI
+ .sns2_scl (sns2_scl), // inout PX_SCL
+ .sns2_sda (sns2_sda), // inout PX_SDA
+ .sns2_ctl (sns2_ctl), // inout PX_ARO/TCK
+ .sns2_pg (sns2_pg), // inout SENSPGM
+
+ .sns3_dp (sns3_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
+ .sns3_dn (sns3_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
+ .sns3_clkp (sns3_clkp), // inout CNVCLK/TDO
+ .sns3_clkn (sns3_clkn), // inout CNVSYNC/TDI
+ .sns3_scl (sns3_scl), // inout PX_SCL
+ .sns3_sda (sns3_sda), // inout PX_SDA
+ .sns3_ctl (sns3_ctl), // inout PX_ARO/TCK
+ .sns3_pg (sns3_pg), // inout SENSPGM
+
+ .sns4_dp (sns4_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
+ .sns4_dn (sns4_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
+ .sns4_clkp (sns4_clkp), // inout CNVCLK/TDO
+ .sns4_clkn (sns4_clkn), // inout CNVSYNC/TDI
+ .sns4_scl (sns4_scl), // inout PX_SCL
+ .sns4_sda (sns4_sda), // inout PX_SDA
+ .sns4_ctl (sns4_ctl), // inout PX_ARO/TCK
+ .sns4_pg (sns4_pg), // inout SENSPGM
+
+ .gpio_pins (gpio_pins), // inout[9:0]
+
+ .SDRST (SDRST), // DDR3 reset (active low)
+ .SDCLK (SDCLK), // output
+ .SDNCLK (SDNCLK), // outputread_and_wait(BASEADDR_STATUS)
+ .SDA (SDA[14:0]), // output[14:0]
+ .SDBA (SDBA[2:0]), // output[2:0]
+ .SDWE (SDWE), // output
+ .SDRAS (SDRAS), // output
+ .SDCAS (SDCAS), // output
+ .SDCKE (SDCKE), // output
+ .SDODT (SDODT), // output
+ .SDD (SDD[15:0]), // inout[15:0]
+ .SDDML (SDDML), // inout
+ .DQSL (DQSL), // inout
+ .NDQSL (NDQSL), // inout
+ .SDDMU (SDDMU), // inout
+ .DQSU (DQSU), // inout
+ .NDQSU (NDQSU), // inout
+ .memclk (memclk),
+ .ffclk0p (ffclk0p), // input
+ .ffclk0n (ffclk0n), // input
+ .ffclk1p (ffclk1p), // input
+ .ffclk1n (ffclk1n), // input
.DUMMY_TO_KEEP(DUMMY_TO_KEEP) // to keep PS7 signals from "optimization"
- ,.MEMCLK (1'b0)
);
// just to simplify extra delays in tri-state memory bus - provide output enable
wire WRAP_MCLK=x393_i.mclk;
@@ -1294,7 +1413,53 @@ simul_axi_hp_wr #(
.reg_dout (PS_REG_DOUT) // output[31:0]
);
+// Generate all clocks
+//always #(CLKIN_PERIOD/2) CLK = ~CLK;
+ simul_clk #(
+ .CLKIN_PERIOD (CLKIN_PERIOD),
+ .MEMCLK_PERIOD (MEMCLK_PERIOD),
+ .FCLK0_PERIOD (FCLK0_PERIOD),
+ .FCLK1_PERIOD (FCLK1_PERIOD)
+ ) simul_clk_i (
+ .rst (1'b0), // input
+ .clk (CLK), // output
+ .memclk (memclk), // output
+ .ffclk0 ({ffclk0n, ffclk0p}), // output[1:0]
+ .ffclk1 ({ffclk1n, ffclk1p}) // output[1:0]
+ );
+ simul_sensor12bits #(
+ .lline(192),
+ .ncols(66),
+ .nrows(18),
+ .nrowb(1),
+ .nrowa(1),
+// .nAV(24),
+ .nbpf(20),
+ .ngp1(8),
+ .nVLO(1),
+ .tMD(4),
+ .tDDO(2),
+ .tDDO1(5),
+ .trigdly(8),
+ .ramp(1),
+ .new_bayer(0)
+ ) simul_sensor12bits_i (
+ .MCLK (PX1_MCLK), // input
+ .MRST (PX1_MRST), // input
+ .ARO (PX1_ARO), // input
+ .ARST (PX1_ARST), // input
+ .OE (1'b0), // input output enable active low
+ .SCL (sns1_scl), // input
+ .SDA (sns1_sda), // inout
+ .OFST (PX1_OFST), // input
+ .D (PX1_D), // output[11:0]
+ .DCLK (PX1_DCLK), // output
+ .BPF (), // output
+ .HACT (PX1_HACT), // output
+ .VACT (PX1_VACT), // output
+ .VACT1 () // output
+ );
// wire [ 3:0] SIMUL_ADD_ADDR;
@@ -1320,10 +1485,10 @@ simul_axi_hp_wr #(
// SuppressWarnings VEditor all - these variables are just for viewing, not used anywhere else
- reg DEBUG1, DEBUG2, DEBUG3;
- reg [11:0] GLOBAL_WRITE_ID=0;
- reg [11:0] GLOBAL_READ_ID=0;
- reg [7:0] target_phase=0; // to compare/wait for phase shifter ready
+ reg DEBUG1, DEBUG2, DEBUG3;
+ reg [11:0] GLOBAL_WRITE_ID=0;
+ reg [11:0] GLOBAL_READ_ID=0;
+ reg [7:0] target_phase=0; // to compare/wait for phase shifter ready
task set_up;
begin
@@ -1463,7 +1628,14 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
`ifdef MEMBRIDGE_DEBUG_READ
integer ii;
`endif
+ reg repetitive;
+ reg single;
+ reg reset_frame;
+
begin
+ repetitive = 1'b1;
+ single = 1'b0;
+ reset_frame = 1'b0;
$display("====== test_afi_rw: write=%d, extra_pages=%d, frame_start= %x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d,@%t",
write_ddr3, extra_pages, frame_start_addr, window_full_width, window_width, window_height, window_left, window_top, $time);
$display("len64=%x, width64=%x, start64=%x, lo_addr64=%x, size64=%x,@%t",
@@ -1471,6 +1643,9 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
start64, lo_addr64, size64, $time);
mode= func_encode_mode_scanline(
+ repetitive,
+ single,
+ reset_frame,
extra_pages,
write_ddr3, // write_mem,
1, // enable
@@ -1533,7 +1708,14 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
integer xfer_size;
integer pages_per_row;
integer startx,starty; // temporary - because of the vdt bug with integer ports
+ reg repetitive;
+ reg single;
+ reg reset_frame;
+
begin
+ repetitive = 1'b1;
+ single = 1'b0;
+ reset_frame = 1'b0;
pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
$display("====== test_scanline_write: channel=%d, extra_pages=%d, wait_done=%d @%t",
channel, extra_pages, wait_done, $time);
@@ -1559,6 +1741,9 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
+ repetitive,
+ single,
+ reset_frame,
extra_pages,
1, // write_mem,
1, // enable
@@ -1661,7 +1846,14 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
integer xfer_size;
integer pages_per_row;
+ reg repetitive;
+ reg single;
+ reg reset_frame;
+
begin
+ repetitive = 1'b1;
+ single = 1'b0;
+ reset_frame = 1'b0;
pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
$display("====== test_scanline_read: channel=%d, extra_pages=%d, show_data=%d @%t",
channel, extra_pages, show_data, $time);
@@ -1687,6 +1879,9 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
+ repetitive,
+ single,
+ reset_frame,
extra_pages,
0, // write_mem,
1, // enable
@@ -1760,7 +1955,15 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
integer tile_rows_per_window;
integer tile_size;
integer startx,starty; // temporary - because of the vdt bug with integer ports
+ reg repetitive;
+ reg single;
+ reg reset_frame;
+
begin
+ repetitive = 1'b1;
+ single = 1'b0;
+ reset_frame = 1'b0;
+
tiles_per_row= (window_width/tile_width)+ ((window_width % tile_width==0)?0:1);
tile_rows_per_window= ((window_height-1)/tile_vstep) + 1;
tile_size= tile_width*tile_height;
@@ -1788,6 +1991,9 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
+ repetitive,
+ single,
+ reset_frame,
byte32,
keep_open,
extra_pages,
@@ -1881,7 +2087,15 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
integer tile_rows_per_window;
integer tile_size;
+ reg repetitive;
+ reg single;
+ reg reset_frame;
+
begin
+ repetitive = 1'b1;
+ single = 1'b0;
+ reset_frame = 1'b0;
+
tiles_per_row= (window_width/tile_width)+ ((window_width % tile_width==0)?0:1);
tile_rows_per_window= ((window_height-1)/tile_vstep) + 1;
tile_size= tile_width*tile_height;
@@ -1909,6 +2123,9 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
+ repetitive,
+ single,
+ reset_frame,
byte32,
keep_open,
extra_pages,
@@ -2017,7 +2234,10 @@ task write_block_scanline_chn; // S uppressThisWarning VEditor : may be unused
end
endtask
-function [6:0] func_encode_mode_tiled;
+function [10:0] func_encode_mode_tiled;
+ input repetitive;
+ input single;
+ input reset_frame;
input byte32; // 32-byte columns (0 - 16-byte columns)
input keep_open; // for 8 or less rows - do not close page between accesses
input [1:0] extra_pages; // number of extra pages that need to stay (not to be overwritten) in the buffer
@@ -2025,34 +2245,48 @@ function [6:0] func_encode_mode_tiled;
input write_mem; // write to memory mode (0 - read from memory)
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
+
+ reg [10:0] rslt;
begin
- func_encode_mode_tiled={byte32,keep_open,extra_pages,write_mem,enable,~chn_reset};
+ rslt = 0;
+ rslt[MCONTR_LINTILE_EN] = ~chn_reset;
+ rslt[MCONTR_LINTILE_NRESET] = enable;
+ rslt[MCONTR_LINTILE_WRITE] = write_mem;
+ rslt[MCONTR_LINTILE_EXTRAPG +: MCONTR_LINTILE_EXTRAPG_BITS] = extra_pages;
+ rslt[MCONTR_LINTILE_KEEP_OPEN] = keep_open;
+ rslt[MCONTR_LINTILE_BYTE32] = byte32;
+ rslt[MCONTR_LINTILE_RST_FRAME] = reset_frame;
+ rslt[MCONTR_LINTILE_SINGLE] = single;
+ rslt[MCONTR_LINTILE_REPEAT] = repetitive;
+// func_encode_mode_tiled={byte32,keep_open,extra_pages,write_mem,enable,~chn_reset};
+ func_encode_mode_tiled = rslt;
end
endfunction
-function [4:0] func_encode_mode_scanline;
+function [10:0] func_encode_mode_scanline;
+ input repetitive;
+ input single;
+ input reset_frame;
input [1:0] extra_pages; // number of extra pages that need to stay (not to be overwritten) in the buffer
// can be used for overlapping tile read access
input write_mem; // write to memory mode (0 - read from memory)
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
+
+ reg [10:0] rslt;
begin
- func_encode_mode_scanline={extra_pages,write_mem,enable,~chn_reset};
+ rslt = 0;
+ rslt[MCONTR_LINTILE_EN] = ~chn_reset;
+ rslt[MCONTR_LINTILE_NRESET] = enable;
+ rslt[MCONTR_LINTILE_WRITE] = write_mem;
+ rslt[MCONTR_LINTILE_EXTRAPG +: MCONTR_LINTILE_EXTRAPG_BITS] = extra_pages;
+ rslt[MCONTR_LINTILE_RST_FRAME] = reset_frame;
+ rslt[MCONTR_LINTILE_SINGLE] = single;
+ rslt[MCONTR_LINTILE_REPEAT] = repetitive;
+// func_encode_mode_scanline={extra_pages,write_mem,enable,~chn_reset};
+ func_encode_mode_scanline = rslt;
end
endfunction
-/*
-task enable_memcntrl_en_dis;
- input [3:0] chn;
- input en;
- begin
- if (en) begin
- ENABLED_CHANNELS = ENABLED_CHANNELS | (1<