making previous simulation tasks run on the full x393 code (3af47156) · Commits · Elphel / x393

.settings/com.elphel.vdt.iverilog.prefs

+4 −1

Original line number	Diff line number	Diff line
		com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->
		com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->
		eclipse.preferences.version=1
		iverilog_100_TopModulesOther=glbl<-@\#\#@->
		iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
		iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
		iverilog_77_Param_Exe=/usr/local/bin/iverilog
		iverilog_78_VVP_Exe=/usr/local/bin/vvp
		iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave

axi/cmprs_afi_mux.v

+3 −3

Original line number	Diff line number	Diff line
		@@ -32,7 +32,7 @@ module cmprs_afi_mux#(
		parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid address
		parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
		parameter CMPRS_AFIMUX_CYCBITS = 3,
		parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
		parameter AFI_MUX_BUF_LATENCY = 4'd2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
		)(
		// input rst,
		input mclk, // for command/status
		@@ -370,13 +370,13 @@ module cmprs_afi_mux#(
		.din ({ wvalid, wlast, afi_awid}), // input[0:0]
		.dout ({afi_wvalid, afi_wlast, afi_wid}) // output[0:0]
		);

		localparam [3:0] AFI_MUX_BUF_LATENCYM1 = AFI_MUX_BUF_LATENCY - 1;
		dly_16 #(
		.WIDTH(3)
		) afi_wdata_i (
		.clk (hclk), // input
		.rst (!en), // input
		.dly (AFI_MUX_BUF_LATENCY-1), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
		.dly (AFI_MUX_BUF_LATENCYM1), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
		.din ({wvalid, cur_chn}), // input[0:0]
		.dout ({wdata_en,wdata_sel}) // output[0:0]
		);

compressor_jp/cmprs_buf_average.v

+4 −4

Original line number	Diff line number	Diff line
		@@ -295,10 +295,10 @@ module cmprs_buf_average#(
		end

		// delay from the start of data output from color converter to copy subtract_dc to be valid when average values are set
		dly_16 #(.WIDTH(1)) i_cs_first_out_late (.clk(xclk),.rst(1'b0), .dly(15), .din(cs_first_out), .dout(cs_first_out_late));
		dly_16 #(.WIDTH(1)) i_color_enable_d (.clk(xclk),.rst(1'b0), .dly( 1), .din(color_enable), .dout(color_enable_d));
		dly_16 #(.WIDTH(1)) i_dv (.clk(xclk),.rst(1'b0), .dly( 2), .din(dv_pre3), .dout(dv));
		dly_16 #(.WIDTH(1)) i_ds (.clk(xclk),.rst(1'b0), .dly( 2), .din(ds_pre3), .dout(ds));
		dly_16 #(.WIDTH(1)) i_cs_first_out_late (.clk(xclk),.rst(1'b0), .dly(4'd15), .din(cs_first_out), .dout(cs_first_out_late));
		dly_16 #(.WIDTH(1)) i_color_enable_d (.clk(xclk),.rst(1'b0), .dly( 4'd1), .din(color_enable), .dout(color_enable_d));
		dly_16 #(.WIDTH(1)) i_dv (.clk(xclk),.rst(1'b0), .dly( 4'd2), .din(dv_pre3), .dout(dv));
		dly_16 #(.WIDTH(1)) i_ds (.clk(xclk),.rst(1'b0), .dly( 4'd2), .din(ds_pre3), .dout(ds));

		cmprs_tile_mode2_decode #(
		.CMPRS_COLOR18 (CMPRS_COLOR18),

compressor_jp/compressor393.v

+17 −17

Original line number	Diff line number	Diff line
		@@ -110,7 +110,7 @@ module compressor393 # (

		parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
		parameter CMPRS_AFIMUX_CYCBITS = 3,
		parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
		parameter AFI_MUX_BUF_LATENCY = 4'd2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used

		)(
		// input rst, // global reset
		@@ -275,12 +275,12 @@ module compressor393 # (
		.rq_in5 (status_rq_mux[5]), // input
		.start_in5 (status_start_mux[5]), // output

		.db_in6 (0), // input[7:0]
		.rq_in6 (0), // input
		.db_in6 (8'b0), // input[7:0]
		.rq_in6 (1'b0), // input
		.start_in6 (), // output

		.db_in7 (0), // input[7:0]
		.rq_in7 (0), // input
		.db_in7 (8'b0), // input[7:0]
		.rq_in7 (1'b0), // input
		.start_in7 (), // output

		.db_out (status_ad), // output[7:0]
		@@ -451,16 +451,16 @@ module compressor393 # (
		.fifo_count1 (fifo_count[8 +: 8]), // input[7:0]
		.fifo_rst2 (), // output
		.fifo_ren2 (), // output
		.fifo_rdata2 (0), // input[63:0]
		.fifo_rdata2 (64'b0), // input[63:0]
		.eof_written2 (), // output
		.fifo_flush2 (0), // input
		.fifo_count2 (0), // input[7:0]
		.fifo_flush2 (1'b0), // input
		.fifo_count2 (8'b0), // input[7:0]
		.fifo_rst3 (), // output
		.fifo_ren3 (), // output
		.fifo_rdata3 (0), // input[63:0]
		.fifo_rdata3 (64'b0), // input[63:0]
		.eof_written3 (), // output
		.fifo_flush3 (0), // input
		.fifo_count3 (0), // input[7:0]
		.fifo_flush3 (1'b0), // input
		.fifo_count3 (8'b0), // input[7:0]
		.afi_awaddr (afi0_awaddr), // output[31:0]
		.afi_awvalid (afi0_awvalid), // output
		.afi_awready (afi0_awready), // input
		@@ -524,16 +524,16 @@ module compressor393 # (
		.fifo_count1 (fifo_count[24 +: 8]), // input[7:0]
		.fifo_rst2 (), // output
		.fifo_ren2 (), // output
		.fifo_rdata2 (0), // input[63:0]
		.fifo_rdata2 (64'b0), // input[63:0]
		.eof_written2 (), // output
		.fifo_flush2 (0), // input
		.fifo_count2 (0), // input[7:0]
		.fifo_flush2 (1'b0), // input
		.fifo_count2 (8'b0), // input[7:0]
		.fifo_rst3 (), // output
		.fifo_ren3 (), // output
		.fifo_rdata3 (0), // input[63:0]
		.fifo_rdata3 (64'b0), // input[63:0]
		.eof_written3 (), // output
		.fifo_flush3 (0), // input
		.fifo_count3 (0), // input[7:0]
		.fifo_flush3 (1'b0), // input
		.fifo_count3 (8'b0), // input[7:0]
		.afi_awaddr (afi1_awaddr), // output[31:0]
		.afi_awvalid (afi1_awvalid), // output
		.afi_awready (afi1_awready), // input

compressor_jp/csconvert18a.v

+6 −6

Original line number	Diff line number	Diff line
		@@ -272,15 +272,15 @@ module csconvert18a(
		assign caddr = caddr_r;
		assign cwe = cwe_r;

		dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(15), .din(pre_first_in), .dout(strt_dly[0]));
		dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(15), .din(strt_dly[0]), .dout(strt_dly[1]));
		dly_16 #(.WIDTH(1)) i_strt (.clk(CLK),.rst(1'b0), .dly( 4), .din(strt_dly[1]), .dout(strt));
		dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(pre_first_in), .dout(strt_dly[0]));
		dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(strt_dly[0]), .dout(strt_dly[1]));
		dly_16 #(.WIDTH(1)) i_strt (.clk(CLK),.rst(1'b0), .dly( 4'd4), .din(strt_dly[1]), .dout(strt));

		// SRL16 i_strt_dly0 (.Q(strt_dly[0]), .D(pre_first_in), .CLK(CLK), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1)); // dly=15+1
		// SRL16 i_strt_dly1 (.Q(strt_dly[1]), .D(strt_dly[0]), .CLK(CLK), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1)); // dly=15+1
		// SRL16 i_strt (.Q(strt), .D(strt_dly[1]), .CLK(CLK), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0)); // dly=4+1
		dly_16 #(.WIDTH(1)) i_ystrt (.clk(CLK),.rst(1'b0), .dly(5), .din(strt), .dout(ystrt));
		dly_16 #(.WIDTH(1)) i_nxtline (.clk(CLK),.rst(1'b0), .dly(1), .din(!RST && ywe_r && (yaddr_r[3:0]==4'hf) && (yaddr_r[7:4]!=4'hf)), .dout(nxtline));
		dly_16 #(.WIDTH(1)) i_ystrt (.clk(CLK),.rst(1'b0), .dly(4'd5), .din(strt), .dout(ystrt));
		dly_16 #(.WIDTH(1)) i_nxtline (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(!RST && ywe_r && (yaddr_r[3:0]==4'hf) && (yaddr_r[7:4]!=4'hf)), .dout(nxtline));

		// SRL16 i_ystrt (.Q(ystrt), .D(strt), .CLK(CLK), .A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b0)); // dly=5+1
		// SRL16 i_nxtline(.Q(nxtline),.D(!RST && ywe_r && (yaddr_r[3:0]==4'hf) && (yaddr_r[7:4]!=4'hf)), .CLK(CLK), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0)); // dly=1+1
		@@ -595,7 +595,7 @@ end
		// new, q is signed char
		assign q[8:0]= ((cbcr[10]==cbcr[9]) && (!limit_diff \|\| (cbcr[10]==cbcr[8])))? cbcr[9:1]: {cbcr[10],limit_diff?cbcr[10]:(~cbcr[10]),{7{~cbcr[10]}}};

		dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(1), .din(ywe_r), .dout(cwe0));
		dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(ywe_r), .dout(cwe0));
		//SRL16 i_cwe0 (.D(ywe_r ), .Q(cwe0), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLK)); // dly=2=1+1

		always @ (posedge CLK) begin

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