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Commit 286a6494 authored by Andrey Filippov's avatar Andrey Filippov
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bug fixes in Verilog code

parent c8b52324
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Showing with 146 additions and 183 deletions
.project
View file @ 286a6494
......@@ -62,77 +62,77 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150311172942225.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150422150006515.log</location>
</link>
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<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150311172942225.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150422150006515.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150311172942225.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150422150006515.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150311172942225.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150422150006515.log</location>
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<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150311172942225.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150422150006515.log</location>
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<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150311172942225.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150422150006515.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150311172804030.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150422145717867.log</location>
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<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150313235008423.log</location>
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<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150311172804030.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150422145717867.log</location>
</link>
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<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150422150006515.log</location>
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<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150311172804030.log</location>
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<link>
<name>vivado_state/x393-opt-phys.dcp</name>
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<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150311172942225.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150422150006515.dcp</location>
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<link>
<name>vivado_state/x393-place.dcp</name>
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<location>/home/andrey/git/x393/vivado_state/x393-place-20150311172942225.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150422150006515.dcp</location>
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<name>vivado_state/x393-route.dcp</name>
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<location>/home/andrey/git/x393/vivado_state/x393-route-20150422150006515.dcp</location>
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<location>/home/andrey/git/x393/vivado_state/x393-synth-20150311172804030.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150422145717867.dcp</location>
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</projectDescription>
includes/x393_parameters.vh
View file @ 286a6494
......@@ -244,5 +244,7 @@
parameter MCNTRL_TEST01_STATUS_REG_CHN1_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f, // status/readback register for channel 4
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
\ No newline at end of file
memctrl/cmd_encod_linear_rd.v
View file @ 286a6494
......@@ -27,7 +27,8 @@ module cmd_encod_linear_rd #(
parameter COLADDR_NUMBER= 10,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter RSEL= 1'b1
) (
input rst,
input clk,
......@@ -125,10 +126,10 @@ module cmd_encod_linear_rd #(
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) | (1 << ENC_DCI);
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
......
memctrl/cmd_encod_linear_rw.v
View file @ 286a6494
......@@ -26,7 +26,9 @@ module cmd_encod_linear_rw#(
parameter COLADDR_NUMBER= 10,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) (
input rst,
input clk,
......@@ -58,7 +60,8 @@ module cmd_encod_linear_rw#(
.COLADDR_NUMBER (COLADDR_NUMBER),
.NUM_XFER_BITS (NUM_XFER_BITS),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
.CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL)
) cmd_encod_linear_rd_i (
.rst (rst), // input
.clk (clk), // input
......@@ -78,7 +81,8 @@ module cmd_encod_linear_rw#(
.COLADDR_NUMBER (COLADDR_NUMBER),
.NUM_XFER_BITS (NUM_XFER_BITS),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
.CMD_DONE_BIT (CMD_DONE_BIT),
.WSEL (WSEL)
) cmd_encod_linear_wr_i (
.rst (rst), // input
.clk (clk), // input
......
memctrl/cmd_encod_tiled_32_rd.v
View file @ 286a6494
......@@ -47,8 +47,8 @@ module cmd_encod_tiled_32_rd #(
parameter COLADDR_NUMBER= 10,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter RSEL= 1'b1 // Late/early READ commands
) (
input rst,
input clk,
......@@ -227,20 +227,20 @@ module cmd_encod_tiled_32_rd #(
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
// loop:
4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
// end loop
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
// do not combine this NOP - ENC_CMD_READ + ENC_NOP enables autoprecharge
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (1 << ENC_BUF_PGNEXT);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (RSEL << ENC_SEL) | (1 << ENC_BUF_PGNEXT);
4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
4'he: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
......
memctrl/cmd_encod_tiled_32_rw.v
View file @ 286a6494
......@@ -25,7 +25,10 @@ module cmd_encod_tiled_32_rw #(
parameter COLADDR_NUMBER= 10,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) (
input rst,
input clk,
......@@ -57,7 +60,8 @@ module cmd_encod_tiled_32_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
.CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (clk), // input
......@@ -80,7 +84,8 @@ module cmd_encod_tiled_32_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
.CMD_DONE_BIT (CMD_DONE_BIT),
.WSEL (WSEL)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.clk (clk), // input
......
memctrl/cmd_encod_tiled_mux.v
View file @ 286a6494
......@@ -750,7 +750,7 @@ module cmd_encod_tiled_mux #(
`endif
;
always @ (posedge clk) begin
if (start_rd_w || start_wr_w) begin
if (start_rd_w || start_wr_w || start_rd32_w || start_wr32_w) begin
bank_r <= bank_w;
row_r <= row_w;
col_r <= col_w;
......
memctrl/cmd_encod_tiled_rd.v
View file @ 286a6494
......@@ -48,8 +48,8 @@ module cmd_encod_tiled_rd #(
parameter COLADDR_NUMBER= 10,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter RSEL= 1'b1
) (
input rst,
input clk,
......@@ -227,15 +227,15 @@ module cmd_encod_tiled_rd #(
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (1 << ENC_BUF_PGNEXT);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI) | (RSEL << ENC_SEL);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (RSEL << ENC_SEL) | (1 << ENC_BUF_PGNEXT);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
......
memctrl/cmd_encod_tiled_rw.v
View file @ 286a6494
......@@ -25,7 +25,9 @@ module cmd_encod_tiled_rw #(
parameter COLADDR_NUMBER= 10,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) (
input rst,
input clk,
......@@ -57,7 +59,8 @@ module cmd_encod_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
.CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (clk), // input
......@@ -80,7 +83,8 @@ module cmd_encod_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
.CMD_DONE_BIT (CMD_DONE_BIT),
.WSEL (WSEL)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.clk (clk), // input
......
memctrl/mcntrl393.v
View file @ 286a6494
......@@ -212,8 +212,9 @@ module mcntrl393 #(
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter BUFFER_DEPTH32= 10 // Block rum buffer depth on a 32-bit port
parameter BUFFER_DEPTH32= 10, // Block RAM buffer depth on a 32-bit port
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) (
input rst_in,
input clk_in,
......@@ -1182,11 +1183,13 @@ module mcntrl393 #(
// encoder for scanline read/write
cmd_encod_linear_rw #(
.ADDRESS_NUMBER(ADDRESS_NUMBER),
.COLADDR_NUMBER(COLADDR_NUMBER),
.NUM_XFER_BITS(NUM_XFER_BITS),
.CMD_PAUSE_BITS(CMD_PAUSE_BITS),
.CMD_DONE_BIT(CMD_DONE_BIT)
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.NUM_XFER_BITS (NUM_XFER_BITS),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL),
.WSEL (WSEL)
) cmd_encod_linear_rw_i (
.rst (rst), // input
.clk (mclk), // input
......@@ -1260,7 +1263,9 @@ module mcntrl393 #(
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS)
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.RSEL (RSEL),
.WSEL (WSEL)
) cmd_encod_tiled_16_rw_i (
.rst (rst), // input
.clk (mclk), // input
......@@ -1286,7 +1291,9 @@ module mcntrl393 #(
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS)
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.RSEL (RSEL),
.WSEL (WSEL)
) cmd_encod_tiled_32_rw_i (
.rst (rst), // input
.clk (mclk), // input
......
x393.v
View file @ 286a6494
......@@ -586,7 +586,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS (MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
.BUFFER_DEPTH32 (BUFFER_DEPTH32)
.BUFFER_DEPTH32 (BUFFER_DEPTH32),
.RSEL (RSEL),
.WSEL (WSEL)
) mcntrl393_i (
.rst_in (axi_rst), // input
.clk_in (axi_aclk), // == axird_bram_rclk SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #mcntrl393_i:clk_in to constant 0
......
x393_testbench01.sav
View file @ 286a6494
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Wed Apr 22 06:13:24 2015
[*] Wed Apr 22 20:56:33 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150422000228091.lxt"
[dumpfile_mtime] "Wed Apr 22 06:07:54 2015"
[dumpfile_size] 272771001
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150422144335663.lxt"
[dumpfile_mtime] "Wed Apr 22 20:53:12 2015"
[dumpfile_size] 598623495
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 42303990
[timestart] 0
[size] 1823 1180
[pos] 2071 0
*-12.659416 42321294 42321138 42326138 42321258 42321294 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] 2074 -3
*-23.659416 42821328 42321138 42326138 42321258 42321294 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.ddr3_i.
[treeopen] x393_testbench01.x393_i.
......@@ -52,10 +52,12 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 373
[sst_width] 234
[signals_width] 336
[sst_expanded] 1
[sst_vpaned_height] 636
[sst_vpaned_height] 641
@820
x393_testbench01.TEST_TITLE[639:0]
@c00200
-top_simulation
@28
......@@ -254,7 +256,7 @@ x393_testbench01.wait_status_condition.status_mode[1:0]
@1401200
-WAIT_STATUS_CONDITION
-top_simulation
@c00200
@c00201
-mem_clocks
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_in[0]
......@@ -265,7 +267,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.iclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.iclk[0]
@1401200
@1401201
-mem_clocks
@c00200
-write_delays
......@@ -1008,85 +1010,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.set[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.want[0]
@1401200
-refresh
@800200
-DDR3_wrap
@28
x393_testbench01.x393_i.mclk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_tri[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_tri[7:0]
@28
x393_testbench01.ddr3_i.SDCLK_D[0]
@22
x393_testbench01.ddr3_i.SDA_D[14:0]
@28
x393_testbench01.ddr3_i.SDBA_D[2:0]
x393_testbench01.ddr3_i.SDRAS_D[0]
x393_testbench01.ddr3_i.SDCAS_D[0]
x393_testbench01.ddr3_i.SDWE_D[0]
x393_testbench01.ddr3_i.DQSL[0]
x393_testbench01.ddr3_i.DQSL_H3[0]
x393_testbench01.ddr3_i.DQSL_D[0]
x393_testbench01.ddr3_i.DQSL_DH1[0]
x393_testbench01.ddr3_i.DQSL_DH2[0]
x393_testbench01.ddr3_i.DQSL_DH3[0]
x393_testbench01.ddr3_i.DQSU_D[0]
@22
x393_testbench01.ddr3_i.SDD[15:0]
x393_testbench01.ddr3_i.SDD_H3[15:0]
x393_testbench01.ddr3_i.SDD_D[15:0]
@28
x393_testbench01.ddr3_i.SDODT_D[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mclk[0]
@22
x393_testbench01.ddr3_i.SDD[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dout[63:0]
@28
x393_testbench01.ddr3_i.en_dq_dl[1:0]
x393_testbench01.ddr3_i.en_dq_d0[1:0]
x393_testbench01.ddr3_i.en_dq_d1[1:0]
x393_testbench01.ddr3_i.en_dq_out[1:0]
x393_testbench01.ddr3_i.en_dq_d3[1:0]
x393_testbench01.ddr3_i.en_dq_in[1:0]
x393_testbench01.ddr3_i.en_dqs_dl[1:0]
x393_testbench01.ddr3_i.en_dqs_out[1:0]
x393_testbench01.ddr3_i.en_dqs_in[1:0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dqsl[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.iclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_dly[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dout[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dqsu[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.iclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dq_block[0].dq_i.dq_dly[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dout[31:0]
@200
-
-
@1000200
-DDR3_wrap
@800200
-dqs0_dq0_out
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_out_dly_i.data_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_out_dly_i.data_out[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.d_ser[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_data_dly[0]
@1000200
-dqs0_dq0_out
@200
-
-
@800200
@c00200
-DDR3
@28
x393_testbench01.x393_i.SDRST[0]
......@@ -1108,7 +1032,7 @@ x393_testbench01.x393_i.SDDMU[0]
@22
x393_testbench01.x393_i.SDD[15:0]
x393_testbench01.x393_i.SDODT[0]
@1000200
@1401200
-DDR3
@c00200
-phy_cmd_
......@@ -1828,7 +1752,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq[0]
@1000200
-PS_PIO
@800200
@c00200
-LINEAR_CH1
@200
-
......@@ -2284,7 +2208,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want[0]
@1000200
@1401200
-LINEAR_CH1
@c00200
-TILED_CH2
......@@ -3516,13 +3440,13 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_done[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause[0]
@800022
@c00022
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
(2)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
@1001200
@1401200
-group_end
@200
-
......
x393_testbench01.tf
View file @ 286a6494
......@@ -29,18 +29,18 @@
// Disabled already passed test to speedup simulation
//`define TEST_WRITE_LEVELLING 1
//`define TEST_READ_PATTERN 1
`define TEST_WRITE_BLOCK 1
`define TEST_READ_BLOCK 1
//`define TEST_WRITE_BLOCK 1
//`define TEST_READ_BLOCK 1
//`define TEST_SCANLINE_WRITE
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_SCANLINE_READ
`define TEST_READ_SHOW 1
//`define TEST_TILED_WRITE 0
//`define TEST_TILED_WRITE 1
`define TEST_TILED_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_TILED_READ 1
//`define TEST_TILED_WRITE32 1
//`define TEST_TILED_READ32 1
`define TEST_TILED_WRITE32 1
`define TEST_TILED_READ32 1
module x393_testbench01 #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
......@@ -80,6 +80,7 @@ module x393_testbench01 #(
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
// wire MEMCLK;
reg [639:0] TEST_TITLE;
// Simulation signals
reg [11:0] ARID_IN_r;
reg [31:0] ARADDR_IN_r;
......@@ -296,23 +297,28 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
axi_set_dqs_odelay_nominal;
`ifdef TEST_WRITE_LEVELLING
$display("===================== TEST_WRITE_LEVELLING =========================");
TEST_TITLE = "WRITE_LEVELLING";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_write_levelling;
`endif
`ifdef TEST_READ_PATTERN
$display("===================== TEST_READ_PATTERN =========================");
TEST_TITLE = "READ_PATTERN";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_read_pattern;
`endif
`ifdef TEST_WRITE_BLOCK
$display("===================== TEST_WRITE_BLOCK =========================");
TEST_TITLE = "WRITE_BLOCK";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_write_block;
`endif
`ifdef TEST_READ_BLOCK
$display("===================== TEST_READ_BLOCK =========================");
TEST_TITLE = "READ_BLOCK";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_read_block;
`endif
`ifdef TESTL_SHORT_SCANLINE
$display("===================== TESTL_SHORT_SCANLINE =========================");
TEST_TITLE = "TESTL_SHORT_SCANLINE";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
......@@ -369,7 +375,8 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_SCANLINE_WRITE
$display("===================== TEST_SCANLINE_WRITE =========================");
TEST_TITLE = "SCANLINE_WRITE";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
......@@ -381,7 +388,8 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_SCANLINE_READ
$display("===================== TEST_SCANLINE_READ =========================");
TEST_TITLE = "SCANLINE_READ";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_scanline_read (
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
......@@ -394,7 +402,8 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_TILED_WRITE
$display("===================== TEST_TILED_WRITE =========================");
TEST_TITLE = "TILED_WRITE";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_tiled_write (
2, // [3:0] channel;
0, // byte32;
......@@ -411,7 +420,8 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_TILED_READ
$display("===================== TEST_TILED_READ =========================");
TEST_TITLE = "TILED_READ";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_tiled_read (
2, // [3:0] channel;
0, // byte32;
......@@ -429,9 +439,10 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_TILED_WRITE32
$display("===================== TEST_TILED_WRITE32 =========================");
TEST_TITLE = "TILED_WRITE32";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_tiled_write (
4, // 2, // [3:0] channel;
2, // 4, // 2, // [3:0] channel;
1, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
......@@ -446,9 +457,10 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_TILED_READ32
$display("===================== TEST_TILED_READ32 =========================");
TEST_TITLE = "TILED_READ32";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_tiled_read (
4, //2, // [3:0] channel;
2, // 4, //2, // [3:0] channel;
1, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
......@@ -461,6 +473,8 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
TILE_HEIGHT,
TILE_VSTEP);
`endif
TEST_TITLE = "ALL_DONE";
$display("===================== TEST_%s =========================",TEST_TITLE);
#20000;
$finish;
end
......@@ -709,7 +723,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.DQSU (DQSU), // inout
.NDQSU (NDQSU), // inout
.DUMMY_TO_KEEP(DUMMY_TO_KEEP) // to keep PS7 signals from "optimization"
// ,.MEMCLK (MEMCLK)
,.MEMCLK (1'b0)
);
// just to simplify extra delays in tri-state memory bus - provide output enable
wire WRAP_MCLK=x393_i.mclk;
......
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