Commit 239f94f6 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev

test commit

parent 541ee368
......@@ -39,8 +39,10 @@ from time import sleep
import vrlg # global parameters
import x393_axi_control_status
import shutil
FPGA_RST_CTRL = 0xf8000240
FPGA0_THR_CTRL = 0xf8000178
FPGA_LVL_SHFTR = 0xf8000900 # 0xf: all enabled, 0x0 - disable all
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