Skip to content

X
x393
Commit 239f94f6 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev
Browse files
Options

test commit

parent 541ee368
Show whitespace changes
Inline Side-by-side
Showing with 2 additions and 0 deletions
py393/x393_utils.py
View file @ 239f94f6
......@@ -39,8 +39,10 @@ from time import sleep
import vrlg # global parameters
import x393_axi_control_status
import shutil
DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
#DEFAULT_BITFILE="/tmp/x393.bit"
FPGA_RST_CTRL = 0xf8000240
FPGA0_THR_CTRL = 0xf8000178
FPGA_LVL_SHFTR = 0xf8000900 # 0xf: all enabled, 0x0 - disable all
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment