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x393
Commit 239f94f6 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev
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test commit

parent 541ee368
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py393/x393_utils.py
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...@@ -39,8 +39,10 @@ from time import sleep ...@@ -39,8 +39,10 @@ from time import sleep
import vrlg # global parameters import vrlg # global parameters
import x393_axi_control_status import x393_axi_control_status
import shutil import shutil
DEFAULT_BITFILE="/usr/local/verilog/x393.bit" DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
#DEFAULT_BITFILE="/tmp/x393.bit" #DEFAULT_BITFILE="/tmp/x393.bit"
FPGA_RST_CTRL = 0xf8000240 FPGA_RST_CTRL = 0xf8000240
FPGA0_THR_CTRL = 0xf8000178 FPGA0_THR_CTRL = 0xf8000178
FPGA_LVL_SHFTR = 0xf8000900 # 0xf: all enabled, 0x0 - disable all FPGA_LVL_SHFTR = 0xf8000900 # 0xf: all enabled, 0x0 - disable all
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