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x393
Commit 225fccd0 authored by Andrey Filippov's avatar Andrey Filippov
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simulating multiple simultanerous sesnor/compressor channels

parent a500d197
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Showing with 559 additions and 140 deletions
axi/cmprs_afi_mux.v
View file @ 225fccd0
......@@ -117,7 +117,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
output [ 1:0] afi_awlock,
output [ 3:0] afi_awcache,
output [ 2:0] afi_awprot,
output [ 3:0] afi_awlen,
output reg [ 3:0] afi_awlen,
output [ 1:0] afi_awsize,
output [ 1:0] afi_awburst,
output [ 3:0] afi_awqos,
......@@ -220,6 +220,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
wire [ 3:0] chunk_ptr_ra;
wire [ 7:0] items_left = counts_corr2[8] ? left_to_eof[(winner2 * 8) +: 8] : counts_corr2[7:0];
reg [5:0] afi_awid_r;
......@@ -246,9 +247,9 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
assign {fifo_ren3, fifo_ren2, fifo_ren1, fifo_ren0} = fifo_ren;
assign afi_awaddr = {chunk_addr,5'b0};
assign afi_awid = {1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
assign afi_awid = afi_awid_r; // {1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
assign afi_awvalid = awvalid[1];
assign afi_awlen = {wleft[3:2],2'b11};
// assign afi_awlen = {wleft[3:2],2'b11};
assign afi_wdata = wdata;
// assign afi_bready = 1'b1; // always ready
......@@ -426,28 +427,33 @@ items_left
if (pre_busy_w) chunk_inc <= (|counts_corr2[7:2])?
3'h4 :
({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);
if (awvalid[0]) afi_awid_r <={1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
if (awvalid[0]) afi_awlen <= {wleft[3:2],2'b11};
end
// delay write channel controls signal to match data latency. wid bits will be optimized (6 -> 3)
dly_16 #(
.WIDTH(8)
.WIDTH(2) // 8)
) afi_wx_i (
.clk (hclk), // input
.rst (!en), // input
.dly (AFI_MUX_BUF_LATENCY), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
.din ({ wvalid, wlast, afi_awid}), // input[0:0]
.dout ({afi_wvalid, afi_wlast, afi_wid}) // output[0:0]
.din ({ wvalid, wlast}), // , afi_awid_r}), // afi_awid}), // input[0:0]
.dout ({afi_wvalid, afi_wlast}) //, afi_wid}) // output[0:0]
);
localparam [3:0] AFI_MUX_BUF_LATENCYM1 = AFI_MUX_BUF_LATENCY - 1;
dly_16 #(
.WIDTH(3)
.WIDTH(9) // 3)
) afi_wdata_i (
.clk (hclk), // input
.rst (!en), // input
.dly (AFI_MUX_BUF_LATENCYM1), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
.din ({wvalid, cur_chn}), // input[0:0]
.dout ({wdata_en,wdata_sel}) // output[0:0]
.din ({wvalid, cur_chn, afi_awid_r}), //}), // input[0:0]
.dout ({wdata_en, wdata_sel, afi_wid}) // }) // output[0:0]
);
cmd_deser #(
......@@ -467,7 +473,7 @@ items_left
.we (cmd_we) // output
);
wire [53:0] chunk_ptr_rd01; // [0:1];
wire [53:0] chunk_ptr_rd01; // [0:1]; // combines 2 pointers - write one and write responce one
cmprs_afi_mux_ptr cmprs_afi_mux_ptr_i (
.hclk (hclk), // input
......
includes/tasks_tests_memory.vh
View file @ 225fccd0
......@@ -133,8 +133,9 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
......@@ -145,6 +146,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
start64, lo_addr64, size64, $time);
mode= func_encode_mode_scanline(
disable_need,
repetitive,
single,
reset_frame,
......@@ -213,8 +215,9 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
......@@ -243,6 +246,7 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
disable_need,
repetitive,
single,
reset_frame,
......@@ -351,8 +355,10 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
......@@ -381,6 +387,7 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
disable_need,
repetitive,
single,
reset_frame,
......@@ -460,8 +467,9 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
......@@ -493,6 +501,7 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
disable_need,
repetitive,
single,
reset_frame,
......@@ -590,8 +599,9 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
......@@ -623,6 +633,7 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
disable_need,
repetitive,
single,
reset_frame,
......
includes/x393_parameters.vh
View file @ 225fccd0
......@@ -50,7 +50,7 @@
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
......@@ -200,7 +200,7 @@
// parameter CMD0_ADDR = 'h0800, // AXI write to command sequence memory
// parameter CMD0_ADDR_MASK = 'h1800, // AXI read address mask for the command sequence memory
parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
parameter MCNTRL_PS_MASK= 'h7e0, // both channels 0 and 1
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
parameter MCNTRL_PS_EN_RST= 'h0,
parameter MCNTRL_PS_CMD= 'h1,
......@@ -271,7 +271,9 @@
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h7f0,
......@@ -522,7 +524,7 @@
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter CMPRS_NUM_AFI_CHN = 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
parameter CMPRS_AFIMUX_RADDR0= 'h40, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
......@@ -658,7 +660,7 @@
// Command sequencers parameters
parameter CMDFRAMESEQ_ADDR_BASE= 'h780,
parameter CMDFRAMESEQ_ADDR_INC= 'h20,
parameter CMDFRAMESEQ_MASK= 'h3e0,
parameter CMDFRAMESEQ_MASK= 'h7e0,
parameter CMDFRAMESEQ_DEPTH = 64, // 32/64/128
parameter CMDFRAMESEQ_ABS = 0,
parameter CMDFRAMESEQ_REL = 16,
......
includes/x393_tasks_status.vh
View file @ 225fccd0
......@@ -113,6 +113,7 @@ endtask
task read_all_status;
begin
$display (" read_all_status @%t",$time);
read_status (MCONTR_PHY_STATUS_REG_ADDR);
read_status (MCONTR_TOP_STATUS_REG_ADDR);
read_status (MCNTRL_PS_STATUS_REG_ADDR);
......
memctrl/mcntrl393.v
View file @ 225fccd0
......@@ -50,7 +50,7 @@ module mcntrl393 #(
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
......@@ -166,7 +166,7 @@ module mcntrl393 #(
parameter CMD_DONE_BIT= 10,
//
parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
parameter MCNTRL_PS_MASK= 'h7e0, // both channels 0 and 1
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
parameter MCNTRL_PS_EN_RST= 'h0,
parameter MCNTRL_PS_CMD= 'h1,
......@@ -240,7 +240,8 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10 // read/write pages until disabled
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
) (
input rst_in,
......@@ -1057,7 +1058,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_linear_wr_sensor_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1121,7 +1123,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_tiled_rd_compressor_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1192,7 +1195,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_linear_rw_chn1_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1252,7 +1256,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_linear_rw_chn3_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1315,7 +1320,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_tiled_rw_chn2_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1382,7 +1388,9 @@ module mcntrl393 #(
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_tiled_rw_chn4_i (
.mrst (mrst), // input
.mclk (mclk), // input
......
memctrl/mcntrl_linear_rw.v
View file @ 225fccd0
......@@ -56,7 +56,8 @@ module mcntrl_linear_rw #(
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10 // read/write pages until disabled
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
)(
input mrst,
input mclk,
......@@ -149,7 +150,7 @@ module mcntrl_linear_rw #(
// wire cmd_wrmem; //=MCNTRL_SCANLINE_WRITE_MODE; // 0: read from memory, 1:write to memory
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
wire disable_need; // do not assert need, only want
wire repeat_frames; // mode bit
wire single_frame_w; // pulse
wire rst_frame_num_w;
......@@ -190,7 +191,7 @@ module mcntrl_linear_rw #(
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
reg [10:0] mode_reg;//mode register: {repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [11:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
......@@ -232,7 +233,7 @@ module mcntrl_linear_rw #(
// Set parameter registers
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[10:0]; // 4:0]; // [4:0];
else if (set_mode_w) mode_reg <= cmd_data[11:0]; // 4:0]; // [4:0];
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
......@@ -335,6 +336,7 @@ module mcntrl_linear_rw #(
assign cmd_wrmem = mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory
assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we;
......@@ -449,7 +451,7 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem;
if (mrst) need_r <= 0;
if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
......
memctrl/mcntrl_tiled_rw.v
View file @ 225fccd0
......@@ -63,7 +63,9 @@ module mcntrl_tiled_rw#(
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10 // read/write pages until disabled
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
)(
input mrst,
input mclk,
......@@ -161,7 +163,7 @@ module mcntrl_tiled_rw#(
wire cmd_wrmem; //= MCNTRL_TILED_WRITE_MODE; // 0: read from memory, 1:write to memory (change to parameter?)
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
wire byte32; // use 32-byte wide colums in each tile (0 - use 16-byte ones)
wire disable_need; // do not assert need, only want
wire repeat_frames; // mode bit
wire single_frame_w; // pulse
wire rst_frame_num_w;
......@@ -211,7 +213,7 @@ module mcntrl_tiled_rw#(
// reg [5:0] mode_reg;//mode register: {write_mode,keep_open,extra_pages[1:0],enable,!reset}
// reg [6:0] mode_reg;//mode register: {byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [10:0] mode_reg;//mode register: {repet,single,rst_frame,na,byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [11:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na,byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [LAST_FRAME_BITS-1:0] last_frame_number;
......@@ -266,7 +268,7 @@ module mcntrl_tiled_rw#(
// Set parameter registers
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[10:0]; // [5:0];
else if (set_mode_w) mode_reg <= cmd_data[11:0]; // [5:0];
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
......@@ -382,7 +384,7 @@ module mcntrl_tiled_rw#(
assign keep_open= mode_reg[MCONTR_LINTILE_KEEP_OPEN]; // keep banks open (will be used only if number of rows <= 8
assign byte32= mode_reg[MCONTR_LINTILE_BYTE32]; // use 32-byte wide columns in each tile (false - 16-byte)
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign status_data= {frame_finished_r, busy_r};
assign pgm_param_w= cmd_we;
assign rowcol_inc= frame_full_width;
......@@ -487,16 +489,16 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (mrst) xfer_start32_wr_r <= 0;
else xfer_start32_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && byte32;
if (mrst) continued_tile <= 1'b0;
if (mrst) continued_tile <= 1'b0;
else if (chn_rst) continued_tile <= 1'b0;
else if (frame_start_r[0]) continued_tile <= 1'b0;
else if (xfer_start_r[0]) continued_tile <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change
if (mrst) need_r <= 0;
if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
if (mrst) want_r <= 0;
if (mrst) want_r <= 0;
else if (chn_rst || xfer_grant) want_r <= 0;
else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
......
memctrl/memctrl16.v
View file @ 225fccd0
......@@ -25,7 +25,7 @@
module memctrl16 #(
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
......
memctrl/phy/mcontr_sequencer.v
View file @ 225fccd0
......@@ -24,7 +24,7 @@ module mcontr_sequencer #(
//command interface parameters
//0x1080..10ff - 8- bit data - to set various delay values
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
// 0x1080..109f - set delay for SDD0-SDD7
// 0x10a0..10bf - set delay for SDD8-SDD15
// 0x10c0..10df - set delay for SD_CMDA
......
simulation_modules/simul_axi_hp_wr.v
View file @ 225fccd0
......@@ -111,6 +111,7 @@ Alex
wire enough_data; // enough data to start a new burst
wire [11:3] next_wr_address; // bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit)
reg [31:0] write_address;
reg [5:0] awid_r; // awid registered with write_address
wire fifo_wd_rd; // read data fifo
wire last_confirmed_write;
......@@ -131,6 +132,7 @@ Alex
reg [ 1:0] wburst; // registered burst type
reg [ 3:0] wlen; // registered awlen type (for wrapped over transfers)
wire start_write_burst_w;
reg start_write_burst_r; // next after start_write_burst_w
wire write_in_progress_w; // should go inactive last confirmed upstream cycle
reg write_in_progress;
reg [ 7:0] num_full_data = 0; // Number of full data bursts in FIFO
......@@ -229,29 +231,31 @@ Alex
assign sim_wr_stb=wstrb_out;
always @ (posedge aclk) begin
if (start_write_burst_w) begin
if (awid_out != wid_out) begin
$display ("%m: at time %t ERROR: awid=%h, awid=%h",$time,awid_out,wid_out);
// $stop;
start_write_burst_r <= start_write_burst_w;
if (start_write_burst_r) begin
if (awid_r != wid_out) begin
$display ("%m: at time %t ERROR: awid=%h, wid=%h",$time,awid_out,wid_out);
$stop;
end
end
if (start_write_burst_w) begin
if (awsize_out != 2'h3) begin
$display ("%m: at time %t ERROR: awsize_out=%h, currently only 'h3 (8 bytes) is valid",$time,awsize_out);
// $stop;
$stop;
end
end
if (awvalid && awready) begin
if (((awlock ^ VALID_AWLOCK) & VALID_AWLOCK_MASK) != 0) begin
$display ("%m: at time %t ERROR: awlock = %h, valid %h with mask %h",$time, awlock, VALID_AWLOCK, VALID_AWLOCK_MASK);
// $stop;
$stop;
end
if (((awcache ^ VALID_AWCACHE) & VALID_AWCACHE_MASK) != 0) begin
$display ("%m: at time %t ERROR: awcache = %h, valid %h with mask %h",$time, awcache, VALID_AWCACHE, VALID_AWCACHE_MASK);
// $stop;
$stop;
end
if (((awprot ^ VALID_AWPROT) & VALID_AWPROT_MASK) != 0) begin
$display ("%m: at time %t ERROR: awprot = %h, valid %h with mask %h",$time, awprot, VALID_AWPROT, VALID_AWPROT_MASK);
// $stop;
$stop;
end
end
end
......@@ -276,6 +280,9 @@ Alex
else if (start_write_burst_w) write_address <= awaddr_out; // precedence over inc
else if (fifo_wd_rd) write_address <= {write_address[31:12],next_wr_address[11:3],write_address[2:0]};
if (rst) awid_r <= 6'bx;
else if (start_write_burst_w) awid_r <= awid_out; // precedence over inc
end
......@@ -304,7 +311,7 @@ fifo_same_clock_fill #( .DATA_WIDTH(79),.DATA_DEPTH(7))
.sync_rst (1'b0),
.we(wvalid && wready),
.re(fifo_wd_rd), //start_write_burst_w), // wrong
.data_in({wlast, wid[5:0], wstrb[7:0], wdata[63:0]}),
.data_in({wlast, wid[5:0], wstrb[7:0], wdata[63:0]}),
.data_out({wlast_out,wid_out[5:0], wstrb_out[7:0], wdata_out[63:0]}),
.nempty(w_nempty),
.half_full(), //w_half_full),
......
simulation_modules/simul_saxi_gp_wr.v
View file @ 225fccd0
......@@ -191,7 +191,7 @@ Alex
always @ (posedge aclk) begin
if (start_write_burst_w) begin
if (awid_out != wid_out) begin
$display ("%m: at time %t ERROR: awid=%h, awid=%h",$time,awid_out,wid_out);
$display ("%m: at time %t ERROR: awid=%h, wid=%h",$time,awid_out,wid_out);
$stop;
end
......
timing/camsync393.v
View file @ 225fccd0
......@@ -550,10 +550,10 @@ module camsync393 #(
else dly_cntr_chn3[31:0] <= input_dly_chn3[31:0];
/// bypass delay to trig_r in internal trigger mode
trig_r[0] <= (input_use_intern && (master_chn ==0)) ? (start_late && start_en):(dly_cntr_run_d[0] && !dly_cntr_run[0]);
trig_r[1] <= (input_use_intern && (master_chn ==1)) ? (start_late && start_en):(dly_cntr_run_d[1] && !dly_cntr_run[1]);
trig_r[2] <= (input_use_intern && (master_chn ==2)) ? (start_late && start_en):(dly_cntr_run_d[2] && !dly_cntr_run[2]);
trig_r[3] <= (input_use_intern && (master_chn ==3)) ? (start_late && start_en):(dly_cntr_run_d[3] && !dly_cntr_run[3]);
trig_r[0] <= (input_use_intern && (master_chn ==0)) ? (start_late && start_en): dly_cntr_end[0];
trig_r[1] <= (input_use_intern && (master_chn ==1)) ? (start_late && start_en): dly_cntr_end[1];
trig_r[2] <= (input_use_intern && (master_chn ==2)) ? (start_late && start_en): dly_cntr_end[2];
trig_r[3] <= (input_use_intern && (master_chn ==3)) ? (start_late && start_en): dly_cntr_end[3];
/// 64-bit serial receiver (52 bit payload, 6 pre magic and 6 bits post magic for error checking
if (!rcv_run_or_deaf) bit_rcv_duration[7:0] <= bit_length_short[7:0]; // 3/4 bit length-1
......
util_modules/cmd_frame_sequencer.v
View file @ 225fccd0
......@@ -43,7 +43,7 @@
module cmd_frame_sequencer#(
parameter CMDFRAMESEQ_ADDR= 'h780,
parameter CMDFRAMESEQ_MASK= 'h3e0,
parameter CMDFRAMESEQ_MASK= 'h7e0,
parameter AXI_WR_ADDR_BITS = 14,
parameter CMDFRAMESEQ_DEPTH = 64, // 32/64/128
parameter CMDFRAMESEQ_ABS = 0,
......
wrap/idelay_fine_pipe.v
View file @ 225fccd0
......@@ -45,8 +45,13 @@ module idelay_fine_pipe
else if (set) fdly <= fdly_pre;
end
`ifdef SIMULATION
reg [7:0] delay_r;
always @ (posedge clk) begin
if (rst) delay_r <= DELAY_VALUE;
else if (ld) delay_r <= delay;
end
always @ (fdly_pre) begin
if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);
if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d (0x%x) @ %t", delay_r, fdly_pre,$time);
end
`endif // SIMULATION
`ifndef IGNORE_ATTR
......
wrap/odelay_fine_pipe.v
View file @ 225fccd0
......@@ -44,8 +44,13 @@ module odelay_fine_pipe
else if (set) fdly <= fdly_pre;
end
`ifdef SIMULATION
reg [7:0] delay_r;
always @ (posedge clk) begin
if (rst) delay_r <= DELAY_VALUE;
else if (ld) delay_r <= delay;
end
always @ (fdly_pre) begin
if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);
if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d (0x%x) @ %t", fdly_pre, delay_r,$time);
end
`endif //SIMULATION
......
x393.v
View file @ 225fccd0
......@@ -1064,6 +1064,7 @@ assign axi_grst = axi_rst_pre;
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.BUFFER_DEPTH32 (BUFFER_DEPTH32),
.RSEL (RSEL),
.WSEL (WSEL)
......@@ -1964,7 +1965,7 @@ assign axi_grst = axi_rst_pre;
.data_out_stb (logger_stb), // output @mclk
.debug_state() // output[31:0]
);
/* Instance template for module mult_saxi_wr_inbuf */
mult_saxi_wr_inbuf #(
.MULT_SAXI_HALF_BRAM_IN (MULT_SAXI_HALF_BRAM_IN),
.MULT_SAXI_BSLOG (MULT_SAXI_BSLOG0),
......
x393_testbench02.tf
View file @ 225fccd0
......@@ -110,7 +110,8 @@ parameter EXTERNAL_TIMESTAMP = 1 ; // embed local timestamp, 1 - embed rec
parameter CLK3_PER = 83.33; //12MHz
parameter CPU_PER=10.4;
parameter HBLANK= 12; /// 52;
parameter TRIG_PERIOD = 6000 ;
parameter HBLANK= 52; // 12; /// 52; //*********************
parameter WOI_HEIGHT= 32;
parameter BLANK_ROWS_BEFORE= 1; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 1; //8;
......@@ -148,7 +149,6 @@ parameter EXTERNAL_TIMESTAMP = 1 ; // embed local timestamp, 1 - embed rec
// localparam FRAME_COMPRESS_CYCLES = (WOI_WIDTH &'h3fff0) * (WOI_HEIGHT &'h3fff0) * CYCLES_PER_PIXEL + FPGA_XTRA_CYCLES;
// in pixel clocks (camsync now has different clock - 100MHz instead of the 96MHz
// localparam TRIG_PERIOD = VIRTUAL_WIDTH * (VIRTUAL_HEIGHT + TRIG_LINES + VBLANK); /// maximal sensor can do
localparam TRIG_PERIOD = 5000 ;
// ========================== end of parameters from x353 ===================================
......@@ -165,6 +165,36 @@ parameter EXTERNAL_TIMESTAMP = 1 ; // embed local timestamp, 1 - embed rec
wire PX1_HACT; // output
wire PX1_VACT; // output
wire PX2_MCLK; // input sensor input clock
wire PX2_MRST; // input
wire PX2_ARO; // input
wire PX2_ARST; // input
wire PX2_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
wire [11:0] PX2_D; // output[11:0]
wire PX2_DCLK; // output sensor output clock (connect to sensor BPF output )
wire PX2_HACT; // output
wire PX2_VACT; // output
wire PX3_MCLK; // input sensor input clock
wire PX3_MRST; // input
wire PX3_ARO; // input
wire PX3_ARST; // input
wire PX3_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
wire [11:0] PX3_D; // output[11:0]
wire PX3_DCLK; // output sensor output clock (connect to sensor BPF output )
wire PX3_HACT; // output
wire PX3_VACT; // output
wire PX4_MCLK; // input sensor input clock
wire PX4_MRST; // input
wire PX4_ARO; // input
wire PX4_ARST; // input
wire PX4_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
wire [11:0] PX4_D; // output[11:0]
wire PX4_DCLK; // output sensor output clock (connect to sensor BPF output )
wire PX4_HACT; // output
wire PX4_VACT; // output
// Sensor signals - as on FPGA pads
wire [ 7:0] sns1_dp; // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
wire [ 7:0] sns1_dn; // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
......@@ -195,6 +225,16 @@ assign PX1_ARO = sns1_ctl; // from FPGA to sensor
wire sns2_ctl; // inout PX_ARO/TCK
wire sns2_pg; // inout SENSPGM
//connect sensor to sensor port 2 (all data rotated left by 1 bit)
assign sns2_dp[6:1] = {PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_D[1], PX2_HACT};
assign PX2_MRST = sns2_dp[7]; // from FPGA to sensor
assign PX2_MCLK = sns2_dp[0]; // from FPGA to sensor
assign sns2_dn[6:0] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_VACT, PX2_DCLK};
assign PX2_ARST = sns2_dn[7];
assign sns2_clkn = PX2_D[11]; // inout CNVSYNC/TDI
assign sns2_clkp = PX2_D[0]; // CNVCLK/TDO
assign PX2_ARO = sns2_ctl; // from FPGA to sensor
wire [ 7:0] sns3_dp; // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
wire [ 7:0] sns3_dn; // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
wire sns3_clkp; // inout CNVCLK/TDO
......@@ -203,6 +243,16 @@ assign PX1_ARO = sns1_ctl; // from FPGA to sensor
wire sns3_sda; // inout PX_SDA
wire sns3_ctl; // inout PX_ARO/TCK
wire sns3_pg; // inout SENSPGM
//connect sensor to sensor port 3 (all data rotated left by 2 bits
assign sns3_dp[6:1] = {PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_D[0], PX3_HACT};
assign PX3_MRST = sns3_dp[7]; // from FPGA to sensor
assign PX3_MCLK = sns3_dp[0]; // from FPGA to sensor
assign sns3_dn[6:0] = {PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_D[1], PX3_VACT, PX3_DCLK};
assign PX3_ARST = sns3_dn[7];
assign sns3_clkn = PX3_D[10]; // inout CNVSYNC/TDI
assign sns3_clkp = PX3_D[11]; // CNVCLK/TDO
assign PX3_ARO = sns3_ctl; // from FPGA to sensor
wire [ 7:0] sns4_dp; // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
wire [ 7:0] sns4_dn; // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
......@@ -213,6 +263,17 @@ assign PX1_ARO = sns1_ctl; // from FPGA to sensor
wire sns4_ctl; // inout PX_ARO/TCK
wire sns4_pg; // inout SENSPGM
//connect sensor to sensor port 4 (all data rotated left by 3 bits
assign sns4_dp[6:1] = {PX4_D[5], PX4_D[3], PX4_D[1], PX4_D[11], PX4_D[9], PX4_HACT};
assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor
assign PX4_MCLK = sns4_dp[0]; // from FPGA to sensor
assign sns4_dn[6:0] = {PX4_D[6], PX4_D[4], PX4_D[2], PX4_D[0], PX4_D[10], PX4_VACT, PX4_DCLK};
assign PX4_ARST = sns4_dn[7];
assign sns4_clkn = PX4_D[7]; // inout CNVSYNC/TDI
assign sns4_clkp = PX4_D[8]; // CNVCLK/TDO
assign PX4_ARO = sns4_ctl; // from FPGA to sensor
wire [ 9:0] gpio_pins; // inout[9:0] ([6]-synco0,[7]-syncio0,[8]-synco1,[9]-syncio1)
// Connect trigger outs to triggets in (#10 needed for Icarus)
assign #10 gpio_pins[7] = gpio_pins[6];
......@@ -805,10 +866,69 @@ assign #10 gpio_pins[9] = gpio_pins[8];
`endif
`ifdef TEST_SENSOR
TEST_TITLE = "TEST_SENSOR";
TEST_TITLE = "GPIO";
$display("===================== TEST_%s =========================",TEST_TITLE);
program_status_gpio (
3, // input [1:0] mode;
0); // input [5:0] seq_num;
TEST_TITLE = "RTC";
$display("===================== TEST_%s =========================",TEST_TITLE);
program_status_rtc( // also takes snapshot
3, // input [1:0] mode;
0); //input [5:0] seq_num;
set_rtc (
32'h12345678, // input [31:0] sec;
0, //input [19:0] usec;
16'h8000); // input [15:0] corr; maximal correction to the rtc
// camsync_setup (
// 4'hf ); // sensor_mask); //
TEST_TITLE = "TEST_SENSOR1";
$display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_channel (
0 ); // input [1:0] num_sensor;
0 ); // input [1:0] num_sensor;
TEST_TITLE = "TEST_SENSOR2";
$display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_channel (
1 ); // input [1:0] num_sensor;
TEST_TITLE = "TEST_SENSOR3";
$display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_channel (
2 ); // input [1:0] num_sensor;
TEST_TITLE = "TEST_SENSOR4";
$display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_channel (
3 ); // input [1:0] num_sensor;
afi_mux_setup (
4'hf, // input [3:0] chn_mask;
'h10000000 >> 5, // input [26:0] afi_cmprs0_sa; // input [26:0] sa; // start address in 32-byte chunks
'h10000 >> 5, // input [26:0] afi_cmprs0_len; // input [26:0] length; // channel buffer length in 32-byte chunks
'h10010000 >> 5, // input [26:0] afi_cmprs1_sa; // input [26:0] sa; // start address in 32-byte chunks
'h10000 >> 5, // input [26:0] afi_cmprs1_len; // input [26:0] length; // channel buffer length in 32-byte chunks
'h10020000 >> 5, // input [26:0] afi_cmprs2_sa; // input [26:0] sa; // start address in 32-byte chunks
'h10000 >> 5, // input [26:0] afi_cmprs2_len; // input [26:0] length; // channel buffer length in 32-byte chunks
'h10030000 >> 5, // input [26:0] afi_cmprs3_sa; // input [26:0] sa; // start address in 32-byte chunks
'h10000 >> 5); // input [26:0] afi_cmprs3_len; // input [26:0] length; // channel buffer length in 32-byte chunks
camsync_setup (
4'hf ); // sensor_mask); //
TEST_TITLE = "GAMMA_LOAD";
$display("===================== TEST_%s =========================",TEST_TITLE);
program_curves(
0, //num_sensor, // input [1:0] num_sensor;
0); // input [1:0] sub_channel;
// just temporarily - enable channel immediately
// enable_memcntrl_en_dis(4'hc + {2'b0,num_sensor}, 1);
`endif
......@@ -822,9 +942,9 @@ assign #10 gpio_pins[9] = gpio_pins[8];
TEST_TITLE = "ALL_DONE";
$display("===================== TEST_%s =========================",TEST_TITLE);
#20000;
TEST_TITLE = "WAITING 60usec more";
TEST_TITLE = "WAITING 80usec more";
$display("===================== TEST_%s =========================",TEST_TITLE);
#60000;
#80000;
$finish;
end
// protect from never end
......@@ -1685,6 +1805,119 @@ simul_axi_hp_wr #(
.VACT1 () // output
);
simul_sensor12bits #(
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
.nrows (PF_HEIGHT), // SENSOR12BITS_NROWS),
`else
.nrows (FULL_HEIGHT), // SENSOR12BITS_NROWS),
`endif
.nrowb (BLANK_ROWS_BEFORE), // SENSOR12BITS_NROWB),
.nrowa (BLANK_ROWS_AFTER), // SENSOR12BITS_NROWA),
// .nAV(24),
.nbpf (0), // SENSOR12BITS_NBPF),
.ngp1 (SENSOR12BITS_NGPL),
.nVLO (SENSOR12BITS_NVLO),
.tMD (SENSOR12BITS_TMD),
.tDDO (SENSOR12BITS_TDDO),
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_2_i (
.MCLK (PX2_MCLK), // input
.MRST (PX2_MRST), // input
.ARO (PX2_ARO), // input
.ARST (PX2_ARST), // input
.OE (1'b0), // input output enable active low
.SCL (sns2_scl), // input
.SDA (sns2_sda), // inout
.OFST (PX2_OFST), // input
.D (PX2_D), // output[11:0]
.DCLK (PX2_DCLK), // output
.BPF (), // output
.HACT (PX2_HACT), // output
.VACT (PX2_VACT), // output
.VACT1 () // output
);
simul_sensor12bits #(
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
.nrows (PF_HEIGHT), // SENSOR12BITS_NROWS),
`else
.nrows (FULL_HEIGHT), // SENSOR12BITS_NROWS),
`endif
.nrowb (BLANK_ROWS_BEFORE), // SENSOR12BITS_NROWB),
.nrowa (BLANK_ROWS_AFTER), // SENSOR12BITS_NROWA),
// .nAV(24),
.nbpf (0), // SENSOR12BITS_NBPF),
.ngp1 (SENSOR12BITS_NGPL),
.nVLO (SENSOR12BITS_NVLO),
.tMD (SENSOR12BITS_TMD),
.tDDO (SENSOR12BITS_TDDO),
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_3_i (
.MCLK (PX3_MCLK), // input
.MRST (PX3_MRST), // input
.ARO (PX3_ARO), // input
.ARST (PX3_ARST), // input
.OE (1'b0), // input output enable active low
.SCL (sns3_scl), // input
.SDA (sns3_sda), // inout
.OFST (PX3_OFST), // input
.D (PX3_D), // output[11:0]
.DCLK (PX3_DCLK), // output
.BPF (), // output
.HACT (PX3_HACT), // output
.VACT (PX3_VACT), // output
.VACT1 () // output
);
simul_sensor12bits #(
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
.nrows (PF_HEIGHT), // SENSOR12BITS_NROWS),
`else
.nrows (FULL_HEIGHT), // SENSOR12BITS_NROWS),
`endif
.nrowb (BLANK_ROWS_BEFORE), // SENSOR12BITS_NROWB),
.nrowa (BLANK_ROWS_AFTER), // SENSOR12BITS_NROWA),
// .nAV(24),
.nbpf (0), // SENSOR12BITS_NBPF),
.ngp1 (SENSOR12BITS_NGPL),
.nVLO (SENSOR12BITS_NVLO),
.tMD (SENSOR12BITS_TMD),
.tDDO (SENSOR12BITS_TDDO),
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_4_i (
.MCLK (PX4_MCLK), // input
.MRST (PX4_MRST), // input
.ARO (PX4_ARO), // input
.ARST (PX4_ARST), // input
.OE (1'b0), // input output enable active low
.SCL (sns4_scl), // input
.SDA (sns4_sda), // inout
.OFST (PX4_OFST), // input
.D (PX4_D), // output[11:0]
.DCLK (PX4_DCLK), // output
.BPF (), // output
.HACT (PX4_HACT), // output
.VACT (PX4_VACT), // output
.VACT1 () // output
);
// wire [ 3:0] SIMUL_ADD_ADDR;
always @ (posedge CLK) begin
......@@ -1804,7 +2037,8 @@ task write_block_scanline_chn; // SuppressThisWarning VEditor : may be unused
end
endtask
function [10:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not used
function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not used
input disable_need;
input repetitive;
input single;
input reset_frame;
......@@ -1816,7 +2050,7 @@ function [10:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
reg [10:0] rslt;
reg [11:0] rslt;
begin
rslt = 0;
rslt[MCONTR_LINTILE_EN] = ~chn_reset;
......@@ -1828,11 +2062,13 @@ function [10:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us
rslt[MCONTR_LINTILE_RST_FRAME] = reset_frame;
rslt[MCONTR_LINTILE_SINGLE] = single;
rslt[MCONTR_LINTILE_REPEAT] = repetitive;
rslt[MCONTR_LINTILE_DIS_NEED] = disable_need;
// func_encode_mode_tiled={byte32,keep_open,extra_pages,write_mem,enable,~chn_reset};
func_encode_mode_tiled = rslt;
end
endfunction
function [10:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not used
function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not used
input disable_need;
input repetitive;
input single;
input reset_frame;
......@@ -1842,7 +2078,7 @@ function [10:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
reg [10:0] rslt;
reg [11:0] rslt;
begin
rslt = 0;
rslt[MCONTR_LINTILE_EN] = ~chn_reset;
......@@ -1852,6 +2088,7 @@ function [10:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not
rslt[MCONTR_LINTILE_RST_FRAME] = reset_frame;
rslt[MCONTR_LINTILE_SINGLE] = single;
rslt[MCONTR_LINTILE_REPEAT] = repetitive;
rslt[MCONTR_LINTILE_DIS_NEED] = disable_need;
// func_encode_mode_scanline={extra_pages,write_mem,enable,~chn_reset};
func_encode_mode_scanline = rslt;
end
......@@ -1862,21 +2099,23 @@ endfunction
task setup_sensor_channel;
input [1:0] num_sensor;
reg trigger_mode; // 0 - auto, 1 - triggered
reg ext_trigger_mode; // 0 - internal, 1 - external trigger (camsync)
reg external_timestamp; // embed local timestamp, 1 - embed received timestamp
reg [31:0] camsync_period;
// reg trigger_mode; // 0 - auto, 1 - triggered
// reg ext_trigger_mode; // 0 - internal, 1 - external trigger (camsync)
// reg external_timestamp; // embed local timestamp, 1 - embed received timestamp
// reg [31:0] camsync_period;
reg [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
reg [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
reg [31:0] window_height; // 16 bit
reg [31:0] window_left;
reg [31:0] window_top;
reg [31:0] frame_start_address;
reg [31:0] frame_start_address_inc;
reg [31:0] last_buf_frame;
reg [31:0] camsync_delay;
reg [ 3:0] sensor_mask;
// reg [31:0] camsync_delay;
// reg [ 3:0] sensor_mask;
reg [26:0] afi_cmprs0_sa;
reg [26:0] afi_cmprs0_len;
// reg [26:0] afi_cmprs0_sa;
// reg [26:0] afi_cmprs0_len;
// Setting up a single sensor channel 0, sunchannel 0
//
......@@ -1886,40 +2125,32 @@ task setup_sensor_channel;
window_top = 0;
window_width = SENSOR_MEMORY_WIDTH_BURSTS;
frame_full_width = SENSOR_MEMORY_FULL_WIDTH_BURSTS;
camsync_period = TRIG_PERIOD;
camsync_delay = CAMSYNC_DELAY;
trigger_mode = TRIGGER_MODE;
ext_trigger_mode = EXT_TRIGGER_MODE;
external_timestamp = EXTERNAL_TIMESTAMP;
// camsync_period = TRIG_PERIOD;
// camsync_delay = CAMSYNC_DELAY;
// trigger_mode = TRIGGER_MODE;
// ext_trigger_mode = EXT_TRIGGER_MODE;
// external_timestamp = EXTERNAL_TIMESTAMP;
frame_start_address = FRAME_START_ADDRESS + num_sensor * FRAME_START_ADDRESS_INC * (LAST_BUF_FRAME + 1);
frame_start_address_inc = FRAME_START_ADDRESS_INC;
last_buf_frame = LAST_BUF_FRAME;
sensor_mask = 1 << num_sensor;
// sensor_mask = 1 << num_sensor;
afi_cmprs0_sa = 'h10000000 >> 5;
afi_cmprs0_len = 'h10000 >> 5;
// program_curves(
// num_sensor, // input [1:0] num_sensor;
// 0); // input [1:0] sub_channel;
program_status_gpio (
3, // input [1:0] mode;
0); // input [5:0] seq_num;
// afi_cmprs0_sa = 'h10000000 >> 5;
// afi_cmprs0_len = 'h10000 >> 5;
program_status_sensor_i2c(
num_sensor, // input [1:0] num_sensor;
3, // input [1:0] mode;
0); //input [5:0] seq_num;
0); // input [5:0] seq_num;
program_status_sensor_io(
num_sensor, // input [1:0] num_sensor;
3, // input [1:0] mode;
0); //input [5:0] seq_num;
program_status_rtc( // also takes snapshot
3, // input [1:0] mode;
0); //input [5:0] seq_num;
set_rtc (
32'h12345678, // input [31:0] sec;
0, //input [19:0] usec;
16'h8000); // input [15:0] corr; maximal correction to the rtc
0); // input [5:0] seq_num;
program_status_compressor(
num_sensor, // input [1:0] num_sensor;
3, // input [1:0] mode;
0); // input [5:0] seq_num;
// moved before camsync to have a valid timestamo w/o special waiting
TEST_TITLE = "MEMORY_SENSOR";
......@@ -1927,12 +2158,12 @@ task setup_sensor_channel;
setup_sensor_memory (
num_sensor, // input [1:0] num_sensor;
FRAME_START_ADDRESS, // input [31:0] frame_sa; // 22-bit frame start address ((3 CA LSBs==0. BA==0)
FRAME_START_ADDRESS_INC, // input [31:0] frame_sa_inc; // 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
frame_start_address, // input [31:0] frame_sa; // 22-bit frame start address ((3 CA LSBs==0. BA==0)
frame_start_address_inc, // input [31:0] frame_sa_inc; // 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
last_buf_frame, // input [31:0] last_frame_num; // 16-bit number of the last frame in a buffer
frame_full_width, // input [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width, // input [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
window_height, // input [31:0] window_height; // 16 bit
window_width, // input [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
window_height, // input [31:0] window_height; // 16 bit
window_left, // input [31:0] window_left;
window_top); // input [31:0] window_top;
......@@ -1982,10 +2213,11 @@ task setup_sensor_channel;
window_top+1, // input [31:0] window_top; (to match 20x20 tiles in 353)
1, // input byte32; // == 1?
2, //input [31:0] tile_width; // == 2
1); // input [31:0] extra_pages; // 1
1, // input [31:0] extra_pages; // 1
1); // disable "need" (yield to sensor channels)
compressor_run (num_sensor, 3); // run repetitive mode
/*
TEST_TITLE = "CAMSYNC_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
......@@ -2018,6 +2250,7 @@ task setup_sensor_channel;
set_camsync_period (camsync_period); // set period (start generating) - in 353 was after everything else was set
*/
TEST_TITLE = "DELAYS_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
......@@ -2076,6 +2309,7 @@ task setup_sensor_channel;
0); // input [15:0] height2_m1; // height of the third sub-frame minus 1 (no need for 4-th)
set_sensor_lens_flat_parameters(
num_sensor,
0, // num_sub_sensor
// add mode "DIRECT", "ASAP", "RELATIVE", "ABSOLUTE" and frame number
19'h20000, // 0, // input [18:0] AX;
19'h20000, // 0, // input [18:0] AY;
......@@ -2163,7 +2397,7 @@ task write_cmd_frame_sequencer;
$display("===================== TEST_%s =========================",TEST_TITLE);
// just temporarily - enable channel immediately
enable_memcntrl_en_dis(4'hc + {2'b0,num_sensor}, 1);
/*
TEST_TITLE = "PROGRAM AFI_MUX";
$display("===================== TEST_%s =========================",TEST_TITLE);
......@@ -2189,13 +2423,12 @@ task write_cmd_frame_sequencer;
afi_mux_mode_chn (
0, //input [0:0] port_afi; // number of AFI port.3
num_sensor, // input [1:0] chn; // channel number to set mode for
/*
mode == 0 - show EOF pointer, internal
mode == 1 - show EOF pointer, confirmed
mode == 2 - show current pointer, internal
mode == 3 - show current pointer, confirmed
each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), bit[3] - not used
*/
//mode == 0 - show EOF pointer, internal
//mode == 1 - show EOF pointer, confirmed
//mode == 2 - show current pointer, internal
//mode == 3 - show current pointer, confirmed
//each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), bit[3] - not used
0); // input [1:0] mode;
afi_mux_chn_start_length (
......@@ -2214,7 +2447,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
afi_mux_enable (
0, // input [0:0] port_afi; // number of AFI port
1); // input en;
*/
TEST_TITLE = "GAMMA_CTL";
......@@ -2227,14 +2460,146 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
1'b1, // input repet_mode; // Normal mode, single trigger - just for debugging
1'b0); // input trig; // pass next frame
// temporarily putting in the very end as it takes about 30 usec to program curves (TODO: see how to make it faster for simulation)
TEST_TITLE = "GAMMA_LOAD";
$display("===================== TEST_%s =========================",TEST_TITLE);
program_curves(
num_sensor, // input [1:0] num_sensor;
0); // input [1:0] sub_channel;
// just temporarily - enable channel immediately
// enable_memcntrl_en_dis(4'hc + {2'b0,num_sensor}, 1);
end
endtask
task camsync_setup;
input [3:0] sensor_mask;
reg trigger_mode; // 0 - auto, 1 - triggered
reg ext_trigger_mode; // 0 - internal, 1 - external trigger (camsync)
reg external_timestamp; // embed local timestamp, 1 - embed received timestamp
reg [31:0] camsync_period;
reg [31:0] camsync_delay;
// reg [ 3:0] sensor_mask;
integer i;
begin
TEST_TITLE = "CAMSYNC_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
camsync_period = TRIG_PERIOD;
camsync_delay = CAMSYNC_DELAY;
trigger_mode = TRIGGER_MODE;
ext_trigger_mode = EXT_TRIGGER_MODE;
external_timestamp = EXTERNAL_TIMESTAMP;
// sensor_mask = 4'hf; // All sensors // 1 << num_sensor;
// setup camsync module
set_camsync_period (0); // reset circuitry
set_gpio_ports (
0, // input [1:0] port_soft; // <2 - unchanged, 2 - disable, 3 - enable
3, // input [1:0] port_a; // camsync
0, // input [1:0] port_b; // motors on 353
0); //input [1:0] port_c; // logger
set_camsync_mode (
1'b1, // input en; // 1 - enable module, 0 - reset
{1'b1,1'b1}, // input [1:0] en_snd; // <2 - NOP, 2 - disable, 3 - enable sending timestamp with sync pulse
{1'b1,external_timestamp}, // input [1:0] en_ts_external; // <2 - NOP, 2 - local timestamp in the frame header, 3 - use external timestamp
{1'b1,trigger_mode}, // input [1:0] triggered_mode; // <2 - NOP, 2 - async sensor mode, 3 - triggered sensor mode
{1'b1, 2'h0}, // input [2:0] master_chn; // <4 - NOP, 4..7 - set master channel
{1'b1, sensor_mask}); // input [4:0] chn_en; // <16 - NOP, [3:0] - bit mask of enabled sensor channels
// setting I/Os after camsync is enabled
reset_camsync_inout (0); // reset input selection
if (ext_trigger_mode)
set_camsync_inout (0, 7, 1 ); // set input selection - ext[7], active high
reset_camsync_inout (1); // reset output selection
set_camsync_inout (1, 6, 1 ); // reset output selection - ext[6], active high
set_camsync_period (SYNC_BIT_LENGTH); ///set (bit_length -1) (should be 2..255)
for (i = 0; i < 4; i = i + 1) begin
set_camsync_delay (
i, // 0, // input [1:0] sub_chn;
camsync_delay + 10 * i); // input [31:0] dly; // 0 - input selection, 1 - output selection
end
set_camsync_period (camsync_period); // set period (start generating) - in 353 was after everything else was set
end
endtask
task afi_mux_setup;
input [3:0] chn_mask;
input [26:0] afi_cmprs0_sa; // input [26:0] sa; // start address in 32-byte chunks
input [26:0] afi_cmprs0_len; // input [26:0] length; // channel buffer length in 32-byte chunks
input [26:0] afi_cmprs1_sa; // input [26:0] sa; // start address in 32-byte chunks
input [26:0] afi_cmprs1_len; // input [26:0] length; // channel buffer length in 32-byte chunks
input [26:0] afi_cmprs2_sa; // input [26:0] sa; // start address in 32-byte chunks
input [26:0] afi_cmprs2_len; // input [26:0] length; // channel buffer length in 32-byte chunks
input [26:0] afi_cmprs3_sa; // input [26:0] sa; // start address in 32-byte chunks
input [26:0] afi_cmprs3_len; // input [26:0] length; // channel buffer length in 32-byte chunks
integer i;
begin
TEST_TITLE = "PROGRAM AFI_MUX";
$display("===================== TEST_%s =========================",TEST_TITLE);
for (i = 0; i < 4; i = i+1) if (chn_mask & (1 << i)) begin
afi_mux_program_status (
0, // input [0:0] port_afi; // number of AFI port (0 - afi 1, 1 - afi2) // configuration controlled by the code. currently
// both AFI are used: ch0 - cmprs_afi_mux_1.0, ch1 - cmprs_afi_mux_1.1,
// ch2 - cmprs_afi_mux_2.0, ch3 - cmprs_afi_mux_2
// May be chenged to ch0 - cmprs_afi_mux_1.0, ch1 -cmprs_afi_mux_1.1,
// ch2 - cmprs_afi_mux_1.2, ch3 - cmprs_afi_mux_1.3
i, // num_sensor, // input [1:0] chn_afi;
3, // input [1:0] mode;
0); // input [5:0] seq_num;
end
// reset all channels
afi_mux_reset(
0, // input [0:0] port_afi;
4'hf); // input [3:0] rst_chn;
// release resets
afi_mux_reset(
0, // input [0:0] port_afi;
0); // input [3:0] rst_chn;
// set report mode (pointer type) - per status
for (i = 0; i < 4; i = i+1) if (chn_mask & (1 << i)) begin
afi_mux_mode_chn (
0, //input [0:0] port_afi; // number of AFI port.3
i, // num_sensor, // input [1:0] chn; // channel number to set mode for
/*
mode == 0 - show EOF pointer, internal
mode == 1 - show EOF pointer, confirmed
mode == 2 - show current pointer, internal
mode == 3 - show current pointer, confirmed
each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), bit[3] - not used
*/
0); // input [1:0] mode;
end
afi_mux_chn_start_length (
0, // input [0:0] port_afi; // number of AFI port
0, // num_sensor,// input [ 1:0] chn; // channel number to set mode for
afi_cmprs0_sa, // input [26:0] sa; // start address in 32-byte chunks
afi_cmprs0_len); // input [26:0] length; // channel buffer length in 32-byte chunks
afi_mux_chn_start_length (
0, // input [0:0] port_afi; // number of AFI port
1, // num_sensor,// input [ 1:0] chn; // channel number to set mode for
afi_cmprs1_sa, // input [26:0] sa; // start address in 32-byte chunks
afi_cmprs1_len); // input [26:0] length; // channel buffer length in 32-byte chunks
// another option - 2 other channels with port_afi == 1, chn == [0,1]
afi_mux_chn_start_length (
0, // input [0:0] port_afi; // number of AFI port
2, // input [ 1:0] chn; // channel number to set mode for
afi_cmprs2_sa, // input [26:0] sa; // start address in 32-byte chunks
afi_cmprs2_len); // input [26:0] length; // channel buffer length in 32-byte chunks
afi_mux_chn_start_length (
0, // input [0:0] port_afi; // number of AFI port
3, // input [ 1:0] chn; // channel number to set mode for
afi_cmprs3_sa, // input [26:0] sa; // start address in 32-byte chunks
afi_cmprs3_len); // input [26:0] length; // channel buffer length in 32-byte chunks
for (i = 0; i < 4; i = i+1) if (chn_mask & (1 << i)) begin
// enable channel i
afi_mux_enable_chn (
0, // input [0:0] port_afi; // number of AFI port
i, // num_sensor, // input [1:0] en_chn; // channel number to enable/disable;
1); // input en;
end
// enable the whole afi_mux module
afi_mux_enable (
0, // input [0:0] port_afi; // number of AFI port
1); // input en;
end
endtask
......@@ -2331,6 +2696,7 @@ task setup_sensor_memory;
begin
base_addr = MCONTR_SENS_BASE + MCONTR_SENS_INC * num_sensor;
mode= func_encode_mode_scanline(
0, // disable_need
1, // repetitive,
0, // single,
0, // reset_frame,
......@@ -2362,6 +2728,7 @@ task setup_compressor_memory;
input byte32; // == 1?
input [31:0] tile_width; // == 2
input [31:0] extra_pages; // 1
input disable_need; // set to 1
reg [29:0] base_addr;
integer mode;
......@@ -2374,6 +2741,7 @@ task setup_compressor_memory;
base_addr = MCONTR_CMPRS_BASE + MCONTR_CMPRS_INC * num_sensor;
mode= func_encode_mode_tiled(
disable_need,
1, // repetitive,
0, // single,
0, // reset_frame,
......@@ -2687,6 +3055,7 @@ endtask
task set_sensor_lens_flat_parameters;
input [1:0] num_sensor;
input [1:0] num_sub_sensor;
// add mode "DIRECT", "ASAP", "RELATIVE", "ABSOLUTE" and frame number
input [18:0] AX;
input [18:0] AY;
......@@ -2704,40 +3073,40 @@ task set_sensor_lens_flat_parameters;
reg [31:0] data;
begin
reg_addr = (SENSOR_GROUP_ADDR + num_sensor * SENSOR_BASE_INC) + SENS_LENS_RADDR + SENS_LENS_COEFF;
data = func_lens_data(num_sensor, SENS_LENS_AX);
data = func_lens_data(num_sub_sensor, SENS_LENS_AX);
data[18:0] = AX;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_AY);
data = func_lens_data(num_sub_sensor, SENS_LENS_AY);
data[18:0] = AY;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_C);
data = func_lens_data(num_sub_sensor, SENS_LENS_C);
data[18:0] = C;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_BX);
data = func_lens_data(num_sub_sensor, SENS_LENS_BX);
data[20:0] = BX;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_BY);
data = func_lens_data(num_sub_sensor, SENS_LENS_BY);
data[20:0] = BY;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_SCALES + 0);
data = func_lens_data(num_sub_sensor, SENS_LENS_SCALES + 0);
data[16:0] = scales0;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_SCALES + 2);
data = func_lens_data(num_sub_sensor, SENS_LENS_SCALES + 2);
data[16:0] = scales1;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_SCALES + 4);
data = func_lens_data(num_sub_sensor, SENS_LENS_SCALES + 4);
data[16:0] = scales2;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_SCALES + 6);
data = func_lens_data(num_sub_sensor, SENS_LENS_SCALES + 6);
data[16:0] = scales3;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_FAT0_IN);
data = func_lens_data(num_sub_sensor, SENS_LENS_FAT0_IN);
data[15:0] = fatzero_in;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_FAT0_OUT);
data = func_lens_data(num_sub_sensor, SENS_LENS_FAT0_OUT);
data[15:0] = fatzero_out;
write_contol_register(reg_addr, data);
data = func_lens_data(num_sensor, SENS_LENS_POST_SCALE);
data = func_lens_data(num_sub_sensor, SENS_LENS_POST_SCALE);
data[3:0] = post_scale;
write_contol_register(reg_addr, data);
end
......@@ -3390,8 +3759,8 @@ task afi_mux_mode_chn;
// ch2 - cmprs_afi_mux_2.0, ch3 - cmprs_afi_mux_2
// May be chenged to ch0 - cmprs_afi_mux_1.0, ch1 -cmprs_afi_mux_1.1,
// ch2 - cmprs_afi_mux_1.2, ch3 - cmprs_afi_mux_1.3
input [1:0] mode;
input [1:0] chn; // channel number to set mode for
input [1:0] mode;
reg [29:0] reg_addr;
/*
mode == 0 - show EOF pointer, internal
......
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