simulating multiple simultanerous sesnor/compressor channels (225fccd0) · Commits · Elphel / x393

axi/cmprs_afi_mux.v

+16 −10

Original line number	Diff line number	Diff line
		@@ -117,7 +117,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
		output [ 1:0] afi_awlock,
		output [ 3:0] afi_awcache,
		output [ 2:0] afi_awprot,
		output [ 3:0] afi_awlen,
		output reg [ 3:0] afi_awlen,
		output [ 1:0] afi_awsize,
		output [ 1:0] afi_awburst,
		output [ 3:0] afi_awqos,
		@@ -220,6 +220,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
		wire [ 3:0] chunk_ptr_ra;
		wire [ 7:0] items_left = counts_corr2[8] ? left_to_eof[(winner2 * 8) +: 8] : counts_corr2[7:0];

		reg [5:0] afi_awid_r;



		@@ -246,9 +247,9 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
		assign {fifo_ren3, fifo_ren2, fifo_ren1, fifo_ren0} = fifo_ren;

		assign afi_awaddr = {chunk_addr,5'b0};
		assign afi_awid = {1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
		assign afi_awid = afi_awid_r; // {1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
		assign afi_awvalid = awvalid[1];
		assign afi_awlen = {wleft[3:2],2'b11};
		// assign afi_awlen = {wleft[3:2],2'b11};
		assign afi_wdata = wdata;
		// assign afi_bready = 1'b1; // always ready

		@@ -427,27 +428,32 @@ items_left
		3'h4 :
		({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);

		if (awvalid[0]) afi_awid_r <={1'b0,wleft[3:2],last_burst_in_frame,cur_chn};

		if (awvalid[0]) afi_awlen <= {wleft[3:2],2'b11};


		end

		// delay write channel controls signal to match data latency. wid bits will be optimized (6 -> 3)
		dly_16 #(
		.WIDTH(8)
		.WIDTH(2) // 8)
		) afi_wx_i (
		.clk (hclk), // input
		.rst (!en), // input
		.dly (AFI_MUX_BUF_LATENCY), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
		.din ({ wvalid, wlast, afi_awid}), // input[0:0]
		.dout ({afi_wvalid, afi_wlast, afi_wid}) // output[0:0]
		.din ({ wvalid, wlast}), // , afi_awid_r}), // afi_awid}), // input[0:0]
		.dout ({afi_wvalid, afi_wlast}) //, afi_wid}) // output[0:0]
		);
		localparam [3:0] AFI_MUX_BUF_LATENCYM1 = AFI_MUX_BUF_LATENCY - 1;
		dly_16 #(
		.WIDTH(3)
		.WIDTH(9) // 3)
		) afi_wdata_i (
		.clk (hclk), // input
		.rst (!en), // input
		.dly (AFI_MUX_BUF_LATENCYM1), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
		.din ({wvalid, cur_chn}), // input[0:0]
		.dout ({wdata_en,wdata_sel}) // output[0:0]
		.din ({wvalid, cur_chn, afi_awid_r}), //}), // input[0:0]
		.dout ({wdata_en, wdata_sel, afi_wid}) // }) // output[0:0]
		);

		cmd_deser #(
		@@ -467,7 +473,7 @@ items_left
		.we (cmd_we) // output
		);

		wire [53:0] chunk_ptr_rd01; // [0:1];
		wire [53:0] chunk_ptr_rd01; // [0:1]; // combines 2 pointers - write one and write responce one

		cmprs_afi_mux_ptr cmprs_afi_mux_ptr_i (
		.hclk (hclk), // input

includes/tasks_tests_memory.vh

+15 −4

Original line number	Diff line number	Diff line
		@@ -133,8 +133,9 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
		reg repetitive;
		reg single;
		reg reset_frame;

		reg disable_need;
		begin
		disable_need = 1'b0;
		repetitive = 1'b1;
		single = 1'b0;
		reset_frame = 1'b0;
		@@ -145,6 +146,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
		(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
		start64, lo_addr64, size64, $time);
		mode= func_encode_mode_scanline(
		disable_need,
		repetitive,
		single,
		reset_frame,
		@@ -213,8 +215,9 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
		reg repetitive;
		reg single;
		reg reset_frame;

		reg disable_need;
		begin
		disable_need = 1'b0;
		repetitive = 1'b1;
		single = 1'b0;
		reset_frame = 1'b0;
		@@ -243,6 +246,7 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
		end
		endcase
		mode= func_encode_mode_scanline(
		disable_need,
		repetitive,
		single,
		reset_frame,
		@@ -351,8 +355,10 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
		reg repetitive;
		reg single;
		reg reset_frame;
		reg disable_need;

		begin
		disable_need = 1'b0;
		repetitive = 1'b1;
		single = 1'b0;
		reset_frame = 1'b0;
		@@ -381,6 +387,7 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
		end
		endcase
		mode= func_encode_mode_scanline(
		disable_need,
		repetitive,
		single,
		reset_frame,
		@@ -460,8 +467,9 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
		reg repetitive;
		reg single;
		reg reset_frame;

		reg disable_need;
		begin
		disable_need = 1'b0;
		repetitive = 1'b1;
		single = 1'b0;
		reset_frame = 1'b0;
		@@ -493,6 +501,7 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
		end
		endcase
		mode= func_encode_mode_tiled(
		disable_need,
		repetitive,
		single,
		reset_frame,
		@@ -590,8 +599,9 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
		reg repetitive;
		reg single;
		reg reset_frame;

		reg disable_need;
		begin
		disable_need = 1'b0;
		repetitive = 1'b1;
		single = 1'b0;
		reset_frame = 1'b0;
		@@ -623,6 +633,7 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
		end
		endcase
		mode= func_encode_mode_tiled(
		disable_need,
		repetitive,
		single,
		reset_frame,

includes/x393_parameters.vh

+7 −5

Original line number	Diff line number	Diff line
		@@ -50,7 +50,7 @@

		//command interface parameters
		parameter DLY_LD = 'h080, // address to generate delay load
		parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
		parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
		//0x1000..103f - 0- bit data (set/reset)
		parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
		parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
		@@ -200,7 +200,7 @@
		// parameter CMD0_ADDR = 'h0800, // AXI write to command sequence memory
		// parameter CMD0_ADDR_MASK = 'h1800, // AXI read address mask for the command sequence memory
		parameter MCNTRL_PS_ADDR= 'h100,
		parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
		parameter MCNTRL_PS_MASK= 'h7e0, // both channels 0 and 1
		parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
		parameter MCNTRL_PS_EN_RST= 'h0,
		parameter MCNTRL_PS_CMD= 'h1,
		@@ -272,6 +272,8 @@
		parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
		parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
		parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
		parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request

		// Channel test module parameters
		parameter MCNTRL_TEST01_ADDR= 'h0f0,
		parameter MCNTRL_TEST01_MASK= 'h7f0,
		@@ -522,7 +524,7 @@
		parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
		parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns

		parameter CMPRS_NUM_AFI_CHN = 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
		parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
		parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
		parameter CMPRS_BASE_INC = 'h10,
		parameter CMPRS_AFIMUX_RADDR0= 'h40, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
		@@ -658,7 +660,7 @@
		// Command sequencers parameters
		parameter CMDFRAMESEQ_ADDR_BASE= 'h780,
		parameter CMDFRAMESEQ_ADDR_INC= 'h20,
		parameter CMDFRAMESEQ_MASK= 'h3e0,
		parameter CMDFRAMESEQ_MASK= 'h7e0,
		parameter CMDFRAMESEQ_DEPTH = 64, // 32/64/128
		parameter CMDFRAMESEQ_ABS = 0,
		parameter CMDFRAMESEQ_REL = 16,

includes/x393_tasks_status.vh

+1 −0

Original line number	Diff line number	Diff line
		@@ -113,6 +113,7 @@ endtask

		task read_all_status;
		begin
		$display (" read_all_status @%t",$time);
		read_status (MCONTR_PHY_STATUS_REG_ADDR);
		read_status (MCONTR_TOP_STATUS_REG_ADDR);
		read_status (MCNTRL_PS_STATUS_REG_ADDR);

memctrl/mcntrl393.v

+17 −9

Original line number	Diff line number	Diff line
		@@ -50,7 +50,7 @@ module mcntrl393 #(

		//command interface parameters
		parameter DLY_LD = 'h080, // address to generate delay load
		parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
		parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
		//0x1000..103f - 0- bit data (set/reset)
		parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
		parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
		@@ -166,7 +166,7 @@ module mcntrl393 #(
		parameter CMD_DONE_BIT= 10,
		//
		parameter MCNTRL_PS_ADDR= 'h100,
		parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
		parameter MCNTRL_PS_MASK= 'h7e0, // both channels 0 and 1
		parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
		parameter MCNTRL_PS_EN_RST= 'h0,
		parameter MCNTRL_PS_CMD= 'h1,
		@@ -240,7 +240,8 @@ module mcntrl393 #(
		parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
		parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
		parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
		parameter MCONTR_LINTILE_REPEAT = 10 // read/write pages until disabled
		parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
		parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request

		) (
		input rst_in,
		@@ -1057,7 +1058,8 @@ module mcntrl393 #(
		.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
		.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
		.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
		) mcntrl_linear_wr_sensor_i (
		.mrst (mrst), // input
		.mclk (mclk), // input
		@@ -1121,7 +1123,8 @@ module mcntrl393 #(
		.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
		.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
		.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
		) mcntrl_tiled_rd_compressor_i (
		.mrst (mrst), // input
		.mclk (mclk), // input
		@@ -1192,7 +1195,8 @@ module mcntrl393 #(
		.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
		.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
		.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
		) mcntrl_linear_rw_chn1_i (
		.mrst (mrst), // input
		.mclk (mclk), // input
		@@ -1252,7 +1256,8 @@ module mcntrl393 #(
		.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
		.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
		.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
		) mcntrl_linear_rw_chn3_i (
		.mrst (mrst), // input
		.mclk (mclk), // input
		@@ -1315,7 +1320,8 @@ module mcntrl393 #(
		.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
		.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
		.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
		) mcntrl_tiled_rw_chn2_i (
		.mrst (mrst), // input
		.mclk (mclk), // input
		@@ -1382,7 +1388,9 @@ module mcntrl393 #(
		.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
		.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
		.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)

		) mcntrl_tiled_rw_chn4_i (
		.mrst (mrst), // input
		.mclk (mclk), // input

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