Commit 210ed954 authored by Andrey Filippov's avatar Andrey Filippov

removed most async resets

parent b721ae66
...@@ -404,10 +404,11 @@ module membridge#( ...@@ -404,10 +404,11 @@ module membridge#(
if (!rw_in_progress) buf_in_line64 <= 0; if (!rw_in_progress) buf_in_line64 <= 0;
else if (buf_rdwr) buf_in_line64 <= is_last_in_line? {(FRAME_WIDTH_BITS+1){1'b0}} : (buf_in_line64 +1); else if (buf_rdwr) buf_in_line64 <= is_last_in_line? {(FRAME_WIDTH_BITS+1){1'b0}} : (buf_in_line64 +1);
next_page_rd <= next_page_rd_w; if (hrst) next_page_rd <= 0;
next_page_wr <= next_page_wr_w; else next_page_rd <= next_page_rd_w;
if (hrst) next_page_wr <= 0;
else next_page_wr <= next_page_wr_w;
end end
......
...@@ -21,7 +21,7 @@ ...@@ -21,7 +21,7 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module cmd_encod_4mux( module cmd_encod_4mux(
input rst, input mrst,
input clk, input clk,
input start0, // this channel was started input start0, // this channel was started
...@@ -51,11 +51,11 @@ module cmd_encod_4mux( ...@@ -51,11 +51,11 @@ module cmd_encod_4mux(
); );
reg [3:0] select; reg [3:0] select;
wire start_w= start0 | start1 |start2 | start3; wire start_w= start0 | start1 |start2 | start3;
always @ (posedge rst or posedge clk) begin always @ (posedge clk) begin
if (rst) start <= 0; if (mrst) start <= 0;
else start <= start_w; else start <= start_w;
if (rst) select <= 0; if (mrst) select <= 0;
else if (start_w) select <={ // normally should be no simultaneous starts, so priority is not needed else if (start_w) select <={ // normally should be no simultaneous starts, so priority is not needed
start3 & ~start2 & ~start1 & ~start0, start3 & ~start2 & ~start1 & ~start0,
start2 & ~start1 & ~start0, start2 & ~start1 & ~start0,
......
...@@ -50,7 +50,7 @@ module cmd_encod_tiled_32_rd #( ...@@ -50,7 +50,7 @@ module cmd_encod_tiled_32_rd #(
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter RSEL= 1'b1 // Late/early READ commands parameter RSEL= 1'b1 // Late/early READ commands
) ( ) (
input rst, input mrst,
input clk, input clk,
// programming interface // programming interface
input [2:0] start_bank, // bank address input [2:0] start_bank, // bank address
...@@ -157,56 +157,57 @@ module cmd_encod_tiled_32_rd #( ...@@ -157,56 +157,57 @@ module cmd_encod_tiled_32_rd #(
assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
always @ (posedge rst or posedge clk) begin always @ (posedge clk) begin
if (rst) gen_run <= 0; if (mrst) gen_run <= 0;
else if (start_d) gen_run<= 1; // delaying else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0; else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0; // if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run; // else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0; if (mrst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
if (rst) num_cols128_m2 <= 0;
if (mrst) num_cols128_m2 <= 0;
else if (start) num_cols128_m2 <= num_cols_in_m1 & ~1; // number of r32-byte columns else if (start) num_cols128_m2 <= num_cols_in_m1 & ~1; // number of r32-byte columns
if (rst) start_d <=0; if (mrst) start_d <=0;
else start_d <= start; else start_d <= start;
if (rst) top_rc <= 0; if (mrst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+2; else if (start_d) top_rc <= {row,col}+2;
else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA
if (rst) row_col_bank <= 0; if (mrst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d? else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w; else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (rst) scan_row <= 0; if (mrst) scan_row <= 0;
else if (start_d) scan_row <= 0; else if (start_d) scan_row <= 0;
else if (pre_act) scan_row <= last_row?0:scan_row+1; else if (pre_act) scan_row <= last_row?0:scan_row+1;
if (rst) scan_col <= 0; if (mrst) scan_col <= 0;
else if (start_d) scan_col <= 0; else if (start_d) scan_col <= 0;
else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ
if (rst) first_col <= 0; if (mrst) first_col <= 0;
else if (start_d) first_col <= 1; else if (start_d) first_col <= 1;
else if (pre_act && last_row) first_col <= 0; else if (pre_act && last_row) first_col <= 0;
if (rst) last_col <= 0; if (mrst) last_col <= 0;
else if (start_d) last_col <= num_cols128_m2==0; // if single column - will start with 1'b1; else if (start_d) last_col <= num_cols128_m2==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m2); // too early for READ ? else if (pre_act) last_col <= (scan_col==num_cols128_m2); // too early for READ ?
if (rst) enable_autopre <= 0; if (mrst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0; else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
if (rst) loop_continue<=0; if (mrst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m2) && last_row; else loop_continue <= (scan_col==num_cols128_m2) && last_row;
if (rst) gen_addr <= 0; if (mrst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0; else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop else gen_addr <= gen_addr+1; // not in a loop
...@@ -222,8 +223,8 @@ module cmd_encod_tiled_32_rd #( ...@@ -222,8 +223,8 @@ module cmd_encod_tiled_32_rd #(
end end
// ROM-based (registered output) encoded sequence // ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin always @ (posedge clk) begin
if (rst) rom_r <= 0; if (mrst) rom_r <= 0;
else case (gen_addr) else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE 4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT); 4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
...@@ -246,17 +247,15 @@ module cmd_encod_tiled_32_rd #( ...@@ -246,17 +247,15 @@ module cmd_encod_tiled_32_rd #(
default:rom_r <= 0; default:rom_r <= 0;
endcase endcase
end end
always @ (posedge rst or posedge clk) begin always @ (posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0; if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d; else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0; if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d; else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0; if (mrst) enc_cmd <= 0;
// else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause // else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
else if (gen_run) begin else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
...@@ -268,7 +267,7 @@ module cmd_encod_tiled_32_rd #( ...@@ -268,7 +267,7 @@ module cmd_encod_tiled_32_rd #(
3'b0}, // [14:0] addr; // 15-bit row/column address 3'b0}, // [14:0] addr; // 15-bit row/column address
rom_cmd[1]? rom_cmd[1]?
row_col_bank[2:0]: row_col_bank[2:0]:
col_bank[2:0], // col_bank[2:0], //
full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic. full_cmd[0]==0 (never write/precharge) => enc_cmd_reg[11]==0 full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic. full_cmd[0]==0 (never write/precharge) => enc_cmd_reg[11]==0
1'b0, // odt_en; // enable ODT 1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE 1'b0, // cke; // disable CKE
...@@ -300,13 +299,13 @@ module cmd_encod_tiled_32_rd #( ...@@ -300,13 +299,13 @@ module cmd_encod_tiled_32_rd #(
fifo_2regs #( fifo_2regs #(
.WIDTH(COLADDR_NUMBER) .WIDTH(COLADDR_NUMBER)
) fifo_2regs_i ( ) fifo_2regs_i (
.rst (rst), // input .mrst (mrst), // input
.clk (clk), // input .clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0] .din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input .wr (pre_act), // input
.rd(pre_read && !rom_r[ENC_NOP]), // input - update only after the second READ .rd (pre_read && !rom_r[ENC_NOP]), // input - update only after the second READ
.srst(start_d), // input .srst (start_d), // input
.dout(col_bank) // output[15:0] .dout (col_bank) // output[15:0]
); );
`include "includes/x393_mcontr_encode_cmd.vh" `include "includes/x393_mcontr_encode_cmd.vh"
......
...@@ -30,7 +30,7 @@ module cmd_encod_tiled_32_rw #( ...@@ -30,7 +30,7 @@ module cmd_encod_tiled_32_rw #(
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period) parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) ( ) (
input rst, input mrst,
input clk, input clk,
// programming interface // programming interface
input [2:0] start_bank, // bank address input [2:0] start_bank, // bank address
...@@ -63,21 +63,21 @@ module cmd_encod_tiled_32_rw #( ...@@ -63,21 +63,21 @@ module cmd_encod_tiled_32_rw #(
.CMD_DONE_BIT (CMD_DONE_BIT), .CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL) .RSEL (RSEL)
) cmd_encod_tiled_rd_i ( ) cmd_encod_tiled_rd_i (
.rst (rst), // input .mrst (mrst), // input
.clk (clk), // input .clk (clk), // input
.start_bank (start_bank), // input[2:0] .start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0] .start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0] .start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0] .rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0] .num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0] .num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input .keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input .skip_next_page_in (skip_next_page_in), // input
.start (start_rd), // input .start (start_rd), // input
.enc_cmd (enc_cmd_rd), // output[31:0] reg .enc_cmd (enc_cmd_rd), // output[31:0] reg
.enc_wr (enc_wr_rd), // output reg .enc_wr (enc_wr_rd), // output reg
.enc_done (enc_done_rd) // output reg .enc_done (enc_done_rd) // output reg
); );
cmd_encod_tiled_32_wr #( cmd_encod_tiled_32_wr #(
...@@ -87,28 +87,28 @@ module cmd_encod_tiled_32_rw #( ...@@ -87,28 +87,28 @@ module cmd_encod_tiled_32_rw #(
.CMD_DONE_BIT (CMD_DONE_BIT), .CMD_DONE_BIT (CMD_DONE_BIT),
.WSEL (WSEL) .WSEL (WSEL)
) cmd_encod_tiled_wr_i ( ) cmd_encod_tiled_wr_i (
.rst (rst), // input .mrst (mrst), // input
.clk (clk), // input .clk (clk), // input
.start_bank (start_bank), // input[2:0] .start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0] .start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0] .start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0] .rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0] .num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0] .num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input .keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input .skip_next_page_in (skip_next_page_in), // input
.start (start_wr), // input .start (start_wr), // input
.enc_cmd (enc_cmd_wr), // output[31:0] reg .enc_cmd (enc_cmd_wr), // output[31:0] reg
.enc_wr (enc_wr_wr), // output reg .enc_wr (enc_wr_wr), // output reg
.enc_done (enc_done_wr) // output reg .enc_done (enc_done_wr) // output reg
); );
always @(posedge rst or posedge clk) begin always @(posedge clk) begin
if (rst) start <= 0; if (mrst) start <= 0;
else start <= start_rd || start_wr; else start <= start_rd || start_wr;
if (rst) select_wr <= 0; if (mrst) select_wr <= 0;
else if (start_rd) select_wr <= 0; else if (start_rd) select_wr <= 0;
else if (start_wr) select_wr <= 1; else if (start_wr) select_wr <= 1;
end end
......
...@@ -50,7 +50,7 @@ module cmd_encod_tiled_32_wr #( ...@@ -50,7 +50,7 @@ module cmd_encod_tiled_32_wr #(
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter WSEL= 1'b0 parameter WSEL= 1'b0
) ( ) (
input rst, input mrst,
input clk, input clk,
// programming interface // programming interface
input [2:0] start_bank, // bank address input [2:0] start_bank, // bank address
...@@ -164,60 +164,57 @@ module cmd_encod_tiled_32_wr #( ...@@ -164,60 +164,57 @@ module cmd_encod_tiled_32_wr #(
assign pre_write= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command assign pre_write= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
always @ (posedge rst or posedge clk) begin always @ (posedge clk) begin
if (rst) gen_run <= 0; if (mrst) gen_run <= 0;
else if (start_d) gen_run<= 1; // delaying else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0; else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0; if (mrst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
if (rst) num_cols128_m1 <= 0; if (mrst) num_cols128_m1 <= 0;
else if (start) num_cols128_m1 <= num_cols_in_m1 & ~1; // number of r16-byte columns (without LSB - number of 32-byte columns) else if (start) num_cols128_m1 <= num_cols_in_m1 & ~1; // number of r16-byte columns (without LSB - number of 32-byte columns)
if (rst) start_d <=0; if (mrst) start_d <=0;
else start_d <= start; else start_d <= start;
if (rst) top_rc <= 0; if (mrst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+2; else if (start_d) top_rc <= {row,col}+2;
else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA
if (rst) row_col_bank <= 0; if (mrst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d? else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (rst) scan_row <= 0; if (mrst) scan_row <= 0;
else if (start_d) scan_row <= 0; else if (start_d) scan_row <= 0;
else if (pre_act) scan_row <= last_row?0:scan_row+1; else if (pre_act) scan_row <= last_row?0:scan_row+1;
if (rst) scan_col <= 0; if (mrst) scan_col <= 0;
else if (start_d) scan_col <= 0; else if (start_d) scan_col <= 0;
else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ
if (rst) first_col <= 0; if (mrst) first_col <= 0;
else if (start_d) first_col <= 1; else if (start_d) first_col <= 1;
else if (pre_act && last_row) first_col <= 0; else if (pre_act && last_row) first_col <= 0;
if (rst) last_col <= 0; if (mrst) last_col <= 0;
else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1; else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ? else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ?
if (rst) enable_autopre <= 0; if (mrst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0; else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
if (rst) loop_continue<=0; if (mrst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row; else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (rst) gen_addr <= 0; if (mrst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0; else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop else gen_addr <= gen_addr+1; // not in a loop
end end
always @ (posedge clk) if (start) begin always @ (posedge clk) if (start) begin
...@@ -230,8 +227,8 @@ module cmd_encod_tiled_32_wr #( ...@@ -230,8 +227,8 @@ module cmd_encod_tiled_32_wr #(
end end
// ROM-based (registered output) encoded sequence // ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin always @ (posedge clk) begin
if (rst) rom_r <= 0; if (mrst) rom_r <= 0;
else case (gen_addr) else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE 4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; 4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
...@@ -256,17 +253,15 @@ module cmd_encod_tiled_32_wr #( ...@@ -256,17 +253,15 @@ module cmd_encod_tiled_32_wr #(
endcase endcase
end end
always @ (posedge rst or posedge clk) begin always @ (posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0; if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d; ***** else enc_wr <= gen_run; // || gen_run_d; *****
if (rst) enc_done <= 0; if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d; ***** else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****
if (rst) enc_cmd <= 0; if (mrst) enc_cmd <= 0;
else if (gen_run) begin else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate rom_cmd[1]? // activate
...@@ -311,7 +306,7 @@ module cmd_encod_tiled_32_wr #( ...@@ -311,7 +306,7 @@ module cmd_encod_tiled_32_wr #(
fifo_2regs #( fifo_2regs #(
.WIDTH(COLADDR_NUMBER) .WIDTH(COLADDR_NUMBER)
) fifo_2regs_i ( ) fifo_2regs_i (
.rst (rst), // input .mrst (mrst), // input
.clk (clk), // input .clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0] .din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input .wr(pre_act), // input
......
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...@@ -529,19 +529,16 @@ module memctrl16 #( ...@@ -529,19 +529,16 @@ module memctrl16 #(
// temporary debug data // temporary debug data
,output [11:0] tmp_debug // add some signals generated here? ,output [11:0] tmp_debug // add some signals generated here?
); );
//wire rst=rst_in; // TODO: decide where to generate
wire ext_buf_rd; wire ext_buf_rd;
wire ext_buf_rpage_nxt; wire ext_buf_rpage_nxt;
wire ext_buf_page_nxt; wire ext_buf_page_nxt;
// wire [6:0] ext_buf_raddr;
wire [3:0] ext_buf_rchn; wire [3:0] ext_buf_rchn;
wire ext_buf_rrefresh; wire ext_buf_rrefresh;
wire ext_buf_rrun; // run read sequence (to be used with external buffer to set initial address wire ext_buf_rrun; // run read sequence (to be used with external buffer to set initial address
reg [63:0] ext_buf_rdata; reg [63:0] ext_buf_rdata;
wire ext_buf_wr; wire ext_buf_wr;
wire ext_buf_wpage_nxt; wire ext_buf_wpage_nxt;
// wire [6:0] ext_buf_waddr;
wire [3:0] ext_buf_wchn; wire [3:0] ext_buf_wchn;
wire ext_buf_wrefresh; wire ext_buf_wrefresh;
wire ext_buf_wrun; // @negedge,first cycle of sequencer run matching write delay wire ext_buf_wrun; // @negedge,first cycle of sequencer run matching write delay
......
...@@ -224,22 +224,16 @@ module mcontr_sequencer #( ...@@ -224,22 +224,16 @@ module mcontr_sequencer #(
wire [31:0] phy_cmd1_word; // cmd1 buffer output wire [31:0] phy_cmd1_word; // cmd1 buffer output
reg buf_raddr_reset; reg buf_raddr_reset;
reg buf_addr_reset; // generated regardless of read/write reg buf_addr_reset; // generated regardless of read/write
// reg [ 6:0] buf_raddr;
reg buf_waddr_reset_negedge; reg buf_waddr_reset_negedge;
// reg [ 6:0] buf_waddr_negedge;
reg buf_wr_negedge; reg buf_wr_negedge;
wire [63:0] buf_wdata; // output[63:0] wire [63:0] buf_wdata; // output[63:0]
reg [63:0] buf_wdata_negedge; // output[63:0] reg [63:0] buf_wdata_negedge; // output[63:0]
wire [63:0] buf_rdata; // multiplexed input from one of the write channels buffer wire [63:0] buf_rdata; // multiplexed input from one of the write channels buffer
// wire [63:0] buf1_rdata;
wire buf_wr; // delayed by specified number of clock cycles wire buf_wr; // delayed by specified number of clock cycles
wire buf_wr_ndly; // before dealy wire buf_wr_ndly; // before dealy
wire buf_rd; // read next 64 bits from the buffer, need one extra pre-read wire buf_rd; // read next 64 bits from the buffer, need one extra pre-read
wire buf_rst; // reset buffer address to wire buf_rst; // reset buffer address to
wire buf_rst_d; //buf_rst delayed to match buf_wr wire buf_rst_d; //buf_rst delayed to match buf_wr
// wire rst=rst_in;
// wire [ 9:0] next_cmd_addr;
reg [ 9:0] cmd_addr; // command word address reg [ 9:0] cmd_addr; // command word address
reg cmd_sel; reg cmd_sel;
reg [ 2:0] cmd_busy; // bit 0 - immediately, reg [ 2:0] cmd_busy; // bit 0 - immediately,
...@@ -252,8 +246,6 @@ module mcontr_sequencer #( ...@@ -252,8 +246,6 @@ module mcontr_sequencer #(
wire pause; // do not register new data from the command memory wire pause; // do not register new data from the command memory
reg [CMD_PAUSE_BITS-1:0] pause_cntr; reg [CMD_PAUSE_BITS-1:0] pause_cntr;
// reg [1:0] buf_page; // one of 4 pages in the channel buffer to use for R/W
// reg [15:0] buf_sel_1hot; // 1 hot channel buffer select
wire [3:0] run_chn_w_d; // run chn delayed to match buf_wr delay wire [3:0] run_chn_w_d; // run chn delayed to match buf_wr delay
wire run_refresh_w_d; // run refresh delayed to match buf_wr delay wire run_refresh_w_d; // run refresh delayed to match buf_wr delay
wire run_w_d; wire run_w_d;
......
...@@ -27,6 +27,9 @@ module clocks393#( ...@@ -27,6 +27,9 @@ module clocks393#(
parameter CLK_CNTRL = 0, parameter CLK_CNTRL = 0,
parameter CLK_STATUS = 1, parameter CLK_STATUS = 1,
parameter CLK_RESET = 'h0, // which clocks should stay reset after release of masrter reset {ff1,ff0,mem,sync,xclk,pclk,xclk}
parameter CLK_PWDWN = 'h0, // which clocks should stay powered down after release of masrter reset {sync,xclk,pclk,xclk}
parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200
parameter DIVCLK_DIVIDE_AXIHP = 1, parameter DIVCLK_DIVIDE_AXIHP = 1,
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
...@@ -80,7 +83,7 @@ module clocks393#( ...@@ -80,7 +83,7 @@ module clocks393#(
parameter FFCLK1_IOSTANDARD = "DEFAULT" parameter FFCLK1_IOSTANDARD = "DEFAULT"
)( )(
// input rst, input async_rst, // always reset MMCM/PLL
input mclk, // global clock, comes from the memory controller (uses aclk generated here) input mclk, // global clock, comes from the memory controller (uses aclk generated here)
input mrst, input mrst,
// command/status interface // command/status interface
...@@ -103,7 +106,11 @@ module clocks393#( ...@@ -103,7 +106,11 @@ module clocks393#(
output xclk2x, // global clock for compressor, 2x frequency (now 200MHz) output xclk2x, // global clock for compressor, 2x frequency (now 200MHz)
output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)? output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
output time_ref, // non-global, just RTC (currently just mclk/8 = 25 MHz) output time_ref, // non-global, just RTC (currently just mclk/8 = 25 MHz)
input [1:0] extra_status // just extra two status bits from the top module input [1:0] extra_status, // just extra two status bits from the top module
output locked_sync_clk,
output locked_xclk,
output locked_pclk,
output locked_hclk
); );
wire memclk; wire memclk;
wire ffclk0; wire ffclk0;
...@@ -116,23 +123,29 @@ module clocks393#( ...@@ -116,23 +123,29 @@ module clocks393#(
wire set_ctrl_w = cmd_we & ((cmd_a && CLK_MASK) == CLK_CNTRL); wire set_ctrl_w = cmd_we & ((cmd_a && CLK_MASK) == CLK_CNTRL);
wire set_status_w = cmd_we & ((cmd_a && CLK_MASK) == CLK_STATUS); wire set_status_w = cmd_we & ((cmd_a && CLK_MASK) == CLK_STATUS);
wire [3:0] locked; wire [3:0] locked;
reg [6:0] reset_clk = 0; reg [6:0] reset_clk = CLK_RESET;
reg [3:0] pwrdwn_clk = 0; reg [3:0] pwrdwn_clk = CLK_PWDWN;
reg [2:0] test_clk; // FF to test input clocks are running reg [2:0] test_clk; // FF to test input clocks are running
wire memclk_rst = reset_clk[4]; wire memclk_rst = reset_clk[4];
wire ffclk0_rst = reset_clk[5]; wire ffclk0_rst = reset_clk[5];
wire ffclk1_rst = reset_clk[6]; wire ffclk1_rst = reset_clk[6];
assign locked_sync_clk = locked[3];
assign locked_xclk = locked[2];
assign locked_pclk = locked[1];
assign locked_hclk = locked[0];
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (mrst) reset_clk <= 0; if (mrst) reset_clk <= CLK_RESET;
else if (set_ctrl_w) reset_clk <= {cmd_data[10:8], cmd_data[3:0]}; else if (set_ctrl_w) reset_clk <= {cmd_data[10:8], cmd_data[3:0]};
if (mrst) pwrdwn_clk <= 0; if (mrst) pwrdwn_clk <= CLK_PWDWN;
else if (set_ctrl_w) pwrdwn_clk <= cmd_data[7:4]; else if (set_ctrl_w) pwrdwn_clk <= cmd_data[7:4];
end end