removed most async resets (210ed954) · Commits · Elphel / x393

axi/membridge.v

+4 −3

Original line number	Original line	Diff line number	Diff line
	@@ -404,10 +404,11 @@ module membridge#(
	if (!rw_in_progress) buf_in_line64 <= 0;		if (!rw_in_progress) buf_in_line64 <= 0;
	else if (buf_rdwr) buf_in_line64 <= is_last_in_line? {(FRAME_WIDTH_BITS+1){1'b0}} : (buf_in_line64 +1);		else if (buf_rdwr) buf_in_line64 <= is_last_in_line? {(FRAME_WIDTH_BITS+1){1'b0}} : (buf_in_line64 +1);

	next_page_rd <= next_page_rd_w;		if (hrst) next_page_rd <= 0;
	next_page_wr <= next_page_wr_w;		else next_page_rd <= next_page_rd_w;


			if (hrst) next_page_wr <= 0;
			else next_page_wr <= next_page_wr_w;

	end		end

memctrl/cmd_encod_4mux.v

+4 −4

Original line number	Original line	Diff line number	Diff line
	@@ -21,7 +21,7 @@
	`timescale 1ns/1ps		`timescale 1ns/1ps

	module cmd_encod_4mux(		module cmd_encod_4mux(
	input rst,		input mrst,
	input clk,		input clk,

	input start0, // this channel was started		input start0, // this channel was started
	@@ -51,11 +51,11 @@ module cmd_encod_4mux(
	);		);
	reg [3:0] select;		reg [3:0] select;
	wire start_w= start0 \| start1 \|start2 \| start3;		wire start_w= start0 \| start1 \|start2 \| start3;
	always @ (posedge rst or posedge clk) begin		always @ (posedge clk) begin
	if (rst) start <= 0;		if (mrst) start <= 0;
	else start <= start_w;		else start <= start_w;

	if (rst) select <= 0;		if (mrst) select <= 0;
	else if (start_w) select <={ // normally should be no simultaneous starts, so priority is not needed		else if (start_w) select <={ // normally should be no simultaneous starts, so priority is not needed
	start3 & ~start2 & ~start1 & ~start0,		start3 & ~start2 & ~start1 & ~start0,
	start2 & ~start1 & ~start0,		start2 & ~start1 & ~start0,

memctrl/cmd_encod_tiled_32_rd.v

+30 −31

Original line number	Original line	Diff line number	Diff line
	@@ -50,7 +50,7 @@ module cmd_encod_tiled_32_rd #(
	parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts		parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
	parameter RSEL= 1'b1 // Late/early READ commands		parameter RSEL= 1'b1 // Late/early READ commands
	) (		) (
	input rst,		input mrst,
	input clk,		input clk,
	// programming interface		// programming interface
	input [2:0] start_bank, // bank address		input [2:0] start_bank, // bank address
	@@ -157,56 +157,57 @@ module cmd_encod_tiled_32_rd #(
	assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command		assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command


	always @ (posedge rst or posedge clk) begin		always @ (posedge clk) begin
	if (rst) gen_run <= 0;		if (mrst) gen_run <= 0;
	else if (start_d) gen_run<= 1; // delaying		else if (start_d) gen_run<= 1; // delaying
	else if (pre_done) gen_run<= 0;		else if (pre_done) gen_run<= 0;

	// if (rst) gen_run_d <= 0;		// if (rst) gen_run_d <= 0;
	// else gen_run_d <= gen_run;		// else gen_run_d <= gen_run;

	if (rst) num_rows_m1 <= 0;		if (mrst) num_rows_m1 <= 0;
	else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows		else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
	if (rst) num_cols128_m2 <= 0;
			if (mrst) num_cols128_m2 <= 0;
	else if (start) num_cols128_m2 <= num_cols_in_m1 & ~1; // number of r32-byte columns		else if (start) num_cols128_m2 <= num_cols_in_m1 & ~1; // number of r32-byte columns

	if (rst) start_d <=0;		if (mrst) start_d <=0;
	else start_d <= start;		else start_d <= start;

	if (rst) top_rc <= 0;		if (mrst) top_rc <= 0;
	else if (start_d) top_rc <= {row,col}+2;		else if (start_d) top_rc <= {row,col}+2;
	else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA		else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA

	if (rst) row_col_bank <= 0;		if (mrst) row_col_bank <= 0;
	else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?		else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?

	else if (pre_act) row_col_bank <= row_col_bank_next_w;		else if (pre_act) row_col_bank <= row_col_bank_next_w;


	if (rst) scan_row <= 0;		if (mrst) scan_row <= 0;
	else if (start_d) scan_row <= 0;		else if (start_d) scan_row <= 0;
	else if (pre_act) scan_row <= last_row?0:scan_row+1;		else if (pre_act) scan_row <= last_row?0:scan_row+1;

	if (rst) scan_col <= 0;		if (mrst) scan_col <= 0;
	else if (start_d) scan_col <= 0;		else if (start_d) scan_col <= 0;
	else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ		else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ

	if (rst) first_col <= 0;		if (mrst) first_col <= 0;
	else if (start_d) first_col <= 1;		else if (start_d) first_col <= 1;
	else if (pre_act && last_row) first_col <= 0;		else if (pre_act && last_row) first_col <= 0;

	if (rst) last_col <= 0;		if (mrst) last_col <= 0;
	else if (start_d) last_col <= num_cols128_m2==0; // if single column - will start with 1'b1;		else if (start_d) last_col <= num_cols128_m2==0; // if single column - will start with 1'b1;
	else if (pre_act) last_col <= (scan_col==num_cols128_m2); // too early for READ ?		else if (pre_act) last_col <= (scan_col==num_cols128_m2); // too early for READ ?

	if (rst) enable_autopre <= 0;		if (mrst) enable_autopre <= 0;
	else if (start_d) enable_autopre <= 0;		else if (start_d) enable_autopre <= 0;
	else if (pre_act) enable_autopre <= last_col \|\| !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column		else if (pre_act) enable_autopre <= last_col \|\| !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column

	if (rst) loop_continue<=0;		if (mrst) loop_continue<=0;
	else loop_continue <= (scan_col==num_cols128_m2) && last_row;		else loop_continue <= (scan_col==num_cols128_m2) && last_row;

	if (rst) gen_addr <= 0;		if (mrst) gen_addr <= 0;
	else if (!start_d && !gen_run) gen_addr <= 0;		else if (!start_d && !gen_run) gen_addr <= 0;
	else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter		else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
	else gen_addr <= gen_addr+1; // not in a loop		else gen_addr <= gen_addr+1; // not in a loop
	@@ -222,8 +223,8 @@ module cmd_encod_tiled_32_rd #(
	end		end

	// ROM-based (registered output) encoded sequence		// ROM-based (registered output) encoded sequence
	always @ (posedge rst or posedge clk) begin		always @ (posedge clk) begin
	if (rst) rom_r <= 0;		if (mrst) rom_r <= 0;
	else case (gen_addr)		else case (gen_addr)
	4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE		4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
	4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);		4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
	@@ -246,17 +247,15 @@ module cmd_encod_tiled_32_rd #(
	default:rom_r <= 0;		default:rom_r <= 0;
	endcase		endcase
	end		end
	always @ (posedge rst or posedge clk) begin		always @ (posedge clk) begin
	// if (rst) done <= 0;
	// else done <= pre_done;

	if (rst) enc_wr <= 0;		if (mrst) enc_wr <= 0;
	else enc_wr <= gen_run; // \|\| gen_run_d;		else enc_wr <= gen_run; // \|\| gen_run_d;

	if (rst) enc_done <= 0;		if (mrst) enc_done <= 0;
	else enc_done <= enc_wr && !gen_run; // !gen_run_d;		else enc_done <= enc_wr && !gen_run; // !gen_run_d;

	if (rst) enc_cmd <= 0;		if (mrst) enc_cmd <= 0;
	// else if ((rom_cmd==0) \|\| (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause		// else if ((rom_cmd==0) \|\| (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
	else if (gen_run) begin		else if (gen_run) begin
	if (rom_cmd[0] \|\| (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command		if (rom_cmd[0] \|\| (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
	@@ -300,7 +299,7 @@ module cmd_encod_tiled_32_rd #(
	fifo_2regs #(		fifo_2regs #(
	.WIDTH(COLADDR_NUMBER)		.WIDTH(COLADDR_NUMBER)
	) fifo_2regs_i (		) fifo_2regs_i (
	.rst (rst), // input		.mrst (mrst), // input
	.clk (clk), // input		.clk (clk), // input
	.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]		.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
	.wr (pre_act), // input		.wr (pre_act), // input

memctrl/cmd_encod_tiled_32_rw.v

+30 −30

Original line number	Original line	Diff line number	Diff line
	@@ -30,7 +30,7 @@ module cmd_encod_tiled_32_rw #(
	parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)		parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)

	) (		) (
	input rst,		input mrst,
	input clk,		input clk,
	// programming interface		// programming interface
	input [2:0] start_bank, // bank address		input [2:0] start_bank, // bank address
	@@ -63,7 +63,7 @@ module cmd_encod_tiled_32_rw #(
	.CMD_DONE_BIT (CMD_DONE_BIT),		.CMD_DONE_BIT (CMD_DONE_BIT),
	.RSEL (RSEL)		.RSEL (RSEL)
	) cmd_encod_tiled_rd_i (		) cmd_encod_tiled_rd_i (
	.rst (rst), // input		.mrst (mrst), // input
	.clk (clk), // input		.clk (clk), // input
	.start_bank (start_bank), // input[2:0]		.start_bank (start_bank), // input[2:0]
	.start_row (start_row), // input[14:0]		.start_row (start_row), // input[14:0]
	@@ -87,7 +87,7 @@ module cmd_encod_tiled_32_rw #(
	.CMD_DONE_BIT (CMD_DONE_BIT),		.CMD_DONE_BIT (CMD_DONE_BIT),
	.WSEL (WSEL)		.WSEL (WSEL)
	) cmd_encod_tiled_wr_i (		) cmd_encod_tiled_wr_i (
	.rst (rst), // input		.mrst (mrst), // input
	.clk (clk), // input		.clk (clk), // input
	.start_bank (start_bank), // input[2:0]		.start_bank (start_bank), // input[2:0]
	.start_row (start_row), // input[14:0]		.start_row (start_row), // input[14:0]
	@@ -104,11 +104,11 @@ module cmd_encod_tiled_32_rw #(
	.enc_done (enc_done_wr) // output reg		.enc_done (enc_done_wr) // output reg
	);		);

	always @(posedge rst or posedge clk) begin		always @(posedge clk) begin
	if (rst) start <= 0;		if (mrst) start <= 0;
	else start <= start_rd \|\| start_wr;		else start <= start_rd \|\| start_wr;

	if (rst) select_wr <= 0;		if (mrst) select_wr <= 0;
	else if (start_rd) select_wr <= 0;		else if (start_rd) select_wr <= 0;
	else if (start_wr) select_wr <= 1;		else if (start_wr) select_wr <= 1;
	end		end

memctrl/cmd_encod_tiled_32_wr.v

+27 −32

Original line number	Original line	Diff line number	Diff line
	@@ -50,7 +50,7 @@ module cmd_encod_tiled_32_wr #(
	parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts		parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
	parameter WSEL= 1'b0		parameter WSEL= 1'b0
	) (		) (
	input rst,		input mrst,
	input clk,		input clk,
	// programming interface		// programming interface
	input [2:0] start_bank, // bank address		input [2:0] start_bank, // bank address
	@@ -164,57 +164,54 @@ module cmd_encod_tiled_32_wr #(
	assign pre_write= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command		assign pre_write= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command


	always @ (posedge rst or posedge clk) begin		always @ (posedge clk) begin
	if (rst) gen_run <= 0;		if (mrst) gen_run <= 0;
	else if (start_d) gen_run<= 1; // delaying		else if (start_d) gen_run<= 1; // delaying
	else if (pre_done) gen_run<= 0;		else if (pre_done) gen_run<= 0;

	// if (rst) gen_run_d <= 0;
	// else gen_run_d <= gen_run;

	if (rst) num_rows_m1 <= 0;		if (mrst) num_rows_m1 <= 0;
	else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows		else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows

	if (rst) num_cols128_m1 <= 0;		if (mrst) num_cols128_m1 <= 0;
	else if (start) num_cols128_m1 <= num_cols_in_m1 & ~1; // number of r16-byte columns (without LSB - number of 32-byte columns)		else if (start) num_cols128_m1 <= num_cols_in_m1 & ~1; // number of r16-byte columns (without LSB - number of 32-byte columns)

	if (rst) start_d <=0;		if (mrst) start_d <=0;
	else start_d <= start;		else start_d <= start;

	if (rst) top_rc <= 0;		if (mrst) top_rc <= 0;
	else if (start_d) top_rc <= {row,col}+2;		else if (start_d) top_rc <= {row,col}+2;
	else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA		else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA

	if (rst) row_col_bank <= 0;		if (mrst) row_col_bank <= 0;
	else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?		else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?

	else if (pre_act) row_col_bank <= row_col_bank_next_w;		else if (pre_act) row_col_bank <= row_col_bank_next_w;


	if (rst) scan_row <= 0;		if (mrst) scan_row <= 0;
	else if (start_d) scan_row <= 0;		else if (start_d) scan_row <= 0;
	else if (pre_act) scan_row <= last_row?0:scan_row+1;		else if (pre_act) scan_row <= last_row?0:scan_row+1;

	if (rst) scan_col <= 0;		if (mrst) scan_col <= 0;
	else if (start_d) scan_col <= 0;		else if (start_d) scan_col <= 0;
	else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ		else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ

	if (rst) first_col <= 0;		if (mrst) first_col <= 0;
	else if (start_d) first_col <= 1;		else if (start_d) first_col <= 1;
	else if (pre_act && last_row) first_col <= 0;		else if (pre_act && last_row) first_col <= 0;

	if (rst) last_col <= 0;		if (mrst) last_col <= 0;
	else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1;		else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1;
	else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ?		else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ?

	if (rst) enable_autopre <= 0;		if (mrst) enable_autopre <= 0;
	else if (start_d) enable_autopre <= 0;		else if (start_d) enable_autopre <= 0;
	else if (pre_act) enable_autopre <= last_col \|\| !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column		else if (pre_act) enable_autopre <= last_col \|\| !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column

	if (rst) loop_continue<=0;		if (mrst) loop_continue<=0;
	else loop_continue <= (scan_col==num_cols128_m1) && last_row;		else loop_continue <= (scan_col==num_cols128_m1) && last_row;

	if (rst) gen_addr <= 0;		if (mrst) gen_addr <= 0;
	else if (!start_d && !gen_run) gen_addr <= 0;		else if (!start_d && !gen_run) gen_addr <= 0;
	else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter		else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
	else gen_addr <= gen_addr+1; // not in a loop		else gen_addr <= gen_addr+1; // not in a loop
	@@ -230,8 +227,8 @@ module cmd_encod_tiled_32_wr #(
	end		end

	// ROM-based (registered output) encoded sequence		// ROM-based (registered output) encoded sequence
	always @ (posedge rst or posedge clk) begin		always @ (posedge clk) begin
	if (rst) rom_r <= 0;		if (mrst) rom_r <= 0;
	else case (gen_addr)		else case (gen_addr)
	4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE		4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
	4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD) ;		4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD) ;
	@@ -256,17 +253,15 @@ module cmd_encod_tiled_32_wr #(
	endcase		endcase
	end		end

	always @ (posedge rst or posedge clk) begin		always @ (posedge clk) begin
	// if (rst) done <= 0;
	// else done <= pre_done;

	if (rst) enc_wr <= 0;		if (mrst) enc_wr <= 0;
	else enc_wr <= gen_run; // \|\| gen_run_d; *****		else enc_wr <= gen_run; // \|\| gen_run_d; *****

	if (rst) enc_done <= 0;		if (mrst) enc_done <= 0;
	else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****		else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****

	if (rst) enc_cmd <= 0;		if (mrst) enc_cmd <= 0;
	else if (gen_run) begin		else if (gen_run) begin
	if (rom_cmd[0] \|\| (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command		if (rom_cmd[0] \|\| (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
	rom_cmd[1]? // activate		rom_cmd[1]? // activate
	@@ -311,7 +306,7 @@ module cmd_encod_tiled_32_wr #(
	fifo_2regs #(		fifo_2regs #(
	.WIDTH(COLADDR_NUMBER)		.WIDTH(COLADDR_NUMBER)
	) fifo_2regs_i (		) fifo_2regs_i (
	.rst (rst), // input		.mrst (mrst), // input
	.clk (clk), // input		.clk (clk), // input
	.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]		.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
	.wr(pre_act), // input		.wr(pre_act), // input

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