Commit 210ed954 authored by Andrey Filippov's avatar Andrey Filippov

removed most async resets

parent b721ae66
......@@ -404,10 +404,11 @@ module membridge#(
if (!rw_in_progress) buf_in_line64 <= 0;
else if (buf_rdwr) buf_in_line64 <= is_last_in_line? {(FRAME_WIDTH_BITS+1){1'b0}} : (buf_in_line64 +1);
next_page_rd <= next_page_rd_w;
next_page_wr <= next_page_wr_w;
if (hrst) next_page_rd <= 0;
else next_page_rd <= next_page_rd_w;
if (hrst) next_page_wr <= 0;
else next_page_wr <= next_page_wr_w;
end
......
......@@ -21,7 +21,7 @@
`timescale 1ns/1ps
module cmd_encod_4mux(
input rst,
input mrst,
input clk,
input start0, // this channel was started
......@@ -51,11 +51,11 @@ module cmd_encod_4mux(
);
reg [3:0] select;
wire start_w= start0 | start1 |start2 | start3;
always @ (posedge rst or posedge clk) begin
if (rst) start <= 0;
always @ (posedge clk) begin
if (mrst) start <= 0;
else start <= start_w;
if (rst) select <= 0;
if (mrst) select <= 0;
else if (start_w) select <={ // normally should be no simultaneous starts, so priority is not needed
start3 & ~start2 & ~start1 & ~start0,
start2 & ~start1 & ~start0,
......
......@@ -50,7 +50,7 @@ module cmd_encod_tiled_32_rd #(
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter RSEL= 1'b1 // Late/early READ commands
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -157,56 +157,57 @@ module cmd_encod_tiled_32_rd #(
assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
always @ (posedge clk) begin
if (mrst) gen_run <= 0;
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
if (mrst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
if (rst) num_cols128_m2 <= 0;
if (mrst) num_cols128_m2 <= 0;
else if (start) num_cols128_m2 <= num_cols_in_m1 & ~1; // number of r32-byte columns
if (rst) start_d <=0;
if (mrst) start_d <=0;
else start_d <= start;
if (rst) top_rc <= 0;
if (mrst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+2;
else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA
if (rst) row_col_bank <= 0;
if (mrst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (rst) scan_row <= 0;
if (mrst) scan_row <= 0;
else if (start_d) scan_row <= 0;
else if (pre_act) scan_row <= last_row?0:scan_row+1;
if (rst) scan_col <= 0;
if (mrst) scan_col <= 0;
else if (start_d) scan_col <= 0;
else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ
if (rst) first_col <= 0;
if (mrst) first_col <= 0;
else if (start_d) first_col <= 1;
else if (pre_act && last_row) first_col <= 0;
if (rst) last_col <= 0;
if (mrst) last_col <= 0;
else if (start_d) last_col <= num_cols128_m2==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m2); // too early for READ ?
if (rst) enable_autopre <= 0;
if (mrst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
if (rst) loop_continue<=0;
if (mrst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m2) && last_row;
if (rst) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop
......@@ -222,8 +223,8 @@ module cmd_encod_tiled_32_rd #(
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
......@@ -246,17 +247,15 @@ module cmd_encod_tiled_32_rd #(
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
always @ (posedge clk) begin
if (rst) enc_wr <= 0;
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
if (mrst) enc_cmd <= 0;
// else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
......@@ -268,7 +267,7 @@ module cmd_encod_tiled_32_rd #(
3'b0}, // [14:0] addr; // 15-bit row/column address
rom_cmd[1]?
row_col_bank[2:0]:
col_bank[2:0], //
col_bank[2:0], //
full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic. full_cmd[0]==0 (never write/precharge) => enc_cmd_reg[11]==0
1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -300,13 +299,13 @@ module cmd_encod_tiled_32_rd #(
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
.rst (rst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input
.rd(pre_read && !rom_r[ENC_NOP]), // input - update only after the second READ
.srst(start_d), // input
.dout(col_bank) // output[15:0]
.mrst (mrst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr (pre_act), // input
.rd (pre_read && !rom_r[ENC_NOP]), // input - update only after the second READ
.srst (start_d), // input
.dout (col_bank) // output[15:0]
);
`include "includes/x393_mcontr_encode_cmd.vh"
......
......@@ -30,7 +30,7 @@ module cmd_encod_tiled_32_rw #(
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -63,21 +63,21 @@ module cmd_encod_tiled_32_rw #(
.CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.mrst (mrst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input
.start (start_rd), // input
.enc_cmd (enc_cmd_rd), // output[31:0] reg
.enc_wr (enc_wr_rd), // output reg
.enc_done (enc_done_rd) // output reg
.start (start_rd), // input
.enc_cmd (enc_cmd_rd), // output[31:0] reg
.enc_wr (enc_wr_rd), // output reg
.enc_done (enc_done_rd) // output reg
);
cmd_encod_tiled_32_wr #(
......@@ -87,28 +87,28 @@ module cmd_encod_tiled_32_rw #(
.CMD_DONE_BIT (CMD_DONE_BIT),
.WSEL (WSEL)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.mrst (mrst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input
.start (start_wr), // input
.enc_cmd (enc_cmd_wr), // output[31:0] reg
.enc_wr (enc_wr_wr), // output reg
.enc_done (enc_done_wr) // output reg
.start (start_wr), // input
.enc_cmd (enc_cmd_wr), // output[31:0] reg
.enc_wr (enc_wr_wr), // output reg
.enc_done (enc_done_wr) // output reg
);
always @(posedge rst or posedge clk) begin
if (rst) start <= 0;
always @(posedge clk) begin
if (mrst) start <= 0;
else start <= start_rd || start_wr;
if (rst) select_wr <= 0;
if (mrst) select_wr <= 0;
else if (start_rd) select_wr <= 0;
else if (start_wr) select_wr <= 1;
end
......
......@@ -50,7 +50,7 @@ module cmd_encod_tiled_32_wr #(
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter WSEL= 1'b0
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -164,60 +164,57 @@ module cmd_encod_tiled_32_wr #(
assign pre_write= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
always @ (posedge clk) begin
if (mrst) gen_run <= 0;
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
if (mrst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
if (rst) num_cols128_m1 <= 0;
if (mrst) num_cols128_m1 <= 0;
else if (start) num_cols128_m1 <= num_cols_in_m1 & ~1; // number of r16-byte columns (without LSB - number of 32-byte columns)
if (rst) start_d <=0;
if (mrst) start_d <=0;
else start_d <= start;
if (rst) top_rc <= 0;
if (mrst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+2;
else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA
if (rst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (mrst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (rst) scan_row <= 0;
if (mrst) scan_row <= 0;
else if (start_d) scan_row <= 0;
else if (pre_act) scan_row <= last_row?0:scan_row+1;
if (rst) scan_col <= 0;
if (mrst) scan_col <= 0;
else if (start_d) scan_col <= 0;
else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ
if (rst) first_col <= 0;
if (mrst) first_col <= 0;
else if (start_d) first_col <= 1;
else if (pre_act && last_row) first_col <= 0;
if (rst) last_col <= 0;
if (mrst) last_col <= 0;
else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ?
if (rst) enable_autopre <= 0;
if (mrst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
if (rst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (mrst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (rst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop
else gen_addr <= gen_addr+1; // not in a loop
end
always @ (posedge clk) if (start) begin
......@@ -230,8 +227,8 @@ module cmd_encod_tiled_32_wr #(
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
......@@ -256,17 +253,15 @@ module cmd_encod_tiled_32_wr #(
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
always @ (posedge clk) begin
if (rst) enc_wr <= 0;
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d; *****
if (rst) enc_done <= 0;
if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****
if (rst) enc_cmd <= 0;
if (mrst) enc_cmd <= 0;
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
......@@ -311,7 +306,7 @@ module cmd_encod_tiled_32_wr #(
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input
......
......@@ -388,19 +388,6 @@ module mcntrl393 #(
);
localparam COL_WDTH = COLADDR_NUMBER-3; // number of column address bits in bursts
localparam FRAME_WBP1 = FRAME_WIDTH_BITS + 1;
wire rrst=rst_in;
wire axi_rst=rst_in;
// Not yet connected
// wire [7:0] status_other_ad; // Other status byte-wide address/data
// wire status_other_rq; // Other status request
// wire status_other_start; // Other status packet transfer start (currently with 0 latency from status_root_rq)
//cmd_ps_pio_stb
// command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ...
// TODO: move to internal !
// Interface to channels to read/write memory (including 4 page BRAM buffers)
......@@ -767,37 +754,33 @@ module mcntrl393 #(
assign select_buf4rd_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf4wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF4_WR_ADDR) & MCONTR_WR_MASK)==0;
always @ (posedge axi_rst or posedge axi_clk) begin
if (axi_rst) select_cmd0 <= 0;
always @ (posedge axi_clk) begin
if (mrst) select_cmd0 <= 0;
else if (axiwr_start_burst) select_cmd0 <= select_cmd0_w;
if (axi_rst) select_buf0rd <= 0;
if (mrst) select_buf0rd <= 0;
else if (axird_start_burst) select_buf0rd <= select_buf0rd_w;
if (axi_rst) select_buf0wr <= 0;
else if (axiwr_start_burst) select_buf0wr <= select_buf0wr_w;
// if (axi_rst) select_buf1rd <= 0; // not used - replaced with membridge
// else if (axird_start_burst) select_buf1rd <= select_buf1rd_w; // not used - replaced with membridge
// if (axi_rst) select_buf1wr <= 0; // not used - replaced with membridge
// else if (axiwr_start_burst) select_buf1wr <= select_buf1wr_w; // not used - replaced with membridge
if (mrst) select_buf0wr <= 0;
else if (axiwr_start_burst) select_buf0wr <= select_buf0wr_w;
if (axi_rst) select_buf2rd <= 0;
if (mrst) select_buf2rd <= 0;
else if (axird_start_burst) select_buf2rd <= select_buf2rd_w;
if (axi_rst) select_buf2wr <= 0;
if (mrst) select_buf2wr <= 0;
else if (axiwr_start_burst) select_buf2wr <= select_buf2wr_w;
if (axi_rst) select_buf3rd <= 0;
if (mrst) select_buf3rd <= 0;
else if (axird_start_burst) select_buf3rd <= select_buf3rd_w;
if (axi_rst) select_buf3wr <= 0;
if (mrst) select_buf3wr <= 0;
else if (axiwr_start_burst) select_buf3wr <= select_buf3wr_w;
if (axi_rst) select_buf4rd <= 0;
if (mrst) select_buf4rd <= 0;
else if (axird_start_burst) select_buf4rd <= select_buf4rd_w;
if (axi_rst) select_buf4wr <= 0;
if (mrst) select_buf4wr <= 0;
else if (axiwr_start_burst) select_buf4wr <= select_buf4wr_w;
if (axi_rst) axird_selected_r <= 0;
if (mrst) axird_selected_r <= 0;
else if (axird_start_burst) axird_selected_r <= select_buf0rd_w || //select_buf1rd_w || // not used - replaced with membridge
select_buf2rd_w || select_buf3rd_w || select_buf4rd_w;
end
......@@ -1618,53 +1601,53 @@ module mcntrl393 #(
.RSEL (RSEL),
.WSEL (WSEL)
) cmd_encod_tiled_32_rw_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start_rd (tiled_rw_start_rd32), // input
.start_wr (tiled_rw_start_wr32), // input
.mrst (mrst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start_rd (tiled_rw_start_rd32), // input
.start_wr (tiled_rw_start_wr32), // input
.start (encod_tiled32_start_out), // output reg
.enc_cmd (encod_tiled32_cmd), // output[31:0] reg
.enc_wr (encod_tiled32_wr), // output reg
.enc_done (encod_tiled32_done) // output reg
.enc_cmd (encod_tiled32_cmd), // output[31:0] reg
.enc_wr (encod_tiled32_wr), // output reg
.enc_done (encod_tiled32_done) // output reg
);
// Combine sequencer data from multiple sources
cmd_encod_4mux cmd_encod_4mux_i (
.rst (rst), // input
.clk (mclk), // input
.mrst (mrst), // input
.clk (mclk), // input
// from ps pio
.start0 (channel_pgm_en0), // start_seq_ps_pio), // input
.enc_cmd0 ({22'b0,seq_data0}), // input[31:0]
.enc_wr0 (1'b0), // input
.enc_done0 (seq_set0), // input
.start0 (channel_pgm_en0), // start_seq_ps_pio), // input
.enc_cmd0 ({22'b0,seq_data0}), // input[31:0]
.enc_wr0 (1'b0), // input
.enc_done0 (seq_set0), // input
// from encod_linear_rw
.start1 (encod_linear_start_out), // input
.enc_cmd1 (encod_linear_cmd), // input[31:0]
.enc_wr1 (encod_linear_wr), // input
.enc_done1 (encod_linear_done), // input
.start1 (encod_linear_start_out) , // input
.enc_cmd1 (encod_linear_cmd), // input[31:0]
.enc_wr1 (encod_linear_wr), // input
.enc_done1 (encod_linear_done), // input
// from encod_tiled_rw
.start2 (encod_tiled16_start_out), // input
.enc_cmd2 (encod_tiled16_cmd), // input[31:0]
.enc_wr2 (encod_tiled16_wr), // input
.enc_done2 (encod_tiled16_done), // input
.enc_cmd2 (encod_tiled16_cmd), // input[31:0]
.enc_wr2 (encod_tiled16_wr), // input
.enc_done2 (encod_tiled16_done), // input
// from encod_tiled_32_rw
.start3 (encod_tiled32_start_out), // input
.enc_cmd3 (encod_tiled32_cmd), // input[31:0]
.enc_wr3 (encod_tiled32_wr), // input
.enc_done3 (encod_tiled32_done), // input
.enc_cmd3 (encod_tiled32_cmd), // input[31:0]
.enc_wr3 (encod_tiled32_wr), // input
.enc_done3 (encod_tiled32_done), // input
.start (), // output reg not used - may be needed for cascading. Pulse before any data output
.enc_cmd (seq_data), // output[31:0] reg
.enc_wr (seq_wr), // output reg
.enc_done (seq_set) // output reg
.enc_cmd (seq_data), // output[31:0] reg
.enc_wr (seq_wr), // output reg
.enc_done (seq_set) // output reg
);
......@@ -1739,105 +1722,104 @@ module mcntrl393 #(
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) memctrl16_i (
.rst_in (rst_in), // input
.clk_in (clk_in), // input
.mclk (mclk), // output
.mrst (mrst), // input
.locked (locked), // output
.ref_clk (ref_clk), // output
.idelay_ctrl_reset (idelay_ctrl_reset), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input
.status_ad (status_mcontr_ad[7:0]), // output[7:0]
.status_rq (status_mcontr_rq), // input request to send status downstream
.status_start (status_mcontr_start), // Acknowledge of the first status packet byte (address)
.rst_in (rst_in), // input
.clk_in (clk_in), // input
.mclk (mclk), // output
.mrst (mrst), // input
.locked (locked), // output
.ref_clk (ref_clk), // output
.idelay_ctrl_reset (idelay_ctrl_reset), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input
.status_ad (status_mcontr_ad[7:0]), // output[7:0]
.status_rq (status_mcontr_rq), // input request to send status downstream
.status_start (status_mcontr_start), // Acknowledge of the first status packet byte (address)
.cmd0_clk (axi_clk), // input
.cmd0_we (cmd_we), // input
.cmd0_addr (buf_waddr), // input[9:0]
.cmd0_data (buf_wdata), // input[31:0]
.cmd0_clk (axi_clk), // input
.cmd0_we (cmd_we), // input
.cmd0_addr (buf_waddr), // input[9:0]
.cmd0_data (buf_wdata), // input[31:0]
.seq_data (seq_data), // input[31:0]
.seq_wr (seq_wr), // not used: seq_wr0), // input
.seq_set (seq_set), // input
.seq_data (seq_data), // input[31:0]
.seq_wr (seq_wr), // not used: seq_wr0), // input
.seq_set (seq_set), // input
.want_rq0 (want_rq0), // input
.need_rq0 (need_rq0), // input
.channel_pgm_en0 (channel_pgm_en0), // output reg
.seq_done0 (seq_done0), // output
.page_nxt_chn0 (), //rpage_nxt_chn0), not used
.buf_run0 (buf_run0),
.buf_wr_chn0 (buf_wr_chn0), // output
.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // output
.buf_wdata_chn0 (buf_wdata_chn0), // output[63:0]
.buf_wrun0 (buf_wrun0),
.buf_rd_chn0 (buf_rd_chn0), // output
.buf_rpage_nxt_chn0 (buf_rpage_nxt_chn0), // output
.buf_rdata_chn0 (buf_rdata_chn0), // input[63:0]
.want_rq1 (want_rq1), // input
.need_rq1 (need_rq1), // input
.channel_pgm_en1 (channel_pgm_en1), // output reg
.seq_done1 (seq_done1), // output
.page_nxt_chn1 (page_ready_chn1), //rpage_nxt_chn0), not used
.buf_run1 (), //buf_run1),
.buf_wr_chn1 (buf_wr_chn1), // output
.buf_wpage_nxt_chn1 (buf_wpage_nxt_chn1), // output
.buf_wdata_chn1 (buf_wdata_chn1), // output[63:0]
.buf_wrun1 (), //buf_wrun1),
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_rpage_nxt_chn1 (rpage_nxt_chn1), // buf_rpage_nxt_chn1), // output
.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]
.want_rq0 (want_rq0), // input
.need_rq0 (need_rq0), // input
.channel_pgm_en0 (channel_pgm_en0), // output reg
.seq_done0 (seq_done0), // output
.page_nxt_chn0 (), //rpage_nxt_chn0), not used
.buf_run0 (buf_run0), // output
.buf_wr_chn0 (buf_wr_chn0), // output
.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // output
.buf_wdata_chn0 (buf_wdata_chn0), // output[63:0]
.buf_wrun0 (buf_wrun0), // output
.buf_rd_chn0 (buf_rd_chn0), // output
.buf_rpage_nxt_chn0 (buf_rpage_nxt_chn0), // output
.buf_rdata_chn0 (buf_rdata_chn0), // input[63:0]
.want_rq1 (want_rq1), // input
.need_rq1 (need_rq1), // input
.channel_pgm_en1 (channel_pgm_en1), // output reg
.seq_done1 (seq_done1), // output
.page_nxt_chn1 (page_ready_chn1), //rpage_nxt_chn0), not used
.buf_run1 (), // output
.buf_wr_chn1 (buf_wr_chn1), // output
.buf_wpage_nxt_chn1 (buf_wpage_nxt_chn1), // output
.buf_wdata_chn1 (buf_wdata_chn1), // output[63:0]
.buf_wrun1 (), // output//buf_wrun1),
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_rpage_nxt_chn1 (rpage_nxt_chn1), // buf_rpage_nxt_chn1), // output
.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]
.want_rq2 (want_rq2), // input
.need_rq2 (need_rq2), // input
.channel_pgm_en2 (channel_pgm_en2), // output reg
.seq_done2 (seq_done2), // output
.page_nxt_chn2 (page_ready_chn2), //rpage_nxt_chn0), not used
.buf_run2 (), //buf_run2),
.buf_wr_chn2 (buf_wr_chn2), // output
.buf_wpage_nxt_chn2 (buf_wpage_nxt_chn2), // output
.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]
.buf_wrun2 (), //buf_wrun2),
.buf_rd_chn2 (buf_rd_chn2), // output
.buf_rpage_nxt_chn2 (rpage_nxt_chn2), // buf_rpage_nxt_chn2), // output
.buf_rdata_chn2 (buf_rdata_chn2), // input[63:0]
.want_rq3 (want_rq3), // input
.need_rq3 (need_rq3), // input
.channel_pgm_en3 (channel_pgm_en3), // output reg
.seq_done3 (seq_done3), // output
.page_nxt_chn3 (page_ready_chn3), //rpage_nxt_chn0), not used
.buf_run3 (), //buf_run3),
.buf_wr_chn3 (buf_wr_chn3), // output
.buf_wpage_nxt_chn3 (buf_wpage_nxt_chn3), // output
.buf_wdata_chn3 (buf_wdata_chn3), // output[63:0]
.buf_wrun3 (), //buf_wrun3),
.buf_rd_chn3 (buf_rd_chn3), // output
.buf_rpage_nxt_chn3 (rpage_nxt_chn3), // buf_rpage_nxt_chn3), // output
.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]
.want_rq4 (want_rq4), // input
.need_rq4 (need_rq4), // input
.channel_pgm_en4 (channel_pgm_en4), // output reg
.seq_done4 (seq_done4), // output
.page_nxt_chn4 (page_ready_chn4), //rpage_nxt_chn0), not used
.buf_run4 (), //buf_run4),
.buf_wr_chn4 (buf_wr_chn4), // output
.buf_wpage_nxt_chn4 (buf_wpage_nxt_chn4), // output
.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]