Skip to content

X
x393
Commit 043d4849 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

working on boson implementaion, fixed old bug in python code

parent 28848f7a
Hide whitespace changes
Inline Side-by-side
Showing with 12677 additions and 2794 deletions
cocotb/x393_dut.v
View file @ 043d4849
......@@ -44,7 +44,7 @@
`include "system_defines.vh"
module x393_dut#(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
`include "includes/x393_simulation_parameters.vh"
`include "includes/x393_simulation_parameters.vh" //SuppressThisWarning Veditor UNUSED
)(
output dutm0_aclk,
output reset_out,
......@@ -409,7 +409,7 @@ module x393_dut#(
parameter BLANK_ROWS_BEFORE= 8; // 1; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 8; // 1; //8;
`endif
parameter TRIG_LINES= 8;
parameter TRIG_LINES= 8; //SuppressThisWarning Veditor UNUSED
parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED
parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG // SuppressThisWarning VEditor - not used
`ifdef PF
......@@ -422,21 +422,21 @@ module x393_dut#(
`endif
parameter WOI_MARGINS = 0; // 4;
parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK;
parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK; //SuppressThisWarning Veditor UNUSED
parameter VIRTUAL_HEIGHT= FULL_HEIGHT + BLANK_ROWS_BEFORE + BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED
parameter TRIG_INTERFRAME= 100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED
parameter TRIG_DELAY= 200; /// delay in sensor clock cycles // SuppressThisWarning VEditor - not used
parameter FULL_WIDTH= WOI_WIDTH + WOI_MARGINS;
parameter FULL_HEIGHT= WOI_HEIGHT + WOI_MARGINS;
// localparam SENSOR_MEMORY_WIDTH_BURSTS = (FULL_WIDTH + 15) >> 4;
// localparam SENSOR_MEMORY_MASK = (1 << (FRAME_WIDTH_ROUND_BITS-4)) -1;
// localparam SENSOR_MEMORY_FULL_WIDTH_BURSTS = (SENSOR_MEMORY_WIDTH_BURSTS + SENSOR_MEMORY_MASK) & (~SENSOR_MEMORY_MASK);
// ========================== end of parameters from x353 ===================================
reg [639:0] TEST_TITLE="abcdef"; //SuppressThisWarning VEditor
// Sensor signals - as on sensor pads
`ifdef LWIR
`elsif BOSON
`else // PAR12 od HISPI
wire PX1_MCLK; // input sensor input clock
wire PX1_MRST; // input
wire PX1_ARO; // input
......@@ -485,8 +485,9 @@ module x393_dut#(
wire PX2_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
wire PX3_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
wire PX4_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
`endif
// for LWIR -
`ifdef LWIR
wire LWIR1_SPI_MISO;
wire LWIR1_SPI_MOSI;
wire LWIR1_SPI_CS;
......@@ -550,7 +551,7 @@ module x393_dut#(
wire LWIR4_MIPI_DN; // not implemented
wire LWIR4_MIPI_CLKP; // not implemented
wire LWIR4_MIPI_CLKN; // not implemented
`endif
......@@ -596,8 +597,8 @@ module x393_dut#(
localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock
localparam PIX_CLK_MULT = 11; // scale clock from FPGA to sensor pixel clock
`else
localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock
localparam PIX_CLK_MULT = 1; // scale clock from FPGA to sensor pixel clock
localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock // SuppressThisWarning VEditor - may be unused
localparam PIX_CLK_MULT = 1; // scale clock from FPGA to sensor pixel clock // SuppressThisWarning VEditor - may be unused
`endif
`ifdef HISPI
localparam HISPI_FULL_HEIGHT = FULL_HEIGHT; // >0 - count lines, ==0 - wait for the end of VACT
......@@ -695,6 +696,8 @@ module x393_dut#(
assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor
assign PX4_ARST = sns4_dn[7]; // same as GP[3]
assign PX4_ARO = sns4_dn[5]; // same as GP[1]
`elsif BOSON
`elsif LWIR
// connect LWIR sensor to x393
assign LWIR1_SPI_MOSI = sns1_dn[0];
......@@ -777,7 +780,7 @@ module x393_dut#(
assign sns4_clkn = LWIR4_MIPI_CLKN;
assign sns4_clkp = LWIR4_MIPI_CLKP;
`else
`else // only PAR12
//connect parallel12 sensor to sensor port 1
assign sns1_dp[6:1] = {PX1_D[10], PX1_D[8], PX1_D[6], PX1_D[4], PX1_D[2], PX1_HACT};
assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor
......@@ -1093,6 +1096,11 @@ module x393_dut#(
.sns1_dn (sns1_dn[3:0]), // inout[3:0]
.sns1_dp74 (sns1_dp[7:4]), // inout[3:0]
.sns1_dn74 (sns1_dn[7:4]), // inout[3:0]
`elsif BOSON
.sns1_dp (sns1_dp[3:0]), // inout[3:0]
.sns1_dn (sns1_dn[3:0]), // inout[3:0]
.sns1_dp74 (sns1_dp[7:4]), // inout[3:0]
.sns1_dn74 (sns1_dn[7:4]), // inout[3:0]
`elsif LWIR
.sns1_dp40 (sns1_dp[4:0]), // input[4:0]
.sns1_dn40 (sns1_dn[4:0]), // input[4:0]
......@@ -1116,6 +1124,11 @@ module x393_dut#(
.sns2_dn (sns2_dn[3:0]), // inout[3:0]
.sns2_dp74 (sns2_dp[7:4]), // inout[3:0]
.sns2_dn74 (sns2_dn[7:4]), // inout[3:0]
`elsif BOSON
.sns2_dp (sns2_dp[3:0]), // inout[3:0]
.sns2_dn (sns2_dn[3:0]), // inout[3:0]
.sns2_dp74 (sns2_dp[7:4]), // inout[3:0]
.sns2_dn74 (sns2_dn[7:4]), // inout[3:0]
`elsif LWIR
.sns2_dp40 (sns2_dp[4:0]), // input[4:0]
.sns2_dn40 (sns2_dn[4:0]), // input[4:0]
......@@ -1141,6 +1154,11 @@ module x393_dut#(
.sns3_dn (sns3_dn[3:0]), // inout[3:0]
.sns3_dp74 (sns3_dp[7:4]), // inout[3:0]
.sns3_dn74 (sns3_dn[7:4]), // inout[3:0]
`elsif BOSON
.sns3_dp (sns3_dp[3:0]), // inout[3:0]
.sns3_dn (sns3_dn[3:0]), // inout[3:0]
.sns3_dp74 (sns3_dp[7:4]), // inout[3:0]
.sns3_dn74 (sns3_dn[7:4]), // inout[3:0]
`elsif LWIR
.sns3_dp40 (sns3_dp[4:0]), // input[4:0]
.sns3_dn40 (sns3_dn[4:0]), // input[4:0]
......@@ -1164,6 +1182,11 @@ module x393_dut#(
.sns4_dn (sns4_dn[3:0]), // inout[3:0]
.sns4_dp74 (sns4_dp[7:4]), // inout[3:0]
.sns4_dn74 (sns4_dn[7:4]), // inout[3:0]
`elsif BOSON
.sns4_dp (sns4_dp[3:0]), // inout[3:0]
.sns4_dn (sns4_dn[3:0]), // inout[3:0]
.sns4_dp74 (sns4_dp[7:4]), // inout[3:0]
.sns4_dn74 (sns4_dn[7:4]), // inout[3:0]
`elsif LWIR
.sns4_dp40 (sns4_dp[4:0]), // input[4:0]
.sns4_dn40 (sns4_dn[4:0]), // input[4:0]
......@@ -1705,6 +1728,9 @@ simul_axi_hp_wr #(
);
`endif
`ifdef LWIR
`elsif BOSON
`else // PAR12 od HISPI
simul_clk_mult_div #(
.MULTIPLIER (PIX_CLK_MULT),
.DIVISOR (PIX_CLK_DIV),
......@@ -1744,53 +1770,8 @@ simul_axi_hp_wr #(
.en (1'b1), // input
.clk_out (PX4_MCLK) // output
);
`endif
/*
wire lwir1_miso;
simul_lwir160x120_vospi #(
.DATA_FILE ("/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat"),
.WINDOW_WIDTH (160),
.WINDOW_HEIGHT (120),
.TELEMETRY (2), // 1),
.FRAME_PERIOD (946969),
.FRAME_DELAY (100),
.MS_PERIOD (25) // 1us instead of 1 ms
) simul_lwir160x120_vospi_i (
.mclk (x393_i.ps7_i.SAXIHP0ACLK), // PX1_MCLK), // input temporarily made faster
.mrst ( PX1_MRST), // input
.pwdn (1'b1), // input
.spi_clk ( 1'b0), // input
.spi_cs ( 1'b0), // inout
.spi_miso ( lwir1_miso), // output
.spi_mosi ( 1'bz), // input
.gpio0 (), // inout
.gpio1 (), // inout
.gpio2 (), // inout
.gpio3 (), // inout
.i2c_scl (), // input
.i2c_sda (), // inout
.mipi_dp (), // output
.mipi_dn (), // output
.mipi_clkp (), // output
.mipi_clkn (), // output
.telemetry_rev ( 16'h7654), // input[15:0]
.telemetry_status ( 32'h137f1248), // input[31:0]
.telemetry_srev (64'h0123456789abcdef), // input[63:0]
.telemetry_temp_counts ( 16'd59000), // input[15:0]
.telemetry_temp_kelvin ( 16'd29500), // input[15:0]
.telemetry_temp_last_kelvin ( 16'd29300), // input[15:0]
.telemetry_time_last_ms ( 32'h12345678), // input[31:0]
.telemetry_agc_roi_top ( 16'd0), // input[15:0]
.telemetry_agc_roi_left ( 16'd0), // input[15:0]
.telemetry_agc_roi_bottom ( 16'd119), // input[15:0]
.telemetry_agc_roi_right ( 16'd159), // input[15:0]
.telemetry_agc_high (16'd19200), // input[15:0]
.telemetry_agc_low ( 16'd200), // input[15:0]
.telemetry_video_format (32'haaaa5555) // input[31:0]
);
*/
`ifdef LWIR
simul_lwir160x120_vospi #(
.DATA_FILE (LWIR_DATA_FILE1),
......@@ -1965,6 +1946,187 @@ simul_axi_hp_wr #(
);
`elsif BOSON
wire boson_single = 1;
wire [BOSON_OUT_BITS-1:0] boson_pxd1;
wire [BOSON_OUT_BITS-1:0] boson_pxd2;
wire [BOSON_OUT_BITS-1:0] boson_pxd3;
wire [BOSON_OUT_BITS-1:0] boson_pxd4;
wire boson_pclk1;
wire boson_pclk2;
wire boson_pclk3;
wire boson_pclk4;
wire boson_dvalid1;
wire boson_dvalid2;
wire boson_dvalid3;
wire boson_dvalid4;
wire boson_vsync1;
wire boson_vsync2;
wire boson_vsync3;
wire boson_vsync4;
wire boson_hsync1;
wire boson_hsync2;
wire boson_hsync3;
wire boson_hsync4;
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
.WIDTH (BOSON_WIDTH), // 160), 640),
.HEIGHT (BOSON_HEIGHT), // 120), 513),
.OUT_BITS (BOSON_OUT_BITS), // 16),
.FPS (BOSON_FPS), // 60.0),
.HSW (BOSON_HSW), // 8),
.FP_BP (BOSON_FP_BP), // 22), // 102),
.FP (BOSON_FP), // 12), 52),
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_1_i (
.mrst (sns1_dp[7]), // input
.single (boson_single), // input
.ext_sync (sns1_ctl), // input
.pxd (boson_pxd1), // output[15:0]
.pclk (boson_pclk1), // output
.dvalid (boson_dvalid1), // output
.vsync (boson_vsync1), // output
.hsync (boson_hsync1), // output
.uart_in (sns1_dp[4]), // input sns_txd
.uart_out (sns1_dn[4]) // output sns_rxd
);
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_1_i (
.red (boson_pxd1[ 7:0]), // input[7:0]
.green (boson_pxd1[15:8]), // input[7:0]
.blue (8'h17), // input[7:0]
.hs (boson_hsync1), // input
.vs (boson_vsync1), // input
.de (boson_dvalid1), // input
.pclk (boson_pclk1), // input
.dp (sns1_dp[2:0]), // output[2:0]
.dn (sns1_dn[2:0]), // output[2:0]
.clkp (sns1_clkp), // output
.clkn (sns1_clkn) // output
);
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
.WIDTH (BOSON_WIDTH), // 160), 640),
.HEIGHT (BOSON_HEIGHT), // 120), 513),
.OUT_BITS (BOSON_OUT_BITS), // 16),
.FPS (BOSON_FPS), // 60.0),
.HSW (BOSON_HSW), // 8),
.FP_BP (BOSON_FP_BP), // 22), // 102),
.FP (BOSON_FP), // 12), 52),
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_2_i (
.mrst (sns2_dp[7]), // input
.single (boson_single), // input
.ext_sync (sns2_ctl), // input
.pxd (boson_pxd2), // output[15:0]
.pclk (boson_pclk2), // output
.dvalid (boson_dvalid2), // output
.vsync (boson_vsync2), // output
.hsync (boson_hsync2), // output
.uart_in (sns2_dp[4]), // input sns_txd
.uart_out (sns2_dn[4]) // output sns_rxd
);
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_2_i (
.red (boson_pxd2[ 7:0]), // input[7:0]
.green (boson_pxd2[15:8]), // input[7:0]
.blue (8'h17), // input[7:0]
.hs (boson_hsync2), // input
.vs (boson_vsync2), // input
.de (boson_dvalid2), // input
.pclk (boson_pclk2), // input
.dp (sns2_dp[2:0]), // output[2:0]
.dn (sns2_dn[2:0]), // output[2:0]
.clkp (sns2_clkp), // output
.clkn (sns2_clkn) // output
);
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
.WIDTH (BOSON_WIDTH), // 160), 640),
.HEIGHT (BOSON_HEIGHT), // 120), 513),
.OUT_BITS (BOSON_OUT_BITS), // 16),
.FPS (BOSON_FPS), // 60.0),
.HSW (BOSON_HSW), // 8),
.FP_BP (BOSON_FP_BP), // 22), // 102),
.FP (BOSON_FP), // 12), 52),
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_3_i (
.mrst (sns3_dp[7]), // input
.single (boson_single), // input
.ext_sync (sns3_ctl), // input
.pxd (boson_pxd3), // output[15:0]
.pclk (boson_pclk3), // output
.dvalid (boson_dvalid3), // output
.vsync (boson_vsync3), // output
.hsync (boson_hsync3), // output
.uart_in (sns3_dp[4]), // input sns_txd
.uart_out (sns3_dn[4]) // output sns_rxd
);
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_3_i (
.red (boson_pxd3[ 7:0]), // input[7:0]
.green (boson_pxd3[15:8]), // input[7:0]
.blue (8'h17), // input[7:0]
.hs (boson_hsync3), // input
.vs (boson_vsync3), // input
.de (boson_dvalid3), // input
.pclk (boson_pclk3), // input
.dp (sns3_dp[2:0]), // output[2:0]
.dn (sns3_dn[2:0]), // output[2:0]
.clkp (sns3_clkp), // output
.clkn (sns3_clkn) // output
);
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
.WIDTH (BOSON_WIDTH), // 160), 640),
.HEIGHT (BOSON_HEIGHT), // 120), 513),
.OUT_BITS (BOSON_OUT_BITS), // 16),
.FPS (BOSON_FPS), // 60.0),
.HSW (BOSON_HSW), // 8),
.FP_BP (BOSON_FP_BP), // 22), // 102),
.FP (BOSON_FP), // 12), 52),
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_4_i (
.mrst (sns4_dp[7]), // input
.single (boson_single), // input
.ext_sync (sns4_ctl), // input
.pxd (boson_pxd4), // output[15:0]
.pclk (boson_pclk4), // output
.dvalid (boson_dvalid4), // output
.vsync (boson_vsync4), // output
.hsync (boson_hsync4), // output
.uart_in (sns4_dp[4]), // input sns_txd
.uart_out (sns4_dn[4]) // output sns_rxd
);
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_4_i (
.red (boson_pxd4[ 7:0]), // input[7:0]
.green (boson_pxd4[15:8]), // input[7:0]
.blue (8'h17), // input[7:0]
.hs (boson_hsync4), // input
.vs (boson_vsync4), // input
.de (boson_dvalid4), // input
.pclk (boson_pclk4), // input
.dp (sns4_dp[2:0]), // output[2:0]
.dn (sns4_dn[2:0]), // output[2:0]
.clkp (sns4_clkp), // output
.clkn (sns4_clkn) // output
);
`else
......
fpga_version.vh
View file @ 043d4849
......@@ -35,7 +35,9 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930139; // Adding pullup on senspgm
parameter FPGA_VERSION = 32'h03930200; // Initial Boson implementation
//BOSON
// parameter FPGA_VERSION = 32'h03930139; // Adding pullup on senspgm
// parameter FPGA_VERSION = 32'h03930138; // Fixing output trigger in free running mode
// parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output
// parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
......
includes/x393_parameters.vh
View file @ 043d4849
......@@ -429,6 +429,8 @@
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2,
parameter SENSI2C_STATUS = 'h1,
......@@ -500,8 +502,16 @@
//`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
//`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
//`elsif BOSON
parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7
//`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
......@@ -589,15 +599,15 @@
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`endif
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`ifdef SIMULATION
`ifdef SIMULATION
parameter VOSPI_MRST_MS = 1, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 5, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 3, // Wait to tymeout SPI when needed to re-sync
`else
`else
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`endif
`endif
//`else
//sensor_fifo parameters (for parallel12)
......@@ -658,6 +668,7 @@
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
// ALL PARAMETERS HERE SHOULD BE DEFINED (for use in C-generator)
`define TWEAKING_IOSTANDARD
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
......@@ -668,12 +679,18 @@
`ifdef TWEAKING_IOSTANDARD
parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
// parameter PXD_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
// parameter SENSI2C_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
`else
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`endif
`elsif BOSON
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
......@@ -686,17 +703,15 @@
`endif
`ifdef TWEAKING_IOSTANDARD
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
// parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
// parameter HISPI_IOSTANDARD = "PPDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
`else
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
`ifdef TWEAKING_IOSTANDARD
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
`else
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
......
includes/x393_simulation_parameters.vh
View file @ 043d4849
......@@ -53,8 +53,8 @@
parameter FCLK0_PERIOD = 41.667, // 24MHz
`endif
parameter FCLK1_PERIOD = 0.0,
`ifdef LWIR
// for python (export to C header) all parameters should be defined
//`ifdef LWIR
parameter LWIR_DATA_FILE1 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE2 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE3 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
......@@ -83,7 +83,17 @@
parameter LWIR_GPIO_IN = 4'b0000,
`endif
parameter BOSON_DATA_FILE = "/input_data/pattern_160_120_16.dat",
parameter BOSON_WIDTH = 160, // 640
parameter BOSON_HEIGHT = 120, // 513
parameter BOSON_OUT_BITS = 16, // 16
parameter BOSON_FPS = 60.0, // 60.0
parameter BOSON_HSW = 8, // 8
parameter BOSON_FP_BP = 22, // 102 (FP+BP)
parameter BOSON_FP = 12, // 52
parameter BOSON_VSW = 7, // 87, // in scan lines
//`endif
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
......@@ -192,9 +202,16 @@
parameter HISTOGRAM_START_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
`ifdef LWIR
parameter WOI_WIDTH= 160,
parameter WOI_HEIGHT= 122,
`elsif BOSON
parameter WOI_WIDTH= 160, // 640,
parameter WOI_HEIGHT= 120, // 513,
`else
parameter WOI_WIDTH= 256, // 512, // 256, //1040, // 64,
parameter WOI_HEIGHT= 256, // 512, // 256, // 64, // 32,
`endif
parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
parameter SENSOR_PRIORITY = 1000
input_data/pattern_160_120_14.dat
View file @ 043d4849
//
// autogenerated from /data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.tiff
// autogenerated from ../input_data/pattern_160_120_14.tiff
// GENERATOR = ./x393_tiff_verilog.py
// WIDTH = 160
// HEIGHT = 120
//
160e 3189 3348 3256 3201 31ef 3258 324e 32e9 333d 3365 3427 3690 2714 13d1 0e40 11f6 3293 334b 31f1 31d0 31e8 3210 31bb 3173 31ec 3255 3264 3301 33d1 3568 16c0 0dd6 103b 1092 10fa 10e2 115e 1206 11f6 1123 10d7 0ff5 10e3 2c2c 3435 3288 33c3 3738 252f 0dcf 0dc3 0e3e 0eab 0f5b 104b 1008 0ebb 0cd8 0b4f 0f2c 2a2e 3436 3257 3241 31f4 321c 3376 340f 207a 093e 0c08 0ec9 0f59 0fac 0fb8 102f 0e98 27f6 3774 34b2 33be 3369 3325 3349 33f8 34eb 3591 35d4 35f8 362f 366f 3610 35c1 3555 34b1 3452 3429 33d1 33a5 32a8 326d 321a 322b 356e 1fed 09cc 0d1a 0d85 0d33 0dca 0e00 0e5e 0db4 0ed4 0ec7 0e85 0e54 0dfe 0e97 0e35 0e42 0e84 0f0b 1005 100b 10d7 1104 112c 125b 283b 37fd 34f5 3507 34f9 354c 34ee 3454 343d 3432 3483 34d9 34c3 3505 34fb 3458 3437 33f4 3443 3403 33ad 3308 1ffc 0d7a 073e 09b4 0c84 0c16 0b3e 0be4
31bf 338b 329a 32f6 3291 329b 32c0 3300 3379 33a2 341d 363c 21a5 0fbb 0f56 0fbf 0e6c 2a60 35fe 3208 31a3 31b9 31ff 316b 318f 323c 3218 31c5 3230 347b 2f16 0df8 0ef1 1035 1042 0ffc 1028 1038 10a3 115b 10c8 1022 0f16 0b78 1eeb 37bd 364d 3456 21fd 0d92 0d53 0eac 0f8c 0fc1 0fb5 0f6c 0ea7 0cd1 0b4f 0d9b 2c75 3440 31cc 324a 3242 3280 3288 3287 329b 35d3 223f 09b4 0ea6 1048 10fa 1141 0fee 1185 3265 36a2 34a1 3464 33d9 3394 33a2 345e 34ee 358f 35c7 364a 375e 38d5 3907 385b 365e 352f 3503 3483 3407 33bd 3344 32bd 32eb 3249 3533 24d2 0a3c 0c79 0dc0 0e67 0ee4 0f46 0f25 0f4c 0f85 0e7d 0e98 0d7a 0d89 0e5a 0edb 0f35 0fc2 0fa5 1081 1059 10b6 1124 10d6 1141 15b1 33d9 3766 35e0 3564 356c 34c7 34ac 3484 34a5 34a2 34de 350b 34cc 3505 345c 343c 3417 3411 3416 339f 33c0 353e 317b 2298 0cc7 0946 0be2 0c17 0c41
......
input_data/pattern_160_120_14.dat0 0 → 100644
View file @ 043d4849
//
// autogenerated from /data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.tiff
//
160e 3189 3348 3256 3201 31ef 3258 324e 32e9 333d 3365 3427 3690 2714 13d1 0e40 11f6 3293 334b 31f1 31d0 31e8 3210 31bb 3173 31ec 3255 3264 3301 33d1 3568 16c0 0dd6 103b 1092 10fa 10e2 115e 1206 11f6 1123 10d7 0ff5 10e3 2c2c 3435 3288 33c3 3738 252f 0dcf 0dc3 0e3e 0eab 0f5b 104b 1008 0ebb 0cd8 0b4f 0f2c 2a2e 3436 3257 3241 31f4 321c 3376 340f 207a 093e 0c08 0ec9 0f59 0fac 0fb8 102f 0e98 27f6 3774 34b2 33be 3369 3325 3349 33f8 34eb 3591 35d4 35f8 362f 366f 3610 35c1 3555 34b1 3452 3429 33d1 33a5 32a8 326d 321a 322b 356e 1fed 09cc 0d1a 0d85 0d33 0dca 0e00 0e5e 0db4 0ed4 0ec7 0e85 0e54 0dfe 0e97 0e35 0e42 0e84 0f0b 1005 100b 10d7 1104 112c 125b 283b 37fd 34f5 3507 34f9 354c 34ee 3454 343d 3432 3483 34d9 34c3 3505 34fb 3458 3437 33f4 3443 3403 33ad 3308 1ffc 0d7a 073e 09b4 0c84 0c16 0b3e 0be4
31bf 338b 329a 32f6 3291 329b 32c0 3300 3379 33a2 341d 363c 21a5 0fbb 0f56 0fbf 0e6c 2a60 35fe 3208 31a3 31b9 31ff 316b 318f 323c 3218 31c5 3230 347b 2f16 0df8 0ef1 1035 1042 0ffc 1028 1038 10a3 115b 10c8 1022 0f16 0b78 1eeb 37bd 364d 3456 21fd 0d92 0d53 0eac 0f8c 0fc1 0fb5 0f6c 0ea7 0cd1 0b4f 0d9b 2c75 3440 31cc 324a 3242 3280 3288 3287 329b 35d3 223f 09b4 0ea6 1048 10fa 1141 0fee 1185 3265 36a2 34a1 3464 33d9 3394 33a2 345e 34ee 358f 35c7 364a 375e 38d5 3907 385b 365e 352f 3503 3483 3407 33bd 3344 32bd 32eb 3249 3533 24d2 0a3c 0c79 0dc0 0e67 0ee4 0f46 0f25 0f4c 0f85 0e7d 0e98 0d7a 0d89 0e5a 0edb 0f35 0fc2 0fa5 1081 1059 10b6 1124 10d6 1141 15b1 33d9 3766 35e0 3564 356c 34c7 34ac 3484 34a5 34a2 34de 350b 34cc 3505 345c 343c 3417 3411 3416 339f 33c0 353e 317b 2298 0cc7 0946 0be2 0c17 0c41
332f 3299 32af 330c 32f1 3301 3348 3347 33b4 3370 3607 27fe 0d4d 0f79 107c 0fb3 0e4e 18cd 35f5 33be 325b 31cb 31a3 317a 321d 3292 3295 3210 3208 3666 1f5a 0c62 0ebe 0efd 0e99 0e97 0ebe 0fba 0f21 0fd1 106e 0ea9 0f2e 16fa 2532 2dca 24ee 155b 0c89 0e14 0f1a 0fba 0f88 0fc5 0f1b 0e6b 0d9a 0c9a 0ad8 2603 3551 3175 315c 31c0 31fa 3220 324c 322e 32a8 3345 3602 198e 0b92 1037 1040 106a 0d3f 1fa2 3790 347f 33df 344d 3421 33d8 33ed 34a2 352e 3580 37f0 39d3 3321 2b5f 296f 2d11 348f 3841 35f4 34c6 341d 33fc 338b 3300 32b5 3205 3495 2446 0a9f 0ccb 0d21 0ddb 0e47 0e4f 0ee2 0e84 0e6a 0e07 0ee1 0f0c 0e5a 0e49 0e0e 0e8e 0f0e 0f23 0ef7 1011 10c7 1128 1134 119b 1172 281c 397d 35ed 355d 35a0 356c 34f1 34c7 34fa 3510 354a 3566 3521 356b 3485 33ff 33f4 339c 3359 33b1 3335 32ed 3346 357f 2e1e 102a 0948 0bb4 0c01
328f 32f6 3306 32cb 330b 331e 3342 334e 338b 33d1 347d 13fb 0d65 0eeb 0efe 0ef6 0e44 0f47 2486 3777 33fb 32dc 323c 31dc 31f1 3240 3294 3301 35f1 2dc2 0f36 0d4f 0dfc 0eb4 0da7 0d91 0d07 0e12 0dd9 0e23 0c66 1ae0 2f8e 3755 3782 1541 0d0f 0e0e 0f4e 0f5c 1010 1005 0f8f 0faf 0f7e 0f84 0e77 0c87 13b6 34f9 32fa 32b4 32e8 32f5 32f1 32c5 333c 32ff 32dc 3310 3561 2e86 0d3b 0f51 0fd8 0c2d 15a9 33f7 34b8 3373 3383 337c 3408 3411 3426 34c6 353d 3836 33db 200a 1412 120a 11f7 12a8 16fd 2414 35b1 36d2 34e6 3499 33f2 3399 3346 3289 3597 1f4c 0a2a 0cb6 0d4d 0e28 0d4a 0d3c 0dc1 0d0e 0d6a 0d87 0d44 0e84 0e67 0ddb 0d4e 0c9e 0d9d 0e0c 0dfd 0ef4 1004 1007 1009 108f 1068 1e42 38c0 35e8 3553 34f0 3447 33f5 33eb 3445 3517 353e 3541 3522 3544 34bb 347d 3435 33ad 3391 3355 3385 3349 32ec 31c0 346e 2bdd 0aea 0a10 0b8e
3239 327f 32ce 32eb 332b 3360 337c 334b 334c 3519 2c2c 0cb5 0eda 0fcf 1058 1035 0f10 0fad 1074 258d 366e 3637 33a5 32f4 32f1 3353 3481 3777 2e84 1315 0d08 0ea7 0f34 0ff5 0e86 0d92 0d30 0d6f 0dac 0be4 1faf 36cb 366d 3499 3723 1d06 0bec 10ec 10a5 10a7 112e 1013 0fc1 0f59 0ed5 0ed3 0f2c 0c47 2239 3680 331f 33c5 3433 342c 3438 33f8 33a2 33e3 3397 341c 34e2 37b2 15d4 0c63 0e0a 19fd 3262 3629 33ff 33e5 33a2 33fe 3454 344f 347c 34b8 37f2 3039 1559 0f67 1192 11b0 1220 1296 11b9 108f 1b2a 3484 364b 3403 3379 336a 3409 341c 360d 1563 0bd9 0dc6 0f01 0f0e 0f3b 0e96 0d82 0d10 0d4c 0e58 0d45 0b8c 0a34 09c1 0a32 0c15 0e40 0eb5 0e85 0f99 1055 1122 11cb 1101 0fec 19a0 3755 35be 3470 33b0 3383 33c4 3389 33b6 348c 34ea 34da 34e1 34fd 34da 348f 3403 3349 3331 32f6 330d 32a5 31fa 3193 316c 3515 1bfd 0881 0bd6
3232 32b9 32f8 32f1 3339 3379 3365 331e 3302 35ab 2398 0c05 0f35 10b7 10cc 0fa3 0f82 0fd0 0f5e 0ff9 1bb2 2d3b 352b 3700 3784 36c2 32a9 248c 11a5 0e17 0eef 0f56 0ef1 0e8f 0d3f 0d64 0db2 0e85 0ba0 1ab7 35b7 33aa 32d4 32bf 339b 2cd1 0ccb 0f8a 1032 0fa6 0f74 0f10 0ec6 0ec6 0ec6 0eb1 0eab 101e 30a3 35ef 3464 3402 33dd 3408 33c8 3400 342a 34a9 34d9 3608 38a8 3a59 231c 1c6a 2b33 36cd 3649 34d9 3467 3444 33f3 3440 348f 34a3 3541 36fd 3476 161c 1007 11a3 12b8 1324 123b 11ce 11b9 1250 11ba 1d5a 3720 3558 33b1 337d 349d 37b2 2c90 0cf7 0ccd 0e22 0e71 0eba 0fa7 0ffe 0f56 0e32 0ce2 0b3c 1107 1c53 222a 22df 1db1 119b 0adb 0d26 0ecc 0f3d 0fa8 10db 118f 1145 1004 191d 3740 3500 340f 3456 3468 3405 33d1 343a 34ac 350f 350d 3501 353c 34d6 343a 33d4 3349 3302 325b 3224 31e5 3124 312e 30df 32af 2c7e 0a80 0a64
32ce 32eb 32f0 3339 335d 335c 3307 331d 331b 359c 20ce 0bd2 0ea5 0fce 102c 0f1d 0ec2 0e69 0de4 0ec8 0f52 1133 16d5 1cd6 1e4c 1a7b 13eb 0ed8 0edf 0e27 0e75 0ef5 0f19 0e68 0e11 0d4f 0d1b 0db5 0e10 2fe0 33fd 3192 3186 31e5 32ae 35fa 20d2 0bff 0ffd 0fa3 103e 0f64 0f00 0f1d 0efb 0eb4 0d7c 2228 37e5 34c7 3481 33f1 33b1 33b7 3433 34c3 3567 351d 3858 36a8 2966 1c28 2e99 39fd 37d4 353b 349d 3429 33db 33d2 33cb 3446 344e 3462 352f 3901 210e 0f48 1252 1203 11e7 11c8 11d6 1199 10fd 1114 1191 11f1 2b5c 3839 34a3 34ab 371d 36ee 1780 0cb2 0dae 0df6 0e60 0ec9 0ec3 0e7e 0f63 0dce 0e55 2322 3413 378d 36dc 364a 3717 346b 22a6 0b70 0bfb 0f45 0fbb 111d 115c 1155 1085 1e9c 383f 3462 33e5 34a2 34f5 34a8 342d 3479 34cc 35ac 35d2 35e3 359d 3526 34f8 349e 3427 3360 329f 325d 3224 3186 3114 30c5 318d 32a1 10c9 0a4d
3311 32f5 32c2 3311 3391 334a 3328 337d 333d 35d9 2595 0bd3 0ec0 0fb3 1088 1048 1180 1172 0f76 0f9f 0f68 0f82 0f13 0ef7 0f2e 0f02 0f0e 0e94 0e35 0e68 0f76 0f28 0ef3 0fba 0f0a 0de6 0d83 0c5c 1a4c 355e 31b1 3186 314b 3250 33a8 353a 371a 1f1e 0d62 0ea1 1084 1150 10f6 0f66 0e1d 0c74 1d83 36da 3614 34f6 3464 33ee 3393 336c 342f 3546 35d6 3895 2f76 186d 0fc3 0dd3 25ee 3899 345a 33be 33a1 339d 3344 3397 340f 33fd 3433 3496 363f 3451 1319 0fd1 10ae 1027 1009 1074 109a 10ae 1076 10d1 1045 1019 1cdf 3948 3733 397b 368c 1cf3 0e50 0ec7 0e7b 0e88 0f52 0eb4 0e58 0e23 0d7f 0ed4 2ba0 37e1 34f6 33f9 3380 3387 336d 346e 3776 2a66 0d1d 0e23 1012 1159 1244 1233 1054 2afb 382e 34f9 3404 34b2 3502 34eb 349a 346d 34a6 3555 35b3 376b 3811 37ac 36de 35cf 34b6 343b 3315 327f 3232 320a 315c 30ce 31fc 34a1 12ff 09b6
3342 32e1 32b0 32d6 333c 337d 3380 3330 338a 355c 2dd0 0cb7 0edb 0fcf 110e 10ef 1069 103e 10b6 0fdf 0fbb 1015 1022 0f45 0ede 0ef4 0eac 0dbc 0eb3 1026 0ffb 0fe2 0f2b 0f27 0ed9 0dfe 0dfb 0cca 2619 35ac 326f 324c 32b5 337b 34c6 35ba 36b5 37ea 277b 136d 0d3c 0be6 0c1a 0cc9 12e9 25af 3610 3555 349a 34b9 3485 3449 3419 33da 345c 3526 3853 2ebe 1311 100b 1136 0f74 1992 36f3 3440 33a5 33c5 33ff 33cb 33ef 3435 33f8 345b 3460 3857 27a4 0e60 1045 106b 0fb5 0fa3 107a 1089 1010 10a5 10b5 0f93 0f11 175e 37bd 37fa 2c0c 17f8 0eb6 1049 0f94 0e71 0ee8 0f69 0e1d 0e29 0e0e 0cba 26b3 37f1 33b3 32d5 3272 326a 3288 3345 33a1 3474 3902 239c 0c86 0fd9 0faf 111a 107d 171b 36f8 3641 352d 3428 3489 352a 35c9 3597 34fa 34d5 3655 3825 33f7 2eba 2cf8 313d 3776 3810 356f 3436 333f 32e8 32d9 31e8 3187 3248 3461 11d0 0a97
32de 32cf 32e5 32df 3327 332a 333c 339e 33c6 3461 35b9 1540 0d23 101e 1029 1005 0f9a 104c 109d 1033 0f6c 103c 0fc3 0efe 0f22 0ee0 0f61 0f82 0fb5 1075 1051 10e8 10cb 0f6d 0f04 0e0c 0ee0 0dbd 2b8b 3589 332c 330e 3364 3414 3499 353f 355e 3514 368f 346f 2d3c 2663 2579 2bec 3420 3716 34ed 33ed 33fc 3480 3465 34eb 34c9 3465 346d 3611 358b 15d5 0fdb 1237 11a3 1169 129e 2b3f 3922 34c1 343d 33dc 343d 341f 3436 33e1 33dd 35bf 35b0 1550 0efe 0fa7 10f6 10b0 0fe9 105c 0f7e 1099 0fea 0eee 1988 2a0d 3442 2458 1691 125d 10e0 102b 0fcd 103b 1015 1003 0fc4 0f67 0f54 0e1c 178a 3681 34cc 33f0 3348 334a 333a 3385 33b6 3433 351a 36a6 3559 123b 0df8 0ef3 1007 1145 2e90 37eb 35ed 34fb 348e 3432 34d8 35d2 3646 360a 3894 3141 1db9 13c3 11f6 12c1 13ee 1afc 2afb 386e 3667 3477 339a 330f 327c 321d 3314 3202 0d77 0bc5
32cc 330f 330d 32ee 3304 3311 333e 33a8 33ee 3438 3621 2927 0b99 0ef3 1079 113b 10d9 114f 10de 104d 0fbf 0f8a 0f8c 0fdf 0f33 0ec2 0e90 0f85 1070 1107 106b 0faa 0ef3 0eb2 0e8e 0dfb 0f8a 0de6 2b14 3539 336d 338a 333c 33f0 3494 34b1 3486 3484 3446 3464 3614 36ef 36a2 3698 358d 350f 34ec 34c7 34e0 34ca 34c6 352f 34e2 34eb 3554 382e 2551 0f3f 1263 128e 1235 11fa 12be 18af 3410 393a 354e 34bc 34c1 34df 3485 3414 35b1 37e8 1ef3 0f20 110a 1112 1168 1075 0fa2 0f98 0f7c 0f72 0eed 253e 37f9 3861 39fb 21d1 0e2b 111d 1187 1159 1112 10df 109f 0fcc 0f84 0fda 0f85 0eb5 27e3 37c4 347c 3489 3458 3424 3424 342b 344f 348d 34ef 357b 3917 1e4a 0b26 0d51 1313 2dcc 38f0 367d 3597 34ba 34aa 3498 34c0 353e 3681 3953 2e5f 12cb 0e58 10e8 11c8 1205 1222 115e 12cf 2499 38bf 3561 3400 3334 330a 3239 35ab 2882 0a52 0d0e
3317 334f 333f 3311 3399 337f 3373 3400 33fc 345f 3483 36ec 20f8 0b95 0f39 10a3 10a2 10b3 0f75 0f10 0f2b 0e61 0f46 0f43 0f08 0ee4 0f03 0f7f 1074 1076 101d 107d 1066 108e 1009 0ee8 0f26 0e0e 26be 374e 33d5 33fa 33a0 33d1 3445 340a 3403 341d 3404 343b 3475 34af 350c 3597 35e6 3601 35ac 3514 352b 3540 354d 3571 353c 34eb 358a 3780 18e1 108e 1281 12ed 1388 129b 1269 137d 1a23 30c9 3a5d 3913 3779 3720 37b6 394c 35dd 1f15 0e26 0fd7 10ef 115b 116d 10ea 0ffd 0f0d 0f48 0d74 2664 38ce 34f4 3430 36ca 2e38 0edd 10be 10a5 11fd 11e1 107d 10ba 0feb 1031 1016 0f4f 1354 33d8 35f4 3494 34b1 34c3 3499 34f3 348c 34b4 34ba 3522 3773 3acf 28ca 131d 2295 3461 3940 3686 3624 358d 34fa 34b4 3461 3479 34f6 375f 31ce 12d4 0ee8 1150 1196 11a3 11e3 1229 1190 12b3 1370 2a60 3846 3435 33e8 3370 3448 36bf 1651 0b64 0daf
3372 3367 3353 335e 33b6 3396 33a9 3401 3418 344f 34d8 3586 36ff 2392 0e86 0d1c 0e87 0f5e 0f1d 0fb1 0f5a 0f74 0f3a 0f67 1087 105d 0fc0 0f82 0f62 0fe8 1049 111c 1045 1065 0ff3 0f45 0e8b 0f8b 1d27 3858 34b6 343f 33bc 33fb 3416 340e 339b 33c6 342e 34af 3505 3549 35c3 362c 3625 3678 35f5 35c9 3524 34b6 34ec 34ff 3568 34d4 352c 34b5 1311 1103 1247 119a 12e6 12ac 11cb 1209 1343 15e9 2269 2ee7 3415 3490 31a5 264e 17a0 104a 0f17 0f98 0f98 101a 10c2 1073 1008 0f5b 0dda 1b7d 3848 34b6 3398 33b5 33fe 366f 1b93 0c59 10b3 1134 11ea 120f 1105 1158 1206 115b 0e62 2451 38ac 3587 3557 352b 3508 355a 359d 3553 3524 3609 38b5 3242 23e5 28de 3878 392a 3736 361f 3586 3503 34d7 34e9 3472 3435 3436 34fa 37b8 1b81 0e2d 11d0 1289 1285 124f 1297 11e0 1189 11a4 124f 18bd 365b 35f4 343b 34d9 3930 24ea 0bb5 0d9d 0e12
33b4 333d 3330 337a 33a5 33b1 33dc 33ff 345c 34a7 34c8 34bd 3565 37ac 307a 209f 12b5 0bbe 0edf 0ff8 0eff 0ec7 0f60 1030 1000 0f5c 0f88 0f0d 0f32 0f8f 0f93 0f41 0e46 0dc7 0e96 0e66 0ebf 1052 13db 3293 3777 3416 33f7 3421 3423 344e 344a 3485 34b9 3596 363c 3673 36dd 36d9 36d7 3657 365b 35da 354d 34fe 356a 354d 35b9 357f 35c5 3465 1228 1082 11df 126f 125d 12e0 1330 1323 12ac 1338 129b 147a 1606 1623 1448 1228 11b0 1162 10f9 1140 108c 0fba 100d 1012 1008 0fed 0ef6 2db7 366c 3368 334e 3341 3350 34c9 32f8 14c3 0c7c 10cb 11a0 1248 11d8 1188 1107 1009 1f7e 3897 3717 363b 3627 3610 35f4 35c2 35ef 364b 3711 3838 238b 114e 0deb 1f3d 39ec 3552 3596 3525 34bb 34a8 34aa 3521 34dd 3493 342a 36f1 3158 0ef1 1041 1157 1120 1173 11d9 11c9 11c1 1161 111b 0ffd 1175 2e62 3a31 385f 392c 27d6 0f17 0ea0 0eb9 0e9a
3367 337a 3381 3358 33b2 339e 33ef 3464 34ab 346e 3459 3487 351e 356e 36a3 3806 33e6 2096 0bc1 0d6f 0e21 0eb2 0fd2 10c6 0fbd 0f47 0fc1 0f6f 0f80 0fca 0f16 0de9 0d03 0dd7 0d36 0d96 0dbe 0ecd 10aa 1e51 385d 35d3 345a 351c 353a 35a8 35e4 35b7 35fc 3692 36a4 36b5 36e0 3703 369b 3644 3649 359d 35b4 35b3 3556 35a0 356d 3593 35c7 361e 1534 0ec1 114b 11af 1271 11d9 119a 1148 1190 1221 11a8 12f6 11f3 1316 1230 118b 122c 11a0 10e2 107d 1063 10ae 0fed 0f62 0ef4 0e56 1482 3598 34b1 3360 32e5 3350 33a3 3482 3641 32e7 1be6 0ebf 0d83 0dd2 0d76 0d6d 1278 25d0 3931 3879 373d 3693 3636 361d 365d 35ff 36a5 3707 38d2 1fd3 0f3a 103a 1078 1798 3681 35a3 3498 3467 3465 34b1 34ab 3510 34f5 347d 34a4 3981 2345 0d7c 1016 1047 115d 1191 1156 11f6 11a3 1174 10dd 0d5d 0ed7 2873 3b4c 3170 1e7c 0efc 0f0e 1001 1095 0f63
336e 3322 3390 3387 3352 33d8 33d7 33d0 3406 343a 3465 3484 34cd 34b0 348f 342c 34ac 36f2 24ca 0b61 0ea0 0f3d 0fe7 0f90 0f97 0f95 0fc7 0fa6 1097 10d5 100d 0f4d 0fa1 1030 0ebb 0ea2 0ead 0fca 1055 1101 220c 37b1 37fe 3675 35db 3605 360c 35b5 3631 3678 361d 3601 3632 35fc 3597 35b2 3531 351f 35a8 35be 358e 3551 3509 34fc 34b1 378f 1dab 0e0a 10dc 1177 122c 11fb 118f 1160 11d0 12e2 1236 1284 1270 1112 109f 0fbd 0fe7 1056 10cc 1101 11b7 11f2 1114 1005 0e93 0d38 1ac9 374a 33c3 3327 3319 330f 339b 3487 34b7 35e0 377c 2ee8 2241 1be3 1d01 2574 32a3 3908 36d0 3716 36a5 364b 362e 362d 366c 366a 36ba 3a25 268f 0f70 111f 11e3 1170 10b0 28ac 3855 3382 3322 3301 337d 33a1 3434 34ca 34bf 370a 33a4 11e9 0e7c 1074 10ca 1152 1135 111a 11bc 1157 0eaf 1147 21fd 30d5 308a 1853 1182 0ef7 0f7b 0ea9 0efd 1088 0fe0
337d 3379 33ae 338a 33e0 342e 33f1 33ed 340d 3427 3445 345c 341d 33f6 33e1 335b 3384 3390 373e 2020 0b8c 0e9b 0f21 0f4d 0f65 0f56 0f58 0fd8 108b 1129 10ab 11b5 118d 110b 1194 1174 108b 119b 10b2 10d9 11c5 1d8b 3108 3944 3956 3744 3679 3675 372c 36e8 366b 366b 3613 35c4 3562 3560 34fe 3524 3539 3548 355a 354e 351f 34af 34c4 3713 2e54 0eab 10cc 122f 115e 1203 12e3 129b 120a 1181 1112 1115 1144 110e 109e 104d 102d 0fb3 116a 1143 1135 117f 116d 10dd 0fea 0ed5 1dcc 3724 3363 3377 3387 3376 33c6 3431 3509 3555 35cc 3771 38a4 381d 3842 3858 3672 34f2 3572 360d 3617 366d 36c0 3704 36cb 36ff 3857 359f 141a 1131 11fe 12cb 11d1 1110 152f 3062 37c0 340e 335e 33ea 345a 3455 3501 3767 3776 1a66 0d42 0f38 106d 1139 1113 10c9 1065 116b 0e40 161a 30d9 39fd 38eb 3511 1199 0ef4 1030 0fe4 0f39 0fb0 1005 0eae
33d0 340a 33d0 3468 347f 3455 3420 342a 33e2 33ed 340e 3435 3419 33de 33bf 33b1 3380 335d 34d0 33a3 10d7 0ce1 0e50 0e8d 0f53 0fa3 0fc9 1050 10d3 1180 1135 122b 1239 1298 1208 10de 1135 1145 1200 11f1 1172 1239 1565 1ec5 2c62 3904 38d0 371d 374a 3728 368f 35e0 35bd 3561 350a 3508 3528 34f2 34e8 34f7 3563 3554 355e 35a0 3653 3710 3948 1f3f 0e80 11db 1231 1207 12dd 1297 12dc 12b9 12e6 1279 122a 129f 11d1 120d 114a 1133 11a7 1164 1081 105b 100c 0fb0 0f57 0ef7 1b5e 36f0 336d 3365 33fb 3410 3429 3497 3535 355a 3591 35e9 3643 366d 36a0 3628 3636 3626 359b 35c2 357c 3579 35bc 3610 36c6 3644 39b5 2917 0fe5 1218 11fc 12f3 135e 1231 1250 16cd 2ecf 38f7 37f3 3735 3741 3821 39ad 33a5 1b13 0c92 0fae 1024 1108 1158 1123 114d 1065 0fa6 1433 3460 3878 35ad 3588 3877 1cff 0cd2 10df 1134 110a 1108 109c 1000
33ee 3433 345e 34c3 34ba 348d 34c0 3456 3426 348d 345c 3471 346c 348c 346b 33f7 3368 3338 333e 371c 1fba 0ac5 0dd6 0ec7 0f4a 0fdd 1089 1120 1130 1274 1217 11b1 11ef 11f2 10d4 104b 106b 111b 123e 12b1 11b7 1189 129a 133c 14f9 2124 37cf 392f 377a 3790 3638 3586 3593 354d 3502 3526 353e 356f 3573 3599 3624 35f4 35e2 3645 36a7 36d6 3773 362b 19b2 0e8a 1041 10ff 1113 1103 111c 11b0 11f2 11a3 11d3 11e1 11c5 11ab 1124 1182 11ad 11f6 11c6 1153 0fde 0f50 0f28 0f6d 15fa 35f3 353a 346c 348c 3498 34d5 34f5 34e6 3550 358b 35d7 35de 361c 3662 3661 3656 3647 3601 35f8 3550 34b4 34c8 34d2 35b8 360a 3932 1ee2 1032 11b6 11aa 11b2 1151 1203 1238 11c2 146c 211c 2e9f 3392 339a 2f09 231a 142e 0e50 0ff4 1056 111b 1115 10fe 1128 10c4 103e 1028 2e26 38c1 3514 350b 35cb 37fc 30e5 105f 1081 1121 10ed 112c 110a 10b3
342b 3401 341f 343b 3498 34d9 34bd 34b8 34bf 34d6 34f0 34ff 349b 344c 3423 33dd 333d 32d9 3375 361a 2ab0 0b41 0dd4 0f01 0fc0 0fe9 103b 10fe 11d1 11a9 0fc7 1003 100e 1016 0f78 1097 1101 120a 12d4 1221 12b0 12ee 12c6 1378 1427 1496 20da 3a14 3893 36ea 3616 357a 3596 35c4 3564 356f 35cc 360a 3631 362c 35e7 3623 35e6 3617 3632 362e 3628 3736 36ed 2481 128d 0e03 0eb7 0f98 0f58 0fda 109f 10d0 10c7 1136 1152 1139 11a8 1185 1101 115c 112d 0fc6 0fb4 0fa7 0ec4 0eea 10d7 2cb1 37e5 3445 346e 3475 34ab 346f 3489 34ee 3528 35bb 35ba 35f9 35fe 3609 3607 35e8 3587 356b 3532 34de 348b 34bc 3506 358c 386b 1b0a 0eee 1237 10fe 112c 10c2 1033 0fda 100e 112d 10d2 1203 1315 12aa 110e 0e8a 0f6b 102f 1056 0fbc 10c2 10f5 115a 10f5 102c 0f8d 1c68 3939 3553 34e0 3575 35db 365e 395a 288d 0e43 0ea2 10c2 1048 109f 1034
33ed 33d6 3447 3462 35ac 36f0 3790 37f1 37df 3658 34e8 3569 355a 349a 346c 342f 3348 3305 3336 354b 2d39 0c57 0ec8 0f34 0f80 0f77 0fbf 0fda 0fcd 0ff7 0f6b 0fd1 1027 1079 1036 1107 11b6 1205 1245 11ff 1289 138d 13d7 1492 13ea 13cc 1566 2b45 3a38 3676 3633 3584 3576 3546 354f 3537 3509 355a 3572 35b9 35b7 35f0 35d2 35e4 35cd 3588 35f8 35b8 3682 3896 34f5 2861 145e 0cc1 0f88 1002 1046 10af 103f 10b1 1157 1194 112a 1111 1019 1008 1033 0fe1 0fc8 10ff 10b0 0fdd 0f04 1aaf 3780 366c 34bd 3537 34c4 34a4 34f0 354a 355a 35a4 3599 360b 3625 3645 3648 3623 35b6 3575 3524 3522 3519 34fe 3505 359b 3836 1dd8 0ede 120a 1197 116b 1215 11b9 11b1 10f2 10ce 1030 0f86 0f30 1049 101e 107d 0f65 0fb8 1042 0f73 0f9c 0ff2 0fd3 0f4a 0f18 0f93 293b 38b0 3506 3493 3511 358b 3611 369c 3934 2c52 16a8 0dd4 0d2a 0c5e 0d10
33dd 3496 3581 3790 3283 2963 23c4 23cd 297d 324e 3826 36d3 358f 354c 34cd 347e 334d 32d5 330d 3535 2cd9 0c28 0f69 0fb5 0f76 0fc1 0fb5 0fe8 0ff7 1077 10f9 10f8 1115 1176 112b 1178 112a 11d7 115d 116c 1187 1255 134d 13bd 12a1 12d9 134d 1b25 379c 35f6 3538 353f 352e 3533 353e 3506 34d3 3577 35ba 35df 35d6 35c7 365c 3674 3635 35b8 35b4 3610 360b 3621 3699 3824 3551 1d43 0dd8 0fba 1013 105d 10d6 10da 11df 1150 1157 11e1 11e0 10e4 11f8 11ba 117f 1267 11e9 1128 105c 1052 22ad 39a2 3821 35d6 3508 3520 357a 3592 35b2 35eb 35fb 35f4 3611 3621 3606 359d 352b 3522 3527 3524 3566 3581 35ab 35ab 380c 277e 0d7c 117b 1237 110a 1180 117b 11f0 11c9 11af 0fe5 0fb3 0f53 0f9d 0f3c 0f84 0f18 0f95 104f 1026 0fe0 103e 0fae 0e77 0eee 1090 2f7b 36da 33ea 3362 33c2 3476 352f 3571 3618 3886 370f 2deb 25d8 24f6 2afb
3420 35cc 363a 22cf 1277 0f3d 0f40 0f4b 107d 13f0 2187 35d1 3835 35bc 352d 3414 32da 323a 32b4 35be 2916 0c94 0fa5 105b 102f 0fa6 0ff2 1030 1091 1024 10ba 10ce 115e 125d 1233 11a6 121a 11c6 1205 1202 1209 1384 13c7 1310 12c0 137e 134f 1499 31b8 372f 354c 353e 3507 3550 3587 3591 35d4 35f0 3648 363f 36d6 36fa 36ba 36b0 361f 35cd 359d 353c 3567 3550 3514 3514 36b7 37cd 190d 0daf 0f68 10e3 11c3 11bb 11b0 1169 11ef 119c 11cf 1161 11ae 11f7 1234 11e9 1294 1228 11a5 10b5 1191 20ef 3579 3974 37b3 35f7 35b8 35af 35c6 35c8 361c 3634 35e0 35f0 35b7 359a 3566 3506 3523 3532 3530 353c 34fc 34e5 35d8 3332 10cd 0e75 1033 105c 10b6 113a 10d0 10d9 10e3 1040 100f 0f96 0fd7 0fbd 0ffd 0f7f 1008 1061 102f 0fce 116d 1146 0e9e 0e4b 0fa4 3096 3595 335a 3335 336b 33f3 3499 3517 357c 3595 3623 375a 386d 38b7 3811
352d 353f 1b2e 0e18 0f4b 1068 10e3 10f4 12a3 12c8 12f7 1b2a 34a5 372a 350d 341e 32d4 3207 3270 3712 1e8d 0d2d 100d 0fef 1021 1017 1031 10ca 1094 10b0 109e 1144 1085 0f3d 0e54 0e3c 0ebc 103c 1187 1119 1295 13e8 1460 141d 13cd 137e 136c 1307 2cee 387f 35cd 35bd 351b 3572 355e 350a 3514 3517 35a7 36c8 3747 3748 36ff 3627 3551 356f 3508 34b2 34d0 34c4 34ee 350f 34fb 375e 314c 0f6b 0f43 0fb0 1087 10dd 1144 10bb 1096 10f0 1183 11ea 11eb 125f 1284 1253 121c 1267 126f 1288 11f3 10e9 16a2 2220 30ea 39e5 378b 35db 3609 35c8 35f1 366f 364a 3632 35ee 35ae 362f 3600 35ca 35cb 3574 3527 34a1 34a1 34c6 37ab 2553 0b7d 0e5a 0fca 10c1 113e 117c 11e3 10ed 1074 1061 0f83 0fe0 1022 0fa6 0fae 0f12 101f 0fdc 0f7e 111d 119b 0fd1 0e61 0f34 2eb1 3744 33e3 335c 3397 340c 344c 34eb 34c1 3510 356f 357f 3566 35b4 35c3
3687 1dc8 0c4b 0f41 0ff3 0f76 1098 1153 1100 120b 11ea 10f5 1bda 36b7 35bc 3486 33c0 32e6 35be 3344 1346 0fb8 0fc8 0ffa 0ff6 0fd4 1019 1080 0ffd 1016 0f55 0f06 18a1 231f 2705 2660 1fdc 1439 0d5c 1074 12ac 133c 1368 1340 133e 141f 1524 12ff 2d22 3944 366f 36ca 366f 3633 35e9 35cd 35d1 3654 369f 37bc 381c 37af 3795 36d3 3645 35b9 359b 359b 35ed 35fc 35e5 357d 35a6 3502 3889 1c97 0e90 0fba 10d5 10a4 115a 1202 12be 12bb 126c 11fa 11cb 1143 11a5 122b 1213 12b6 1316 13e2 13e6 129f 120a 119c 1540 2556 393e 3845 36d7 36bd 3679 369a 367a 3614 3605 360d 3621 368e 3655 362e 364a 3603 358d 351d 3533 3561 3770 2103 0b98 0c43 0e8d 0f6b 10b4 1104 11c4 1126 102a 0f50 0efa 0ee8 0f96 0f51 0efd 0f85 0faf 101d 1133 11c2 1070 0e7a 0fa1 2773 399c 34a3 3428 3452 3457 3463 34c3 344d 3477 350a 357a 3528 357e 357f
2cba 0d1d 0dbd 0e9b 0f86 0f21 0fb0 10b8 10d9 11d4 1149 11b9 1099 286b 3743 33f5 3446 367e 382f 1e67 0f34 10bf 108f 10bb 10c2 0fdb 0fad 0ff9 1037 0f5c 1695 2ca7 3778 38c0 37e2 367b 3709 34b8 257b 1061 0f42 12ad 12c2 1281 1309 1244 12cf 13c0 3293 3881 36e9 36fb 36e0 36b7 36b2 36c0 374f 375f 36e6 37d1 3857 38c1 38d3 3801 3799 374d 36f3 370c 3712 371b 36e8 36a9 35d1 359c 3830 29e0 1067 1182 1182 12ac 12cc 1319 13d9 142a 1460 13e8 1330 12f3 12b6 12d3 1355 1395 1450 152f 15cb 15ef 158c 1401 13dd 13ad 24ea 3b26 37ca 3766 36f1 36bd 365e 35fa 35ba 3606 35e4 3650 3684 3651 366e 3689 3673 3620 3626 35db 35c9 3740 2851 14d2 0c96 0d73 0fdb 10a4 11bf 1119 10ca 1092 103a 0fb6 1022 1062 0f8b 0f73 0ff8 0f9d 1077 11c6 10d0 0f35 105c 1b94 38b1 35e3 34dd 34f0 34c0 34a3 34d3 34fb 352b 34d8 3561 3561 353d 35e5
1ce3 0bc7 0f30 0fc7 0fc7 0ff9 0f2f 1074 1230 128a 106d 109e 1042 18db 36c9 351f 3766 36d3 2030 0ecc 1005 10fb 1086 109a 0fa7 0fd3 1094 10e1 107a 195c 3539 3802 34ff 3480 343a 33f1 3480 352a 3822 2fed 11f9 0fe4 123b 1398 1390 131c 125e 18d0 37bb 3721 36a1 367e 36be 3733 3756 3756 37b8 3738 3729 3798 38b4 39b8 3a35 39f3 38d0 37e1 37a2 3799 36ef 367a 3603 35ef 35da 35ca 3746 2ea5 0faa 1127 1156 11af 1188 11b7 1217 1318 1391 12ef 11e6 1225 1199 1178 1204 12ef 1456 1486 14b2 161b 15e9 1606 14d0 137d 1519 303f 3a6f 371c 36da 366f 363b 35c9 35ae 35c7 35e7 3625 366d 36c5 369c 36a7 3651 3669 363d 35db 35ca 3603 3787 3699 2d6d 1825 0e44 1133 11d9 118f 1122 1182 11c8 11a1 1196 11f9 10ba 106c 10c4 1013 10ca 11f9 119b 0fdf 1075 1322 2a0e 3964 35a5 3513 34fb 34fb 34ae 34e5 354a 34dc 354f 356e 35cc 35d5
0fe6 0d51 0eac 0f76 0fdd 1000 0fa0 1104 11e9 10a3 103b 0ee0 0d3d 12a0 3298 36a6 2bbb 184c 0db0 0fdc 1062 1031 10d2 10e2 1019 106d 10b3 1006 124e 31a0 36d9 33f8 3417 343c 3484 346f 3483 3473 34d1 38e7 2c76 0fbf 1297 140c 13ea 13c0 117a 27ad 391e 362e 355d 35be 369d 370d 3786 37b8 3832 37cf 38e0 3b6f 39cf 3617 347a 36d2 3a77 3b69 3947 3844 36d7 35cc 3578 3567 355a 35b6 383c 2fa0 0ff8 11a4 1225 1122 10ec 10c7 114e 11dc 126b 123e 11dc 1192 10c3 1057 10c3 1122 11b0 11aa 125f 1350 13ef 15b2 1531 14ac 1386 2003 3a55 3730 3683 364d 35cb 357d 355d 3542 35bc 35fc 3621 366a 3618 367a 3659 3636 35cc 3522 358c 3550 3499 34d5 3765 3729 1fbb 0e14 106f 105c 10ec 111a 11b7 11d0 1186 11b7 10e2 105b 1020 0fe4 1059 119c 11c3 1048 0ffc 10dc 156c 2d95 39fe 36bf 35e1 35ca 34b3 349f 349e 34c0 3534 3595 35de 359a
0b50 0df0 0e77 0f38 0f53 0f57 0f37 1015 106a 1002 0de1 15cd 2674 332e 268f 150f 0fad 0f0a 0fed 10fd 11a3 11bd 1169 1147 1127 1040 1048 0e5d 2441 37fc 33c5 3350 3390 33da 3448 344d 343c 343e 3492 355d 3939 1db4 0fb0 1197 11f8 1040 1b70 37b0 36c1 357d 34dd 3543 35be 3615 3698 375c 37e7 39e8 38ce 2995 1d28 18e1 184d 1a5a 2025 2e1e 3b9c 397a 375c 362f 3599 3565 3601 36bf 39b8 2cb0 1140 11d2 1230 11d2 123e 1213 11e0 1190 117e 113a 1102 10fe 10b8 11f3 113d 1099 1051 1187 120c 1323 13b7 14ea 15b2 159f 14b7 1770 358d 36fc 35ff 3611 360d 35bf 3581 3589 35f3 3662 3666 365c 36c4 36f5 3649 362d 35d4 358d 3588 350e 344a 340b 346c 363d 384c 1a7f 0edf 10a0 1017 10cb 1112 106c 1025 10b8 106b 0fae 0f31 0fd7 1049 10af 11a6 109e 0fd6 103b 0f8c 1364 2643 34d8 389b 3728 3555 354e 34c3 3539 35a0 35b0 35a4 35cf
0bb2 0d4c 0e9a 0f73 0f0d 1002 0fbe 0f2d 0fd7 0ef6 21d1 35cf 3736 38f7 2afc 0db3 117d 11d2 12c1 135d 13cd 127c 11e3 11c6 10dd 0fff 1056 1255 331a 365e 33d8 3369 33f2 33f1 34a1 34b6 3490 34a6 3506 34f2 38ad 2e15 0f25 101c 0f7e 1bef 34f1 3866 35a1 34f6 349b 3506 3588 35c9 362c 372b 393f 3393 1b3e 13fa 1552 162d 15e3 1629 16dc 1798 2309 3977 38d3 3694 3595 365b 36d8 371a 3ad0 2202 112a 10ec 11e4 125a 1301 121b 1233 1206 1139 1154 108d 0f18 0edd 0f02 0efd 0f9c 1023 10df 11b7 1238 1324 150e 1628 16a6 1513 140e 31ad 377d 3596 35f5 35f5 35c7 359c 3598 361e 368d 36bc 3720 3747 374a 36c4 3660 35ef 35de 3589 3500 3487 3432 34c1 3539 37af 30d3 0f9f 0fae 0ff1 10a4 10c9 10c1 1060 1093 1046 0feb 1047 0fae 1134 1152 10f8 11b2 1150 1035 1051 0f8e 1117 15d6 2146 337f 39be 3647 35c3 35f8 35d7 3587 35dc 35ab
0cc6 0dce 0f20 0f9d 0fd3 0fbd 0f09 0f4c 0cfd 2309 384a 34f7 3442 35f5 3558 13d8 0f6e 128d 1335 1296 12c1 123f 1161 10a8 1061 10a6 0f04 1be3 37a6 346b 33a3 33bf 3470 34d4 34f0 34ef 34e5 35ba 35b8 36a7 39e2 3741 1627 195d 29c8 38fd 3929 36a9 35e8 35c1 3581 351b 3510 3564 35a1 376d 35ea 1800 1164 14b7 1539 161a 15ca 15f9 166c 1640 15a6 227e 39b9 372d 3685 367b 3634 384d 362c 1540 11ca 1297 13a6 142b 13c1 1309 1272 11f3 1192 0e02 0ea5 172e 1ebd 205e 1b93 129f 0ca4 0f5d 1168 11bf 127d 135c 1452 1691 1533 1467 328f 38cd 369b 3688 35fe 35dd 35af 3599 3607 36b6 368d 36f6 3706 3719 3706 369f 3689 361c 360b 358b 3522 34a3 34b0 3442 34a7 3893 18f8 0d74 0f71 0f57 1012 10c0 1024 1083 10ac 108a 1136 10fc 11ba 11ee 1052 1033 1203 11b9 0fe1 0f40 10a4 10d0 117f 17bf 2ec6 3997 3667 3627 3601 35ed 3617 352d
0d9b 0e6c 0f30 0f3e 0fe2 0fa1 0fd3 0e5a 18f3 36fa 34be 33a3 3401 3486 37b5 271a 0ccd 10ac 118d 11d5 1248 11ce 124c 1133 107a 0fda 107b 2e04 3684 33cb 3341 3400 34b8 3500 353a 3585 3591 3645 38a4 375f 2cfa 268e 3460 3882 38f5 36aa 3604 35f2 3587 35a1 358f 354d 3547 358e 3626 396e 21c7 1115 13a9 148f 1468 1566 156a 15cc 15bd 15b5 1563 1591 2e07 39ba 36c5 3641 36cb 3a7c 21bd 1091 11f7 12b8 13a8 1380 1268 11dd 1105 1037 0ea6 1ac7 2ff6 37f2 386c 388a 383f 35bf 26d1 123c 116f 1343 1284 1317 134c 141b 14bf 1805 369a 3938 3761 36b7 364d 35d4 35e8 35fb 3659 36f1 36b4 3771 3776 36ed 3739 36f9 366d 3634 360a 3507 350e 34cf 3498 3402 3466 388d 231b 0c08 0faf 0fe1 10e1 1117 10a6 109f 110a 1021 0fd4 0fbc 10e7 123f 108a 0f62 1216 1320 0f9f 0f84 10a4 1121 11f9 12c2 1823 3402 38d7 3706 36be 36ac 368f 35f2
0eaf 0e9e 0ee5 1001 0f80 0f4c 0f7e 0f70 2bc8 3677 3365 33ad 341f 34bb 3580 370d 2080 0ce7 101b 120b 12dd 138b 131f 11ed 1006 0ecb 2542 37c5 34d5 3438 33e0 3455 34e1 3543 3597 35d8 36b6 39a3 2d92 195d 1306 15bf 358d 382d 358b 35a3 3547 3561 3570 354c 35ac 3554 35c7 3659 38c5 3565 14f7 13ee 14bc 13ec 14ae 1521 155c 14b4 14dd 1447 1465 13ff 1f62 3a3c 3835 3915 3a99 26b2 112b 120c 1156 118f 118f 11c2 11a8 1130 10b3 0ee9 20b6 3866 382e 358e 3562 35af 3590 36cb 39ec 31b9 1576 13ab 14ad 1416 1429 14e9 1466 1fb8 3b5c 38eb 37d3 3743 368d 35cd 359f 363c 368b 3682 371e 3852 39cc 39f3 396a 381e 3710 36d8 3696 3654 35a9 34de 340e 3435 3501 38f0 26a5 0c71 0fff 1055 110b 117e 1192 11b1 1130 10e9 1058 10bf 11d5 125a 10bc 100f 120a 13ae 119b 10cc 118e 1205 1204 1306 1384 2196 3a0a 3730 3714 36f3 3692 3621
0ec2 0f34 0faf 1032 0f83 0f9b 0e38 1367 34dd 33c5 333c 33ab 346a 3593 361c 3671 3788 2565 1191 0ef4 100b 101c 0f22 0ee8 137e 28ec 37fc 356b 34f3 3525 34e0 3535 355f 3563 3619 3668 399d 2923 124f 1337 1469 143b 2b86 3a25 35f4 35b1 3511 3565 3579 35a5 358d 35ad 363c 3740 3b53 29a8 13cf 1595 147d 1493 1557 1569 1437 1401 1459 14b8 14af 1340 16ec 378d 3cba 35da 218c 1274 12b5 1242 11d6 11c4 11cb 10ee 116a 1206 1129 1e61 399d 371f 360f 35da 358f 35c3 35bd 3629 368a 3a10 2eb0 122a 14d8 15bd 154e 1526 1477 300f 3b1f 38a8 380b 378e 370d 3659 35e3 3624 3675 3737 3a05 384e 326e 2ecd 30db 370f 3b48 38dc 370c 36be 3610 3553 34ba 34f2 35b1 398b 259a 0d1f 10bb 11e8 123b 11bf 11af 117b 117e 1137 10c2 1087 118e 11d0 118b 1194 11df 126f 10fb 10d9 11f3 12d9 12e0 12b7 140e 176f 3608 38b2 37a3 37a6 3717 3666
0ed9 0f2c 0fe7 0f91 0fcb 105c 0e8c 17fb 374f 33f8 3343 343e 34f7 35ab 3613 361f 36a1 38a9 3401 2813 1f4b 1b51 1f7d 2920 34a1 38f2 35e6 35a5 3588 353e 350b 3519 3517 3542 362b 388b 3010 1265 1288 151a 14a5 14b4 1cb5 388d 37f6 35e2 359f 3568 3584 35c5 3614 3621 365b 3841 3885 1978 14c2 15cc 163e 1639 157c 1470 142e 14a4 1419 127d 1618 23dd 2f5d 2af4 20d7 1774 122e 1404 1517 14ad 136a 1331 1356 12d7 1394 1405 15df 359f 39ab 36b9 360d 35fe 3581 35c1 35a2 360b 369b 373e 3aad 1fcd 12dc 1656 144e 11ab 22d4 3ac4 3894 3820 375e 3783 3728 36ce 369a 36c0 3919 3970 2754 18bf 14ec 14d8 159d 199e 250e 3726 3a79 37ae 3748 368c 3571 3530 35a7 39aa 1f4d 0e63 10a2 114b 127f 1225 1163 110a 10e9 1035 10d2 1158 11e4 112f 1136 11f8 123a 11fb 1081 1056 1169 1207 13ae 1332 143b 1564 3006 390e 377c 37cf 3738 36a2
0f75 102a 104f 0f62 0ef8 0f44 0ded 19c3 37fc 33cc 33b9 3491 3518 3545 3594 35e2 365a 369e 378c 38ab 3917 38be 3861 3789 36de 366c 35e0 35ea 3598 3583 3572 35ee 3597 35b5 3636 38d2 1bfa 1105 14c7 140a 1491 14d2 1528 252d 3b17 382c 3588 359c 35d7 35f4 3627 36a6 3818 3aae 22fa 1270 1442 1527 1587 14fb 13f8 13a4 1465 1460 114f 1e67 350f 3a9b 3cb7 27db 1346 165d 1661 1560 1467 1452 1405 14b1 14a1 14c7 14a9 1386 2208 3baf 37d5 374a 36a9 3653 35fc 35fc 35c1 3539 35c5 3653 3943 2f36 1101 11ed 117b 21ab 395d 385d 373b 3703 36d9 3720 3744 371f 3727 38de 391b 1f2d 11fd 13c8 14f6 1522 14c5 1502 1486 1d11 3546 3a8d 37da 3732 3618 367e 3752 3717 14e7 0fac 1201 120c 1220 12af 1146 10c3 10bb 1049 1013 0f38 1074 128a 1073 0e3e 10d0 12e7 1126 1096 10cc 11a1 1314 14e6 136a 1349 2d6f 3916 3727 371d 36e2 36cf
0fbd 0f65 107b 1028 0f0f 0efe 0ec1 183c 3749 3486 340e 3485 34cc 3522 3569 359f 35f8 366b 3648 35ee 3628 35fc 34ff 34cf 3593 357d 358f 3578 3564 3589 35a7 3617 35fb 3628 3750 3314 11df 1349 1569 1403 1499 1432 1457 1641 24f9 382b 39ea 3823 37f2 37e5 3875 3ae0 39a7 24cb 12fa 13ab 13ff 14a3 14a4 141d 1421 13fc 146b 1258 20c2 3a05 3914 3688 385c 32f5 1477 1721 1796 1707 1536 14fb 14be 151f 1503 14b3 13e2 12de 2f26 39de 375c 376f 379a 375e 36ec 374c 3706 3649 362c 3767 3ad5 3826 1649 19c6 2c95 3a1f 3890 36e0 36aa 3618 3644 366b 36a3 371d 37bc 39e1 2033 111b 1374 14d1 1561 1522 14ec 144d 147f 158e 1f1a 3938 3898 36f6 3674 36b8 3b3f 286d 0fe6 1219 1248 12e5 12b3 13b9 127b 1142 1003 0edd 1522 24bf 2eb8 32b4 30d4 2850 1a59 114b 11e3 10cf 10cd 12b5 145d 1519 1480 131f 3033 3929 36d4 3694 3678 3691
0e71 0f0f 10bb 114e 103e 0fcc 10ef 13ad 336f 3646 3443 3450 34b9 34f2 352f 3558 356c 35c6 35ec 35f6 35a4 35aa 358b 3594 35bc 35a7 35e5 35a5 3535 350f 35a5 3612 36c7 36a9 390b 2da5 10b6 1454 1473 1455 13bc 13f5 1433 1507 14a5 1b84 2aea 3567 38f5 38e4 3604 2c54 1c1d 13e1 13ec 13a5 1374 13c8 140a 13ef 1429 14d5 13da 1a9c 391b 39a4 3761 36d3 36e9 39db 2171 129c 1757 176e 172e 178c 1688 169c 15c4 148d 122e 1d23 3a32 3873 37a2 3767 3777 37a7 3744 37d5 3779 36fd 3963 3849 2d41 25b0 3520 39a1 39ea 375f 36cd 36b6 36a7 361a 360d 3651 36b5 3749 39ae 2d0e 105d 12d8 13be 147e 13e1 134e 1535 1397 131e 1406 15db 2c28 3ba6 3776 3729 3a8d 325c 13a8 114e 11c0 1258 12f7 1332 1348 1194 10a5 0eee 211c 3747 3a71 3912 3801 3844 3950 3847 2613 1017 0f7b 111d 1289 1432 14d0 1479 15bf 3636 384f 3704 36ee 36a5 36eb
0f21 1053 112c 1139 0ffd 0fdf 114c 1230 273d 388f 3443 34d4 34f5 34f9 34fe 34e7 3511 3551 35c7 3609 355b 3555 354a 34f9 3529 3554 3541 3586 355f 35a0 35e9 35b0 35f3 35ef 3825 2bac 10a1 147b 150c 14b7 143d 157f 14e8 14b6 156c 148b 151f 18dc 1bc8 1b2d 17fb 14d7 1407 144f 142a 142a 13d8 1451 151f 1415 148b 14ee 138e 2da3 3b94 37ba 3722 3733 37ec 39c3 37b4 1a91 1391 165f 17b9 17c2 1752 16be 1575 1214 1699 33f9 3943 3761 3725 3724 3793 3754 379d 3829 38bd 3b52 3020 1980 1218 16d1 3800 395d 370d 3711 36dc 364c 367f 365e 36b2 36d9 3771 37ed 3a42 1c23 1023 12bb 1316 13d5 13f7 145f 147f 149b 1419 14eb 1505 2016 3c61 3a98 3bed 31a4 1584 10da 12de 12d9 134c 1389 1359 128b 11a3 0f65 231c 3a6d 37b2 35e7 3635 3586 3565 358f 367f 39e6 27b8 0d8b 10c2 120e 12f5 1528 138a 2047 39ed 36f3 368f 368a 3686 3649
0f0d 0f65 10a1 0f7d 0edb 0f07 1071 121d 1696 3494 370b 34d5 350d 34da 34f3 34f2 3523 3563 35a5 3597 3556 3579 3567 34e2 3520 3568 354b 3563 3542 35d5 359a 3583 358b 35de 37a8 2eae 10a5 1362 151d 1584 159c 1551 15ba 152d 1568 15a3 166d 16a7 15d6 15b7 157e 1480 14bc 13d7 1452 1502 14e1 14bd 1547 1615 15bf 15b5 193b 37d4 389e 3727 378d 383e 38ee 393d 3b17 374b 1fef 1345 13e8 14ab 13e0 12ea 1235 1caa 33f2 3a1b 371c 36bd 363f 36cc 36b2 36a5 3750 37f0 3ba8 2dec 15df 13b0 1407 1605 2f10 3b5c 36b7 36a1 365e 3633 35c9 35bf 3626 366d 3715 39d1 3490 12a4 125f 13d7 145a 1390 14a4 1447 145f 13c2 1397 11f4 11c6 1cd6 37ef 352a 2536 149c 1236 1355 1389 13ac 1319 1374 134d 125b 112b 1c14 39b5 370e 35f0 3601 3639 35fa 358b 352d 356e 36a4 3a76 1bb7 0eb9 1305 1491 1330 161c 33d9 3846 365b 35de 35f3 360d 35bf
0ed9 0f7e 1046 0fa6 0f65 0f8a 0f6f 1094 11b9 1cb0 3695 382d 35b1 3577 35be 35c6 35b9 355a 3577 3583 3519 3566 3555 354b 358f 359a 357f 3557 351f 3535 35b6 3659 36b6 374d 37f6 3634 1529 1387 14f1 14c2 146c 145c 154d 14a5 1407 1413 1446 13c9 13ca 14d8 14f4 14d6 137d 1321 1348 142a 14be 1492 141e 14df 14fe 1589 1f72 3ac5 380a 37dd 3822 38b2 38d8 38d8 3881 39c9 3a5e 2fa2 22fe 1cea 1c18 219a 2dd5 3968 3a32 3840 37ad 36cd 363e 35f4 3614 35e3 36ba 38f8 33c6 15c2 14c0 15da 15a2 1636 2009 3a66 38c7 36d2 3692 3644 35b7 359a 35c3 364b 37a4 3bb9 21ac 10ef 136a 145c 15d5 1473 1475 1419 134e 133f 1163 1ded 2f29 386d 20c2 13f3 12bf 1427 136c 1335 1454 1441 146b 14df 1423 12f5 12f3 3052 3976 35cd 3585 35ee 3677 3667 35f9 35fe 35b9 36a1 399d 2e17 0f5f 1398 13bf 1563 2efc 3af5 3758 36b8 3645 362e 35c9 35a8
0f2e 10d5 111c 0f23 0f32 0fc7 0ff3 10b6 1311 125d 1c90 326d 3a18 38d2 36be 35ed 35ae 3555 3585 3577 3567 3584 3576 3562 35a8 35b0 3565 352c 352a 351f 3623 36ec 3756 37e7 3877 3a8a 20d3 114d 14c7 14d0 151c 1496 1463 13d7 13bf 1388 134a 1278 129c 141d 153e 157b 15a1 14c4 13e4 140e 145f 1518 1543 1492 14c8 13c3 20d6 3b1b 37c2 3785 37b1 37a2 378d 37bc 37fc 387d 3840 393e 3ad9 3987 3960 39f0 39cd 38b0 3801 37ec 37d8 37a1 36c2 3663 365c 3665 3702 3a0f 1fe4 1218 149b 14ad 154e 15a1 1720 28d6 3cc8 3953 3706 3679 3617 3607 3688 3829 3c50 2b28 1284 12fc 138b 139e 14fd 14ac 139a 12b0 1235 1229 2ab0 39b7 3905 3b01 24a4 0fc0 1339 14de 145f 131f 13be 1454 1432 149d 1480 1280 1b3a 3a2b 37ac 363d 3586 3573 35f1 3610 3685 3711 3700 37aa 3954 3851 130f 10ba 1beb 3217 3b96 37f4 3718 3729 3621 3666 363a 3609
0fb6 1127 1117 0fc7 0f63 1091 10e2 115d 11b1 123d 12c4 160d 2171 2dab 3854 3884 35b3 3625 3624 359f 35a2 35c3 35c7 3590 3590 35b7 3546 34d5 353b 35b2 3654 36e3 376a 37d4 37ca 38e7 34b8 147d 12a1 14a2 13d2 1394 1396 1326 1380 1413 148f 13ba 13f8 14e1 150e 1509 1634 15d2 14ff 1558 156d 15c2 15fd 1563 1541 14fd 1efc 3ace 37f2 3754 36d2 36e9 3702 36ff 3766 37ab 37ab 3754 37b0 3820 384f 3867 3845 3825 3800 37f7 3877 382c 377b 3700 3707 370a 37c5 354e 14b5 13ea 154d 1537 1639 149b 155d 180a 27df 39ff 3bc1 39de 38b9 3961 3b41 39ef 2796 1388 128d 133a 13de 1303 13e7 13dc 134b 123d 10c8 2a87 3b2a 3681 3635 38f8 32da 1144 12c3 1484 150e 13bc 1430 13a8 136b 1340 12a3 10e1 2aad 3b74 376a 367e 3679 369d 370a 36fb 3737 3738 3857 3b2b 3a9c 339a 2932 2fe9 39f5 3a6c 3819 373c 3670 363a 3636 3648 361c 3709
0fde 1146 10f0 0ff6 100f 10e4 1140 1225 11f1 1176 11d0 129c 1243 1342 1d3d 32ab 3946 36c3 3615 35b7 35cf 35a7 358c 3578 35c8 357e 354f 3513 354b 35d4 3675 3716 3771 3747 379b 376a 39de 2e87 13ca 115d 1361 12d9 110b 1208 1237 12a5 124f 13cf 14f0 14b8 14a0 147e 14e1 1546 1542 1537 1525 15ca 14d4 1581 14e4 144f 1a23 38d6 38db 3761 36e2 36c0 3720 372e 370a 36cf 36cc 3732 377d 3800 3884 3891 38b3 389b 3841 3890 390a 383c 38b1 38a1 380d 37e8 39c3 317f 12ce 15f9 16ed 16e5 1762 164a 154d 165a 16a4 1d67 29ea 32a8 34c8 328b 2972 1a97 1168 12e1 12d3 125f 11cf 129b 12ef 12c2 125b 1183 1eb8 3a39 36f4 3633 35fa 369e 397d 227d 0ef5 1341 1405 1402 1355 1384 136d 1271 0f3d 1be5 391d 37e5 36a0 360e 3644 367b 3717 381e 3888 395f 3aed 2be5 1baf 17cd 3886 3a6a 3818 37d0 37ee 37a0 3727 3662 3678 3670 36c4 37a1
1073 110a 1007 0f4c 101f 1099 10f5 11af 11ec 127c 12c3 12ae 13b3 13c7 13e7 1842 3196 3918 36a6 364b 3643 3630 3625 35c4 361e 35af 3535 3595 3554 35ab 362d 3658 36a0 36ac 3710 3775 372f 3a43 332e 1c1a 11f7 106b 1163 133e 1436 1466 1482 1381 1386 1456 14c9 143b 1463 14e6 1504 14c6 13ef 1322 1418 145c 14b5 14f9 15d7 2f4e 3b4c 3777 372a 3713 378d 3793 376c 371e 36bb 37aa 37a2 3841 38da 393e 3939 38e4 38da 3890 386c 384a 382d 3835 3885 3885 3a0e 3064 12a8 14c8 150a 159a 15d0 1615 1618 1471 14db 1540 1644 17d9 17a0 167e 1597 1403 1416 1485 1483 1437 1328 1348 1325 1312 12af 1324 30e7 397d 3678 3622 35ed 3685 3752 37cf 1d55 0faa 120a 1354 144c 13ff 11cf 0fb2 1a61 3519 385f 36e2 3640 35d2 3605 362e 36a8 380f 3a0e 3abd 2239 1280 12c0 13a2 31cd 3a0d 36d3 36ff 372e 36dc 36c9 36c7 362c 36a3 36cf 378e
10da 109f 0fdf 0fe3 0ff5 10f8 1134 126a 1246 1287 12e7 136b 1441 14b8 14c4 1441 1c06 37e1 37d7 36b4 364c 360b 35e2 3590 35e3 35b1 3551 35ac 35db 3613 3682 36ab 36a2 36d1 3659 3676 36fc 3776 39ad 3a45 31f2 21c9 1116 111f 12ff 1367 12fa 1392 13e4 1445 14d5 147e 14aa 153a 1521 151f 15b6 14b8 148a 143c 14ac 1509 1573 1de3 39c9 396b 3780 3790 376e 3749 3772 3791 3790 3791 3834 387f 3844 3801 385f 3871 38ad 389e 3861 3855 380d 3832 388c 38c4 3a21 325b 13a8 14e6 14b2 14c6 1477 14dc 1620 152b 1521 156a 15b5 1641 1565 1531 15d0 1543 1505 156c 1533 142c 14e5 1565 13f7 135b 13c7 17df 37e9 36f6 35fa 362b 3618 36ec 37e7 38f5 38fc 28bb 1802 12d9 11ac 1267 16fc 2615 3835 393f 3792 3747 36cc 361f 3650 3615 36e3 3843 3b0f 22a9 12da 1460 1372 128a 23e6 3bb5 37a9 3767 36f1 36c1 3685 365e 3640 36bb 3661 3992
0fb3 103f 0f07 0eb9 0fba 102f 10fd 1296 1238 123a 1289 13c4 14ab 14f4 14a2 145f 131f 2a8b 39cb 368e 360c 3640 35df 358e 35da 35cf 3629 3614 3656 367b 3678 36e7 36d8 3729 36a4 3633 3694 3767 37b8 3824 3857 39b2 312f 1594 0ff2 131a 13b4 13f1 1544 14e6 1412 14ec 1540 152e 1527 1597 1740 1709 1604 15af 1574 1554 161d 15ce 2439 3a9f 3a52 37f4 37b2 3817 37b5 3819 37e7 37fa 37cc 381d 37fa 385b 3843 3897 38c0 38ec 38d6 38bb 3872 3869 38c2 395f 3a5c 3837 189e 1616 15f3 16e1 15e7 166f 15f9 1645 1535 148e 157f 154c 1526 142d 13e1 137f 1403 14c0 14b1 1378 14e2 14c0 137a 13a4 1446 1e63 3a5e 36be 35f9 369d 361b 365e 3791 382f 3882 3ad1 38af 32bb 2fa0 31cb 3804 3acf 387d 37a1 3709 36c4 3731 36b0 3674 3699 378d 3a77 2c5e 1319 1516 13b3 134b 1344 1626 3169 3c17 37b9 36c9 3737 3727 373a 36c8 3728 3a5a 34db
0fc2 0f17 0dd7 0e82 0f1f 0f42 106c 11d8 11d4 1295 1458 1418 1409 141d 13b2 140b 13ae 1db4 3918 36b0 3686 364b 3620 3600 361b 364f 3687 36b5 36be 368b 36a1 36ea 36ef 3719 3772 36f8 36cd 3756 3782 3743 364e 361e 38af 33c7 1514 1156 1279 1403 150f 1511 154a 15e8 14ed 1554 1594 15b6 15db 161a 162d 15c1 15b2 15dc 15ef 1662 15d1 21a4 35eb 3c06 3b0f 38b5 38ed 3907 38b0 38ae 38c3 38c7 38e7 38dc 38fd 38ae 3888 38ae 387f 3890 38b6 3905 38e8 3911 3a2e 3c80 23f2 151c 17da 179b 1692 1710 176e 16ae 16b7 1615 15f7 156c 151e 14fc 1430 133e 13f1 1497 143e 1365 13f9 1406 1322 1468 149d 2074 3b52 3743 3706 36e9 3663 3669 3722 378c 3834 381e 3867 3903 39b7 393a 38c0 37ea 378f 3712 36b9 3686 3705 36ee 3673 3692 36f0 3946 1b39 13f1 1507 1511 14d9 13f8 129e 19b2 32c1 3bf3 39c9 385f 37f1 3872 39e6 3c71 33a6 17fd
100b 0f3e 0e94 0cbf 0cf1 0e03 107e 1251 11a8 11b3 1168 128d 13ca 1446 13c7 146a 1459 17f2 368b 36c3 366c 3622 3670 3666 3645 3687 36b7 370b 3726 36e3 3703 3742 37d7 37fc 3826 3797 36fa 3731 36e5 36b5 3640 35ff 3612 3a1b 2c62 1117 1380 147b 14bb 1544 1576 15ba 1578 1533 15b6 15e1 1562 14e0 14e5 14be 15d6 160f 15fd 1548 158d 1583 1983 23bc 31d9 3c39 3aa2 396f 3976 3959 38d3 38dd 390c 38e3 38c5 38a1 3870 387f 3864 3898 390f 38fc 387c 3861 393d 3b19 3728 198a 1520 1861 1880 170d 179d 1699 15d0 15fa 1660 1625 15b5 1513 14b3 1436 14f7 14b9 13bb 1367 134c 1483 13d0 1470 14bf 1d59 39e6 370f 3628 3676 367c 3649 36ac 36fa 373a 36e3 36d6 3772 37a4 3777 37b5 37a9 3737 3769 37d6 3749 376f 3740 3700 3712 380e 351e 132f 13fe 15e4 1550 1485 1402 127f 13bb 17c9 2846 35e4 3a5c 3aa4 39df 35a2 2752 16c1 112c
0e02 0aa6 0d03 134b 1638 141f 0f90 0dd2 0fc9 127a 12b3 12c3 14fd 15bd 1485 1448 13e2 16a6 35c4 3749 3681 363e 3627 3618 3657 368c 36e6 372c 37a3 3765 377c 37c5 384e 3877 37e3 374c 372b 376b 3702 36ab 35fa 3599 35d3 36b0 3890 1825 12f8 1532 149e 1482 1461 14ea 1506 1573 162d 16a4 15f8 160b 1618 161b 171a 16bd 1670 1626 1510 14f6 1749 171f 1940 24c7 39fd 3b36 39f6 3999 3945 3998 3952 3919 38b7 38cf 38d6 38db 3898 3906 392a 391e 38db 38be 3994 399c 3bf4 32ae 1861 13b4 16c1 17d2 1768 1868 15f9 1699 1676 1706 1644 1516 14cb 15ac 16d1 16da 1544 159f 1548 1551 15fc 14f6 15b5 1936 361a 387e 3611 36de 365d 361d 368d 3726 3797 377d 3721 375e 37ab 37b3 37bb 3763 375d 3761 3807 37bb 37e9 37d4 3804 3819 39ea 327c 1233 13e2 1475 1484 14f9 13d4 1234 1307 143c 155f 191c 1d82 1ecf 1caf 1684 1319 12d8 1218
1045 222a 3002 34c8 35f4 3546 321b 2695 149a 0e9a 1277 13b5 141a 141f 1325 13d9 1388 18d7 37d7 37bc 36f9 363a 3621 3631 3630 3699 36fd 3775 3784 37d4 37d4 38b4 3896 3857 3811 371f 36ac 36a0 36b8 3678 35c8 35bc 365d 364b 3962 2392 112a 146a 15bc 1586 154b 1607 161f 16e2 16a7 1670 157f 1580 15dd 1626 16f9 1709 1796 1779 177c 1611 15aa 16f8 1735 1789 2324 3bc6 3ba4 3a8b 3a1f 39bc 3946 3929 3935 38ce 38b7 38a4 386a 3881 38db 392d 3880 38a7 38cf 38b4 3997 3c1b 36ef 245c 175b 13b2 16d5 17ef 1729 1721 178c 16b2 169b 1573 1549 14fc 15c9 16e1 15ad 161a 15c5 1580 15fa 159c 15f0 1735 2a1d 3c0f 3711 3747 369f 3699 36fe 3732 3796 3830 37ed 3841 388d 383c 3798 3753 373b 3720 3734 3756 374e 37fe 38a5 3907 3a5a 3336 1343 1501 13e0 13b5 1532 142a 1289 13b9 154d 1600 1640 16e1 1660 1558 13c3 13f0 13c6 1234
301c 3602 33ee 334a 33be 33ab 34e5 3717 3453 1d64 0fa9 1324 13a3 143c 1327 12e9 1220 1f82 3930 36ce 369d 365e 3626 35f6 362d 3704 3758 37be 37e4 37b8 3808 398d 39a7 38ff 37ae 373f 3704 36fd 366b 3658 3645 35bb 35f9 35d9 392d 2a72 1137 1419 14d7 1538 1542 155b 1643 16cc 1684 1552 160e 15ab 15a1 160d 164b 15a9 1779 1849 17b0 181d 1859 17bf 1703 187f 1907 2cda 3d35 3a9c 3a2c 3a31 399f 39a2 39b9 3903 38df 38cf 38cf 389b 38e0 389f 389b 384f 37ed 3851 392b 3911 3a3b 3be7 3941 2af2 183f 15fc 16a0 16db 173d 16c8 15e7 155a 15ae 158e 162b 16d4 14f2 14b3 1447 142f 13e9 13c5 1453 1568 19ae 3529 3bd2 37d7 378f 371b 3728 3736 3786 37f7 37c5 37df 37e8 37e4 37de 3778 36d7 369c 371d 3791 3725 374b 37fc 385a 3904 3705 1581 1425 141d 132c 1500 13b7 10f5 11b5 1381 15f4 159d 165e 16ed 150b 1315 131f 13be 1350
3461 32c4 3258 32b3 32d5 3355 3380 33e5 35f7 3836 1c04 113a 144a 1467 139a 1392 1264 2d52 3893 3638 3610 3641 368d 368b 3686 3712 37f1 37d6 3896 3adf 398b 365c 35d0 385e 3a7d 39a1 379f 375b 36c1 370d 36b9 3694 36b1 3662 39e0 2bdf 121a 14d9 156a 15b9 1558 143e 1495 1551 155c 14fa 15b3 15bc 1526 1576 1604 16ed 16d0 17b6 17df 18a4 19b0 18d0 187a 18ec 18d4 1e24 3a35 3a41 3986 39e6 39e9 398c 3996 394b 3907 388a 38f1 38c8 38d3 38cc 38ce 38d4 384a 3841 386a 38b5 3914 3998 3a9c 3cbd 3505 1996 14f9 1655 1694 16c9 167f 158a 14cb 157a 15fa 16ce 163b 14b8 141d 13af 137f 13a5 13af 13bd 14b1 1cec 34a3 3c3c 39d0 37e1 3826 37ee 37b3 3814 3827 37de 3800 3822 37dd 376f 36c9 3651 3696 374a 37a8 3774 3782 37ad 382b 3aa6 1ffa 11bc 137a 1292 138a 1370 11bb 110e 124f 142b 15e0 164c 1610 159d 1380 13a1 1392 12a2
334f 331e 334e 338e 33cc 3400 3465 345d 34de 370a 3360 1323 11fc 141c 146b 1114 1ee3 38af 36cc 35b5 3577 35a3 3618 35fe 369e 3753 37fb 39fc 36d8 277a 1c61 18ce 191d 1b3d 222a 311b 3b0d 38d5 37cb 376c 36bd 3698 371d 36b0 3a0f 278f 132d 151a 163a 15b9 1563 14da 161d 1537 1559 1614 1733 166d 153f 1523 1595 167c 1700 17bc 1873 1904 1898 18a5 1910 18e2 197c 18a9 3388 3a7c 38e6 3965 3927 38b7 38f8 3909 38df 38fd 390c 392b 393f 394d 38c9 3855 3822 384e 38a4 390e 391b 3955 394b 3937 3c82 30c7 158e 1657 1565 1570 16bb 1675 14f9 152b 1519 14ff 143d 14b1 14d6 1499 1447 142c 156c 1501 1481 1588 19ae 2913 353b 3b42 3a20 3843 380f 37ff 3819 37f0 37b3 376f 37b6 37e4 3743 3658 367a 371f 3793 3790 3772 37c3 3851 3980 330e 128f 1138 136b 1349 1599 1368 111a 1279 1406 15ff 1726 1777 1691 14bb 14a8 1458 130f
32e5 3301 33f4 3405 3408 3491 34aa 3462 34de 3526 38f9 2185 10d1 1363 1014 1c27 3650 3720 3634 359b 363b 3630 367f 3636 36d7 3770 3a67 31b1 1958 1429 14f5 1517 1702 1640 1508 171c 274a 3a47 38c2 374c 36f5 36d4 36b5 3734 3ab9 1efc 12e9 1490 161d 15af 148f 1521 1511 146c 14e4 155a 15a3 13a2 1133 1193 12ba 1433 1625 16d5 16fb 170e 17ec 18d2 1824 1927 198c 17bf 2efc 3bec 39a2 3985 38f6 38fc 38f9 38f3 38e3 38a6 3904 3997 39ac 3985 3965 38ea 387a 38ee 38ff 38bc 38ff 38fd 382e 384d 3985 3d5c 21d2 1526 15dc 15d1 16e6 1612 14c8 146d 1473 153a 14f5 1568 1555 1544 1582 153d 15b9 15af 14df 154a 14f8 163e 18cc 22e8 37b5 3b42 38cc 38a1 382c 37e3 3759 377b 37e8 3811 3791 3756 37c5 373e 372d 371a 36e4 3761 379a 37f8 3a2e 2a0e 1067 10bd 135c 14ca 14f6 1131 1166 1275 152d 170a 18be 182d 1685 1563 1519 1423
337d 333d 33f4 340d 3498 349e 34f6 3596 3596 36a9 3aae 2fed 1173 1649 2637 3749 37eb 35fd 362e 3670 3643 3622 3653 36b8 3722 39e9 3402 16ff 139a 14d3 14d1 15af 172c 1626 169d 1761 16c4 27c8 3ba9 38bd 3820 376d 3786 3aaf 3471 1501 159e 159b 15db 151f 1465 150c 1540 1595 1532 1296 14e9 1da4 24e2 26ab 2392 1b31 13c7 1559 17dc 17de 17e5 1825 1768 1839 1752 176b 2fa8 3c0e 39f9 39c5 3955 3902 390e 39c5 39ad 39b9 3a27 39d8 39ae 39bf 39d6 39e4 396e 3942 390a 389f 38fe 3898 3886 38b6 3951 3c68 2f32 14ed 164e 160e 170e 1629 162d 1608 1553 1512 1539 15e7 15ba 14a9 154b 1612 155a 149f 13f7 1363 1468 1458 1521 1503 1d45 3798 3a89 38fc 38b6 3849 37b9 3781 3769 37b3 37be 37ea 37eb 37a9 3748 374a 374a 372b 3752 37b0 378d 3a03 2eee 184f 0fc3 108c 149b 11f0 1126 115e 1412 15ac 16e2 177e 173f 15e3 1540 144c
347b 345a 3403 3492 3565 35e2 365f 36b0 38b0 3a8c 3475 2e59 307f 36e5 3940 370d 36eb 3668 3639 35f3 35b8 359e 35c4 3635 370e 3981 1cfb 125c 1523 1500 15f2 1698 16b1 165e 1729 1775 181f 1925 333c 3b56 38f1 3815 399d 3c3e 21a3 153d 1723 1833 1813 1637 148e 14e2 1505 154f 128f 2006 3419 3a8f 3b83 3b8e 3c1a 3ac7 2fb6 19d3 14d4 1844 1870 18e0 184c 179d 16b0 17f2 359f 3b90 3a26 39e4 3955 3944 38fb 3974 396a 399f 3a3a 3a6d 39e4 3aad 3a80 3ae6 3a4e 39f6 3952 38b3 386a 38ba 3841 3850 38e0 3a74 3513 15a3 15e3 15a2 167b 15f6 168e 16ab 15ac 13ff 1457 1539 1624 1495 1486 15c4 1646 14d1 12e2 135b 1451 1527 153b 1561 15d9 213e 3b7e 3934 388b 3855 3842 37b6 378f 3743 36ea 37a1 38c9 3881 37ac 37b9 3714 369d 36e6 375f 382d 3871 3a95 39d5 30a9 1f93 1292 1302 122a 11a8 12ea 159c 1616 163b 1653 15a4 155f 148c
3478 34e9 350d 354d 35f4 3703 3799 398b 3255 20eb 15aa 1cf9 3b91 37ec 3607 3628 3651 3645 3678 3674 363a 35f6 366c 36e2 38e9 3001 117c 1333 147a 151b 144d 1463 1548 1661 165e 1667 17fd 172d 23f1 3c31 3a12 3be1 3c64 2669 14e2 1697 1787 1729 1683 1506 1427 14a8 14d1 12b6 2783 3af3 39a4 3799 3783 3823 3886 38e6 3b1e 3852 1c37 1638 1857 194e 1965 18ad 1709 1e0f 3b72 3a4c 3a03 3a32 39b9 398b 39ba 396f 39f0 3a5c 3b1f 3cf2 3dee 3e6e 3e94 3e21 3c9c 3aaa 3a11 395f 3977 3926 3856 3885 3970 3acf 3761 1736 15fc 15c2 1670 159c 1649 1649 156e 1458 14c7 1629 165d 1484 14ef 16e1 17a4 15fe 1418 1472 151a 168a 16c5 159b 15b1 168c 30af 3aab 3883 38e7 384c 3810 3843 377c 3734 3813 38ba 38cb 38e0 379d 372b 3768 3773 37a3 3875 38b1 3812 3831 397e 3b54 29a7 12f3 139b 120e 135a 15f8 167e 1622 15ce 1597 161a 14e3
34d1 3532 3565 3617 3691 368d 39f2 2cfc 15df 1408 14cc 1756 349b 38da 360d 35e0 35e2 35fd 358c 35e5 3623 363c 364a 36a9 39c1 22c3 111d 13ba 1559 14d2 14db 14f5 14b6 1669 1706 1723 15fd 127b 189a 3a66 3bb3 32cf 20b3 15ec 1686 179a 17fb 16d2 1543 14c2 1401 14f2 1450 2404 3c77 3940 3841 37d4 3824 381a 3853 38c0 38c7 3b95 37fb 194f 174d 1899 18e4 1933 160a 2e7b 3bc3 391a 3918 39c1 3988 3980 39ee 3a35 3b13 3c94 3e50 3947 3085 2b1c 2b3b 3047 3948 3dbf 3baa 3a72 3a38 39ba 3907 38ce 3926 3b3c 3565 1681 16b0 16f4 16ea 1653 167c 16a9 1571 147e 143d 14fa 1647 143b 13af 1489 1605 1679 159a 14b7 1530 1653 16ef 179f 1700 16b9 2537 3cb6 39b8 3999 38e3 3877 3819 381d 379d 3845 38b6 38f7 390c 3850 389b 3861 3848 386b 3817 3812 383b 36b0 36ff 37d4 3b92 277a 1270 12e1 131e 1518 1636 1557 15a8 15ee 1692 15b2
34fa 35b4 35df 3656 368e 3929 31ea 14de 1435 15fa 1629 1488 260b 3b62 3704 3660 3573 3501 34ba 356d 360f 364d 369b 390b 3703 15dc 1307 144c 1574 1587 1514 149a 144b 14e6 15e3 13cf 1893 259a 313d 2893 1d6e 1758 1718 17f4 17da 18af 187c 17c3 1571 141e 14ac 1611 1a5f 386e 3a5f 38ad 3835 3864 3851 37ef 381c 38e6 39ac 3995 3ce0 2955 14b5 179d 1777 1584 2449 3b50 399d 3869 3871 38e0 3926 397f 39d3 3a6d 3c5e 3c62 2a32 1d70 1a49 19d9 1a66 1a7a 1e3e 2bf6 3c17 3be2 3a48 3902 3823 37fe 38e3 3c9c 2ef9 1555 16af 171f 1781 1713 1684 16f2 15db 1443 1482 15d6 1583 13a1 12f3 1364 14cb 1600 160f 14e1 13f8 15a3 176a 188b 1865 1822 2093 3c14 3ad1 39b0 38d5 3868 3819 37d2 37bf 3839 3879 3922 3922 38ca 38f9 388b 389e 3855 3827 37d6 37e2 3754 372a 3787 38d7 3976 18e4 12ee 1343 149c 16bd 1695 1615 15c0 15cc 1587
361d 3656 36f8 3743 3702 3979 1d68 12e4 156e 167a 1641 1488 17a6 2efd 3ad9 365a 3593 358f 35b6 35e2 36f2 37d8 3983 3bba 22e6 139e 151c 150a 155f 1568 149e 150e 15bb 1548 122a 226e 386b 3cb4 3dcd 2669 147a 1919 1944 1906 1820 1879 1731 168b 14ae 1515 170a 167a 2645 3c84 3922 38ef 3833 3863 3879 38ad 38a4 3951 3979 3989 3b19 36f4 15b7 159b 16a2 2563 3aa8 3a20 3941 387f 3837 38b7 38ef 3915 398a 3b2e 3b20 22b0 18e9 1a76 19b7 1998 19c6 199c 1a35 193b 2699 3c36 39a2 3834 375c 3747 384e 3c1a 2098 1514 1586 159e 16a8 164b 16e8 16dc 1617 151d 1457 1234 1428 182d 19c0 1724 1269 1341 164d 15b7 1536 14c9 1698 1785 18cf 181c 201b 3bdc 3af9 3a0d 3944 38f6 3831 37f5 37fe 3876 3889 3901 392a 38e1 38e6 38af 381e 3770 37cd 3812 37e7 377f 3741 3716 37b1 3b7e 263e 1199 13f1 155a 1742 1775 164e 155f 162e 1601
3642 374e 37e8 3768 38c0 30d2 1234 13d4 141c 15e3 1625 15de 1641 180c 2d85 3ad9 38f5 379d 3702 37b1 3960 3b96 3b0e 252c 1402 1530 154b 14ea 15ac 1619 1539 155c 1509 12e9 23b5 3a9b 398a 389b 3a73 3386 151c 18ca 19b9 194a 180b 180b 186f 176c 159a 16cb 1869 180a 3358 3b85 391b 38d7 38a3 3897 38a7 38dc 395f 3a25 3a95 3c39 3de7 3b2b 2043 2419 33c5 3c35 3a0d 38f9 389e 3887 37e8 37fe 3881 3839 38d8 3bf7 2525 16ed 17dc 185f 1a57 19cd 1a0f 1996 1897 194b 1904 2e8b 3c04 3875 37f6 3873 3bc8 3138 1461 14e9 1580 155c 165e 16d6 1786 18bf 1600 137e 17d5 2903 3578 38ef 393e 37c8 2fb8 1df1 1227 158c 1534 1491 1640 1739 18b7 1845 243a 3d03 3a63 39f0 3956 38c4 3829 3808 37b6 3893 38d7 3920 396c 39dc 39a0 3972 3883 37c7 3788 3795 376f 3745 36f2 3643 3763 3acf 2f0a 1219 13a0 1420 163d 16ad 1672 1691 169f 15eb
36d8 37c3 374f 3756 39be 271f 0f7e 13dc 14c4 1586 1555 15a2 15b0 1524 1637 2365 3272 392f 39a7 3a28 37ff 2d9f 1cfc 1493 157c 158d 14f6 1450 15f7 162d 15df 1521 13f4 1d90 3a7e 386e 379f 3809 3873 3bd6 23d5 162e 1a9f 1a45 1981 187d 1882 17c0 1748 169c 1472 23ce 3b40 38d7 3840 3884 38b7 38ec 38a6 3902 398c 3a9f 3d8d 389b 2ab2 21d5 37ab 3de7 3bdc 39b0 38d9 38da 387c 3871 385b 37ec 3828 38b1 3b0b 33c9 175d 17d7 17f7 18c6 1a6e 19e7 18b7 18d4 1820 18e8 181c 1e2f 3a8b 3ad3 3a39 3d21 3689 1929 1443 1556 1747 169d 164b 15ff 16e9 173f 13fd 1f31 3730 3bd1 39b5 3844 378b 3815 3a91 3aa1 26ec 110e 14dd 15b7 1612 1766 1852 1814 2e2a 3cc9 3a65 3a30 39af 38bd 389e 3826 37e2 38db 3971 3a7b 3bed 3ca9 3cd9 3be9 3a01 385c 37ff 37cd 379d 3769 36cb 35f3 376f 3a08 313e 12f2 13a2 143e 14f0 16d1 1651 1606 15d5 15d8
371d 3746 36cd 3713 39f5 234e 0fa4 13a3 1668 1756 1569 168f 151c 14b6 1535 1522 17be 1ad2 1c45 1d85 1a0f 1683 15c0 15b2 15c2 1650 1513 14de 1528 1403 1392 1420 1435 2fe9 3b0c 3846 37f0 380a 38e0 3a9e 394b 1de8 14fe 18a6 18b0 1874 173b 1619 1482 1442 1eea 38be 3995 37c6 3796 3865 3919 394c 394e 39ff 3ada 3d1a 2d9f 1b80 17ea 17d3 3465 3c39 38b4 38f8 3914 3903 38e3 38e3 3863 37b6 3831 3969 3d3f 2653 15ec 17c7 18bf 1952 1974 1958 190d 18ca 1948 187b 183e 17fd 32ec 3fa0 3d47 32dd 1c0d 16c4 1779 18f8 18a4 1848 177e 170a 15d9 14d6 1dba 3a80 3aae 3872 3864 37e3 37ce 375d 3818 38bd 3bce 24ad 11ec 15d6 1795 1856 1840 1e0a 3b22 3c36 3abb 3a25 3981 38bd 38bd 388f 3857 3904 3bb3 3b70 3401 2ebd 2e9e 3385 3ae5 3c68 398e 3888 3811 3777 36ae 3666 3708 3a95 2fd1 1316 1387 1534 15e1 16fe 166b 1558 155d 168d
3678 36a2 36a3 36df 398d 25c2 0f92 13a8 15e9 1558 1504 1541 14e5 15c7 14f2 13b2 1333 1318 13d8 1524 1581 1614 15c1 167b 169e 1701 16c5 15fd 1567 1429 146f 14ea 1987 38cb 394b 3857 3743 3807 3911 3a0f 3bd1 3978 25b1 16bf 1446 1481 12de 1203 156d 250d 3934 3a9e 38ed 384e 37e5 382c 38c7 3904 3a10 3ac8 3df1 2c0a 17d6 1884 17aa 1745 2706 3c60 3859 3871 37f0 3843 389f 3888 387b 3871 386e 3ab4 39fb 1a78 16fe 17ee 18bd 1947 1880 1825 1893 178c 17db 15a9 179b 2128 2ea2 2d66 22e2 1845 165a 1703 17dc 1912 1862 17fd 17d4 1799 177d 175e 336d 3bc1 38bf 386e 381d 3836 3890 3811 37dc 3812 3965 38b0 16df 13eb 1659 16d3 182d 32f2 3cbb 3a95 3a68 3a04 396e 3861 38c2 38c1 3987 3bbc 309a 1da0 16e7 173c 1703 17bf 1e62 304e 3ca8 39ae 3892 376d 36fb 36c3 36a5 3b6c 275b 122b 13bb 14f4 15f2 1588 15cc 158b 1569 1589
362d 3656 3659 3696 3857 2e4a 0f12 1346 15b1 14d0 1553 1493 1471 13f4 138d 123f 12da 1260 128c 13c6 1453 13b6 1405 15c7 14fa 16e8 165f 154b 15ea 15fb 15f8 14f6 1f81 3b57 3882 380d 3750 3894 391b 39b9 3a58 3aab 3c30 3690 2b97 2684 26e0 2b23 359b 3b7d 3a29 3994 38be 3843 37fa 382d 38de 3957 3a67 3c84 3555 1951 1912 18e9 17cd 174a 194b 34cf 3c19 38a3 383f 3841 3845 383c 38cb 3893 39dd 3d7c 26dd 1604 16a6 1714 1862 18f6 18a2 18d1 1761 1617 155c 25cb 373e 3da8 30e0 13d6 166f 1848 174a 1693 1676 167a 162d 15a6 1538 1570 1614 21e6 3ce3 39f1 38e4 386b 388b 3881 3852 3831 3837 3888 3962 3d40 246c 11dc 1340 176a 2f5b 3c84 3994 3913 3930 390e 3926 390a 3913 39e8 3c56 2902 14b3 150c 1695 1710 16a3 1735 1718 1812 2c23 3c9a 38dc 37eb 374d 36d5 37d8 39dd 1995 11f1 12d4 1401 155f 161f 1570 152c 146a 13e1
3618 365f 3641 364e 36ce 371a 1642 1229 1591 1578 1591 14a8 13ae 13d5 14a1 1490 1445 1425 14e4 1554 1663 16d2 15db 153f 154d 1615 15b9 1615 15b2 169e 15d1 1580 22e1 3cac 38c1 385a 383c 38bf 38fc 39b0 39ee 3a06 3983 3a5c 3b65 3be8 3b91 3b61 3a24 3909 3920 3921 391b 3814 387e 388c 3915 397d 3a9f 3d33 2358 18f6 1a5e 19ac 19c0 1900 1825 1f4f 38c1 3d25 3a6d 3988 3907 38db 395c 3b05 3d25 2b13 1716 1756 1614 169a 175f 1768 1752 1744 16e2 160d 2e5b 3d55 3bab 3aa2 389e 175e 156d 18eb 18f5 182e 1745 1788 16f6 1606 1509 15d2 1636 2fe5 3d1f 39dd 392c 3936 3902 38ee 38f8 3934 38a3 38c0 3a90 3ed8 2dbc 1569 234c 357e 3bdf 3974 3921 3902 38e8 38da 3916 3917 398a 3cb0 2ee1 13dd 151a 165e 1698 1679 168b 186e 17dc 1720 187a 32cb 3adc 3774 36e3 3683 3ab5 2bf7 1187 1334 13d5 151e 16a0 15a3 15b7 1492 1486 12a6
35b9 35d2 35ec 3602 366f 3985 2bd6 10a0 14bd 15b3 1505 1459 14e3 1579 1630 1597 15ce 158d 156b 16da 1776 16f0 160b 15a2 161f 1784 17a2 1685 1656 16a2 1673 16c2 217b 3c27 38d8 388e 388d 38ec 38aa 38b3 3864 3852 3869 38cf 38dc 38d1 38cd 384c 3894 38c7 38fa 3964 38c8 389f 390a 38e3 3934 38ff 3a5d 38d3 19ee 199d 1a51 1ac0 19f1 19a7 1a23 19b2 1e90 30cc 3b97 3d50 3d2d 3d1a 3cd2 3761 2531 16d9 17fa 182b 1805 18a4 17cb 17ea 177a 171e 15b6 29a1 3da6 39e2 399f 393a 3c3e 263e 13fc 17e5 18b1 1947 18a6 18b9 1885 17fa 17f0 15bf 1fa9 3c42 3b4c 3a05 39b8 394c 3977 39f5 3a08 3a22 3a09 3c2e 362b 2946 2a1c 3a2f 3bda 3a76 38b9 3942 3951 3928 3928 3974 395b 3922 3a2e 390e 1983 1503 163b 16df 177c 179c 1779 1801 1796 173b 1658 2280 3b79 3751 3809 3b5d 32f2 1598 1387 14cc 14dc 16ac 171b 1709 1624 15d6 12dd 21c7
3558 360e 3633 3645 3711 37af 3a30 260a 11eb 142c 1493 1385 13f0 14b2 1620 1585 1570 14d5 159d 16cc 1690 15ed 15f2 15c4 16c8 1780 173e 16a9 1577 15f8 1639 1730 1b90 38b9 39d7 38ab 384e 384d 38b6 38e5 3860 382d 383c 37fd 37ed 380d 37f3 37fc 383b 3867 3990 398a 3906 38ae 388a 38d2 3985 39ce 3b87 3446 172a 1a2b 1a25 19b0 1905 196e 1899 19d0 1917 1a34 200b 272d 2ae6 28b0 22f6 1b32 17a0 173b 17b9 17f1 1869 185f 18cf 18dd 18c1 1816 1de0 3bb4 3b98 39b4 3959 39b1 3a98 398c 1cfd 15ba 1818 182c 17a5 1858 1898 183c 15b6 1941 35be 3cab 3b00 3a82 39b7 3964 39e6 3a47 3a99 3b07 3c21 2900 17d8 151b 22c0 3dba 39fc 38da 385b 3825 385c 38a8 3911 38e8 391d 3921 3c02 2c43 12ac 15cf 16a0 16ad 1738 161f 16c9 16ff 1653 166c 15cc 1758 370c 3c45 3ba2 2ff1 1719 12ca 15ed 14fb 148b 161c 17d0 16d2 170c 1536 23f4 3bef
3587 361f 3608 3642 36ad 376a 3813 39f2 2995 151c 108e 1140 138e 13c7 14ed 1572 15c8 1453 156c 1682 16ad 157c 15b7 1689 16c9 1718 16ec 16a9 155f 1613 163b 1720 17a0 2e2b 3c41 389c 3865 3890 38da 38c1 385f 38b1 383c 37d0 381e 380b 37e9 37ef 37e0 3895 397a 3943 3915 38bd 38d9 3983 399a 3a69 3c14 3446 16d3 19ae 1a83 197f 197b 194e 189c 1989 18de 192d 1969 184c 17b8 183e 1874 18b3 172c 16bf 178c 16d6 166e 1729 1779 17e0 177a 1757 2bc9 3d5f 3a0a 3a78 39df 3a43 3a2b 3bfc 389a 210b 169c 1637 16bf 171c 1562 14f7 1d44 3422 3c56 3a2c 3a54 3a5a 3a5d 39c5 39ec 3a4c 3b57 3cb8 25e2 15cf 167f 17f8 1ccc 396c 3b49 3923 383e 3831 37c5 37fe 385d 3866 38fa 3a44 3bf5 1c64 1346 1582 16bc 1701 1881 164f 1546 1476 13fc 127d 15d0 1f51 3014 2b2f 1e1a 146f 1429 154c 15ef 1552 1445 1557 1667 1729 168c 1d0c 3b0f 3ab5
3532 3582 3574 361f 36bc 374d 376f 37c0 3a13 36d2 2ab9 1bb0 10ab 12d7 14aa 14e3 150a 14fd 1605 15e4 158b 15ab 1609 16bf 17d1 175d 170a 1693 15f8 16ab 15e0 169d 1863 1d1d 38aa 3af3 3895 38e3 388b 382b 37e2 37e3 3796 3757 377f 381f 3836 37f7 37eb 383a 385b 3829 37c5 3826 38e1 3990 39ab 397c 3a51 378c 1810 1838 196f 1a44 19b3 199c 1a25 19ff 18d4 1893 183c 1780 16ab 15b7 164e 17a6 1895 1748 171d 173d 1681 159e 16a3 176c 17fd 1871 343a 3b09 3917 3952 395d 3999 39f0 3a2b 3b59 3ba8 30af 2497 1eb4 1e8f 22ab 2df4 3a1d 3ad8 38c2 3901 38e3 38eb 396a 3939 39a2 3a94 3d9b 2af0 159c 187c 1885 1908 1973 2b59 3e6a 3a88 3929 38cd 3886 38a8 3895 38fa 39fa 3d98 2b7c 1232 142b 1647 160f 16bb 18d5 17c4 163a 157b 15b6 26b0 378e 3e54 29b4 10ff 1269 13da 1555 15be 1616 1641 158d 1589 161c 1656 170e 2e19 3da0 399e
3543 3546 3573 3605 363e 3690 3708 3744 36c0 379a 3916 399d 2bea 1430 1295 14c2 1500 1572 160f 1607 160d 154a 15c8 15ca 167a 1591 164b 1652 15d3 16e7 1665 1588 16d6 16d2 20d1 391c 3bda 3917 37e5 3821 37ce 36e1 3683 368d 3715 374e 375b 375b 376d 37d5 37ce 37e1 3795 37a9 3800 3898 38ca 3971 39e4 3bfc 1f84 15fc 18d9 1957 1880 1826 1881 17f6 1785 171a 1693 17b2 1759 15d2 156e 174e 181c 178f 17b4 176c 170c 15a7 1581 15b2 1775 1956 368a 3ab7 38f4 38c0 38bb 38a4 389c 38f6 3935 3a36 3aef 3bb8 3b4b 3b1d 3c0d 3be0 3a66 3904 37e9 379b 37d8 37fd 3825 382f 38ff 3ae5 38c4 1a36 16f4 1738 1966 18e3 18e9 1b78 31df 3e47 3b12 38ea 38fe 3944 38e2 3a5c 3d12 3022 15c6 139f 13cb 1589 162d 1686 175b 173e 1641 17bd 31e5 3d5a 3a56 3bca 328b 146b 154c 169a 15f6 16a5 1788 1783 1751 172f 1680 164b 1ae8 39d4 3af7 391e
343e 34d4 34f3 3531 35c4 3648 3671 35c6 3607 3604 35f5 36d1 3a97 3151 13e3 145b 146a 1465 150b 1793 17d8 1547 1575 14bc 153e 1587 162c 1614 15dc 1651 1699 1610 15c0 168a 15c4 1d3b 2fe0 39f8 3b62 3990 37a1 3685 35e9 3689 36bb 3677 3650 3649 36a1 36cf 377b 3743 3701 3772 37f9 37ea 3844 38cd 397b 3bd7 30b2 15c9 16a7 17a4 1686 1663 1715 1808 1824 17ae 16ff 1682 1651 155a 15ab 15b6 1707 16c7 16f0 16e3 16ef 1590 14fe 154f 1602 1797 356f 3aa2 3909 38a8 3853 380d 3809 37cb 37fb 3870 385b 387b 3932 3985 3935 38dc 3846 37b9 374e 3721 3775 3772 378a 376c 3867 3b80 2d16 16ba 1811 16f8 1846 181d 175c 17ed 1af3 2d16 3b11 3d7f 3c9a 3c70 3c6b 390a 2817 156a 13e3 1452 1471 1597 15fa 165e 1617 1656 1549 306f 3d2c 396b 3886 397b 3afe 1de3 132b 161e 180e 1816 1751 17dc 1737 1787 1774 15e1 2a59 3cfc 3953 38de
3453 3474 34d7 34d7 350c 3612 35df 35bc 3596 35a1 3574 35a2 3680 3a65 2909 11c7 140a 149d 1586 1601 153b 141e 14ea 1595 1622 16aa 15e9 156c 151a 156a 15d8 1634 1540 1589 15ac 163a 1690 1bfd 2852 381c 3a20 36c4 365c 36df 36f8 36bc 36aa 3691 366c 36fc 3777 372e 36e0 3716 37aa 37d5 37f7 3790 388f 396d 3bf0 2742 1523 1761 172f 171e 1771 1910 18e5 18d6 175f 1642 16b6 15d8 1583 1607 1692 167b 1735 16d7 1706 1654 17c5 16c6 163c 1695 306f 3a77 37c4 37f5 3793 3775 3764 37bc 37b6 37a8 37bd 37e5 3867 38d2 38cc 389d 382b 37cd 37aa 37b5 37a0 37b9 37fd 37f5 38c3 3bbf 2481 164a 16de 162c 1695 16cb 1718 16dc 177f 1868 1e1b 270b 2a5b 28d8 233b 1a13 1536 14f9 155e 159e 156c 15c1 1667 1641 1610 1471 223e 3cbd 394f 3841 3835 38b3 3a71 33e6 15cc 1145 14da 16af 1736 176c 16a0 15d8 14c2 23a1 3b21 39f1 38b0 3836
3498 34ac 349e 34ba 34e5 3595 3585 3566 3526 3529 34e7 3529 357a 3726 3885 17f3 1387 14ec 14fe 1575 1430 13ee 15a9 16f6 165f 152b 1475 1421 143a 1572 1504 14f1 15c2 1636 15ba 15d3 1549 1621 157b 1bdd 327a 3a55 377f 376e 3748 374b 37a2 3772 3707 37aa 378e 3799 37b3 37a5 3807 3811 386c 38f7 38ec 390e 39ae 3bab 295f 1615 140d 1584 16d4 168a 173f 176b 1723 1755 1778 1709 1627 165a 1653 1615 16bc 1768 16e2 17af 180b 17ea 1686 1611 24f7 3cc0 38ed 387a 37a2 3802 37f5 387b 3889 3874 381b 381e 389c 3859 38c6 3857 386c 37ea 382b 3806 382e 3820 3856 38ab 393b 3c37 21c4 16b0 1803 16bf 16f7 161a 16de 175b 16b9 15f9 167c 16af 1637 1581 1531 14f3 1467 13cc 151f 1539 14d7 158c 15f9 16e5 17a2 149b 31b0 3b50 3823 37c6 37b0 37d5 37f3 3b03 3270 18c9 1153 12f2 153b 1611 1549 174a 27e8 3b2a 39dc 38ba 37ff 3833
33dc 3448 348a 3484 3450 3538 34ec 350d 3546 352d 34e5 34d4 3587 3610 3a44 2396 1206 14c0 1502 1612 14e9 15fb 1695 161c 155f 13d8 1308 1345 141d 1462 1488 1501 1670 1647 155c 1506 1606 163d 1780 1690 1afc 36f3 3a3b 3898 380f 37d9 3839 388e 3854 3853 3864 383e 387f 3854 37f4 385b 38bf 3938 3956 3951 3996 39b6 3bd5 352f 278b 1993 12fc 1482 1586 162b 178b 189d 180f 1707 166d 1660 16b1 174c 170e 16af 167d 1623 16ac 1791 168f 16af 1860 3521 3c48 38ca 38c2 3920 38f1 38bc 391e 38c1 38eb 3903 395a 38ff 38f5 38ca 3904 38dc 381b 37cd 37ff 38ab 38c8 3912 3975 3c7e 26b9 15f7 17ca 175b 1630 169a 17c4 179e 17ce 16ca 15d0 16e4 165f 15fc 15dd 16a0 1615 1533 1561 153a 1503 15b6 160a 16ca 178c 19b7 38b2 39ab 3825 381e 37d9 380a 3875 3949 3bd0 39a5 2c38 219e 1f00 21c3 2a4b 36cf 3d9f 3ad8 39a0 38dd 388d 3862
33c9 3490 3535 34b4 3520 35b5 35a9 3540 35a7 356f 357e 35aa 364a 3663 39a0 2af7 129e 156c 169c 166c 1597 162e 1632 15dc 16ca 1682 15dd 1433 149f 15b3 15e6 173d 1742 176b 16ea 176e 189a 180c 1821 17d3 1753 2449 3c48 39e5 39b2 399c 3934 396b 3935 3916 38fa 38dc 3930 395f 3912 38eb 3938 3986 38e2 38cc 38d5 38bc 38fa 3aaf 3cbd 3a85 28f8 1548 1559 1602 16c0 17a8 1828 1778 16d7 178b 17ec 1883 182c 17c3 172d 1731 16ff 165e 1646 157b 1698 1e47 38bf 3ca5 3a4c 3a1f 3a50 39c7 39fb 395e 392b 3921 3984 3936 394e 3920 390a 3916 38b4 384d 386f 38b8 38d8 392b 39d0 3b94 3114 1596 174b 17a7 166b 15a5 1663 160b 1731 16d7 1600 17ad 1730 1601 1631 1622 1609 15b9 15e4 1592 15bb 15ee 15cf 167a 176a 1db0 3b07 396f 3857 387e 38b7 38e7 395e 395a 39a4 3a77 3c8a 3cc1 3cd6 3d68 3dbc 3c85 3b3a 3b03 3a6f 39bf 3944 393d
367f 3567 3596 37ad 3916 37ab 3699 3676 35e5 363a 36ac 369d 36fa 374a 3a5c 2d79 138a 1662 16d4 157c 1508 154a 150a 1499 1581 15a6 14fe 1489 15dd 1745 176d 186b 1808 17d6 176f 16e1 180f 17f5 1815 1786 18a0 1a7d 366b 3bc3 3a87 3a9d 3a09 39b9 3975 396c 39a3 39d3 39fe 3a51 39f2 39cf 3986 3981 395a 3907 386c 38b2 394f 399d 3a2e 3b3a 3e6a 2d5a 17b3 1799 1664 1603 16ff 176f 1831 1881 183a 1802 17d8 178a 173e 1758 178d 183f 18b9 1810 1756 17c5 1df9 3206 3c98 3e64 3cc7 3ae9 3a29 39fd 399b 39cc 399e 395f 399e 39b8 39ed 396a 397d 393a 38e6 38c2 38cf 390b 3a0f 3aaa 3b40 1dcc 1613 182b 1746 16c0 16f2 1728 16b1 1704 15f6 1736 16d3 160e 1652 16bc 158c 1524 1569 15c6 154a 1573 1585 16fc 16b7 1d75 3b64 3a4e 38d9 38a5 3881 38d2 38e6 38f2 396f 39b8 3a1a 3a69 3ad4 3ae2 3b20 3b16 3b5c 3b2f 3acd 3a0f 3a1e 3a3b
1895 1509 1596 1af6 2659 34cd 39e3 3733 370f 3670 362b 363f 36e4 36b1 3adc 299f 13c5 155e 1480 1484 1449 1482 1461 13f0 142e 1469 14d0 15b7 1663 175f 15cb 15db 15b2 1563 1640 16a6 16d0 1754 17d6 18b2 196f 1849 2e81 3c7f 3a84 3a5b 39fe 39af 3970 399b 39f1 3a56 3a97 3ab9 3a09 3a53 3a35 3989 3926 394a 3929 3962 397f 39ca 3a2e 3a13 3b02 3e15 25b7 17db 1883 17b1 1724 17ae 186b 1866 1840 17c8 180d 17e5 1730 1792 16d0 1768 1890 1918 188a 17f7 181d 1acc 211e 2c36 3aca 3dfd 3b72 3ae7 3a87 3afe 3aa2 3a4c 3a32 39b1 39e2 39e0 39a5 39fd 39d2 394b 397d 392e 39c8 3a69 3bff 3411 16f0 15dc 17c0 181e 182b 1847 1742 17a0 1663 16b3 173f 1659 1636 1712 15e2 157f 1515 14cb 1536 153f 1572 16af 16a6 1aa0 37f7 3b1e 38d5 3907 390d 38e0 38ed 38d8 38ba 38f1 38ec 39ce 39ca 3a3b 3aab 3ab9 3a77 3ab6 3ac3 3a05 39be 3a3b
0d54 0e1c 0f11 1141 1290 17a3 2b75 3a3b 37a5 369f 35ef 362c 36db 37af 3b33 201e 140e 14f2 1406 14fb 1515 147b 1461 13ef 13ce 146c 13eb 128a 121c 131d 12ae 12c9 14d2 15d1 1604 1758 17f0 175c 1814 18eb 193e 1847 2c3e 3cfc 3a22 3a0f 39c0 39c3 39ea 3a0c 3a0b 3a77 3ace 3aa4 3a70 3a96 3a1f 39c8 39fa 3a1d 3a03 3a9d 3a3b 3a19 3a44 39f3 3a23 3c9d 35f3 1857 189d 184d 16fe 1724 17b6 183d 1809 188d 18a5 1900 1845 1831 17fe 18ad 17ad 189a 190d 19bf 1916 19b2 19af 194f 2038 355a 3d4a 3ae2 3ac7 3af3 3b43 3b22 3a88 3a2c 39cd 39e6 39c9 39b2 399c 3a21 39ee 39d2 399c 39f7 3a7b 3cae 3313 1b61 13a4 15dc 1828 1841 17cb 1714 160a 162e 1659 1739 1726 1746 1658 1671 1568 1516 15a7 15e7 1643 17c8 17d6 174f 2d8b 3ce2 3859 3856 38e0 38bb 38e1 38cf 389d 3909 3934 397e 39ea 3a1c 3a09 3a96 3a61 3a61 3a74 3a0f 39f4 3a15
0e4c 0f1e 105d 11d3 1432 1499 154b 2a6b 3a4a 3676 35e3 362f 36e9 3a25 3568 15f4 153f 159a 14fc 1680 1729 1686 167c 1619 15a1 1319 1647 22bb 2a7c 2ddb 2b0a 2342 17be 14d1 16ad 17d2 1907 18f4 191a 195b 193d 191e 2de4 3dda 3a8c 3a67 39c0 39b8 3996 39a2 39d4 3a8b 3aa9 3b23 3b44 3ba9 3b84 3b59 3b07 3b00 3aff 3afa 3aad 3a4c 39bf 3a14 3a7a 3a95 3c4a 1de7 16f5 1872 1813 1793 17cc 187d 1997 190b 18b3 1a21 1a2f 197c 197e 19da 1977 18f1 1921 1a86 1aa9 1b7e 1ad2 1abd 19fb 1e81 38da 3c8b 3b4d 3b35 3af5 3b03 3a1d 39d3 39c4 3981 3952 3981 3997 39c5 397b 3944 394c 39be 3a96 3b33 3d4f 3acd 2ec5 210d 16ba 174a 1808 1771 15bb 1547 15ae 1657 16ec 179d 1785 17ee 1614 1482 14f9 15bc 1651 1850 17ed 17d6 1dd6 3a24 3b52 38ee 38e8 3963 3921 3905 3887 3944 39b2 39c5 39ef 39ef 39dc 3a93 39f3 39f3 39e0 39d8 39fa 3a54
0f27 0f48 0ff5 123b 13de 1646 16bb 17a6 32e5 38dd 368e 3775 392c 3be8 21f3 151b 170d 17ac 1825 18b1 1938 1983 18c8 169f 146f 23a6 3720 3c08 3b82 3b14 3bc8 3c43 3801 2496 13e5 16ea 182d 19b2 193e 1936 1a40 19b0 343d 3c49 3ac1 3a54 3a19 39ee 3a37 3a33 3a66 3adc 3b70 3c26 3c23 3cd2 3d09 3cc5 3c31 3be7 3bc4 3b22 3a74 3a5f 39cb 3966 3a07 3a2a 3d73 21e7 16f8 198a 18dc 1877 186c 192c 19f9 191b 193d 1a9c 1a25 19d6 1af5 1a5b 1aa1 1a0a 19df 1a61 1b12 1bed 1c60 1c81 1b43 1a9d 2767 3e6d 3be8 3ba4 3ae1 3a8b 3aa1 39f3 3993 39b6 39b7 3999 39a0 39b7 39ec 39a2 39e5 3a2a 3a34 3a71 3b18 3b4a 3c79 3d33 30b2 1a86 168b 17f6 16b3 1567 167d 1728 1729 1723 185f 18b3 17b5 158f 1492 14ef 156c 175e 1866 18f5 1929 2418 3b90 3d5b 3ac2 39a2 3960 38f0 38d1 3927 3987 39c9 39b4 39a5 39bb 399e 398c 3993 39b3 3a2e 3a0e 3a5f
0fa2 0f99 10b2 1222 135b 149b 16cd 1688 23f3 3ad2 3878 3b10 3c30 26ef 15f7 1732 17f7 180e 18d5 183a 1879 17d5 1690 1452 2905 3c39 3ab0 38c3 3852 387c 38a2 3873 39d4 3ca8 2898 13fa 1888 1a2a 198c 19fa 18ef 1f72 3b8d 3a58 39f1 3a0c 3a28 3aac 3a15 3a79 3baa 3c31 3c9c 3edd 3e80 3cbf 3c6a 3d0d 3ee7 3e64 3cd4 3c52 3ba8 3ad0 3a32 394c 39fe 39e8 3cda 229f 17fa 1982 1965 18e5 18ef 19fc 1a49 18e1 1836 186f 18aa 17f4 1875 1851 1839 19e1 19e6 18e8 1aa2 1add 1adc 1c09 1c49 1c05 1dd5 3961 3ce9 3af8 3ae2 3ad9 3a4c 3a0d 39ff 3a05 3a68 3a55 3a21 3a7e 3a8a 3a32 3a6b 3a6b 3aa9 3ac3 3a5c 39e8 39e8 3a0a 3d3a 343d 17bf 1713 184b 165c 1698 17bd 18c9 1842 18a0 18e2 17c4 1648 150c 15ca 15fa 15a6 1730 17f1 18d5 1957 2193 332f 3c4d 3d2c 3a8d 39aa 39aa 39d1 3a0f 39fc 3a02 39e4 39d1 39cb 397d 3949 39ea 3a57 3a83 3a59
0e6b 1026 1062 10fe 12c8 148a 14b8 14bb 1887 39e7 3cf0 34e3 2223 1600 17dd 18b5 191b 190d 18b4 188c 1726 15fd 1552 2470 3c5b 399a 3893 3871 38ab 383d 3893 38f7 38da 3a3e 3c8e 2036 151d 19a6 19e8 19a4 17f5 31c8 3cae 3a39 3a3e 3a2c 39ee 39fe 3a28 3b96 3be5 3ddb 3d51 31e6 25c6 21a1 214d 2241 2968 36f1 3ec5 3d1d 3c20 3aef 3a11 39d7 3a9e 3af1 3cf3 1fea 184c 1905 1906 1895 186b 192b 19ec 1a31 1a02 19e9 1881 187f 1803 1833 1816 186b 195b 1908 1933 1b3e 1b09 1bbc 1c0a 1b8e 1b2c 3244 3d92 3b05 3a7d 3a25 3a7c 3a98 3a54 3a79 3a75 3a4d 3a9a 3a8f 3b15 3ae8 3b01 3aa1 3ac6 3acf 3a04 39ff 39e2 39c0 39f1 3df9 29e7 1557 18e2 17aa 1673 175e 1914 19cb 197d 1867 1798 15f5 1581 15d3 15dd 14ca 15e9 1651 1739 18d1 186c 1a0d 1f40 2c66 3b83 3ba9 3a8f 3a35 3a05 3a0b 3a40 3a59 3a4b 3a3d 3a22 3991 39c6 3a47 3a45 3aa8
0dec 0f09 0f8f 11b3 138b 12c4 15fb 213d 2d1a 2a72 1fb5 19c0 1756 17d6 1953 1a55 19c5 1980 18c9 17f5 17d7 169f 1930 3711 3a59 3814 37d8 3835 3881 3876 38b8 3921 38e4 38f8 3bcc 3359 1596 1930 1987 17de 2b4e 3d74 3b38 3a82 3a31 3a24 3a6a 3a2b 3a79 3be8 3e05 381c 22f8 1ae1 1af6 1bb5 1c69 1bce 1b5f 1d19 2e1f 3e64 3c47 3afc 3a33 39f4 3a43 3ca2 3811 18be 196b 193d 1941 1940 19cb 1a53 1a21 1ab0 1b73 1af9 183a 164b 15f9 151e 15b5 1770 1918 19bf 19c6 1b58 1c0e 1c58 1bb2 1c5c 1b87 2f24 3da5 3acc 3a37 3a54 3a7b 3a83 3ad5 3acb 3a1f 3a73 3a9b 3ad4 3b3a 3b43 3b0f 3aa4 3a71 3a7c 3a80 3a17 3977 3a0c 3a1c 3c40 380f 184f 17f9 16a2 164d 1801 18c5 1941 195b 189a 189d 171c 16ee 1769 171c 172b 176a 1848 1850 1887 18a1 1868 17af 17fc 2321 3aa4 3bb6 3a56 3a31 3a4d 3aa0 3ae9 3ac3 3a88 3a70 3a08 3a19 3a60 3a3a 3ac6
0d56 0e44 1035 11d7 108f 1f2a 349d 3b9b 3dd0 289d 1444 17a1 1814 1959 19ea 18cd 174f 1787 17fa 1784 176d 15e0 22e9 3bf9 38eb 387b 3879 38a4 3889 3899 38e7 3949 39be 393d 3aa9 3cb5 1c19 1449 1c64 30d0 3d70 3aca 3a84 39ed 39b2 39d0 39c6 39fe 3ac4 3cf0 39af 1e7b 19af 1bac 1c32 1d74 1d04 1bfb 1b91 1b35 1b69 2f2c 3db5 3ae3 3a4a 3a1a 3a9c 3ea8 28b2 170d 1946 1989 18d9 1910 18c0 1965 18c0 18c3 177a 1937 2540 2dda 3230 3121 29d0 1d89 163a 1779 1877 1993 1a98 1aad 1bb4 1b4e 1b67 326d 3e18 3bb3 3abc 3a9c 3a3e 3a61 3af6 3aa9 3ab1 3abe 3a77 3aed 3ade 3b4f 3b0b 3ac8 3a5b 3a65 3ac7 3a2f 3949 39b0 3a6f 3a83 3c56 1eb5 165e 166b 164d 1887 195f 1985 19dd 17c3 1747 1792 178f 173c 1703 1693 17c5 1837 1808 1814 18d5 183b 1737 17db 18a3 2608 3cbf 3a8f 3a19 3a78 3ab6 3a8b 3a6d 3a5a 3a2b 3a37 3a79 3a81 3aaa 3a8e
0d81 0ee7 10a3 0f3b 204f 39cc 3964 3783 3949 34c7 169a 182e 1932 1a14 1a08 1906 1863 18ed 19fb 19d6 1910 17aa 3195 3c2a 398e 3958 3963 3918 389e 392d 3956 399a 3a34 3ca6 3d44 391f 2c11 2e79 3a0a 3caf 3a95 39f1 3a09 3a1b 3a43 39c1 398f 39f1 3acd 3dbd 25b1 17d8 1b69 1d4a 1c51 1c69 1ca8 1bea 1c38 1b91 1b29 1d48 3840 3b8c 39ad 3a5b 3e00 3460 1989 1823 197c 1a35 1956 196c 194f 1963 1a50 1812 24ea 391d 3ea3 3dc4 3d29 3d9b 3e42 3c0c 2b1f 1658 1824 1a0a 1aa5 1b5d 1b5e 1aec 1c98 3962 3dad 3c44 3b73 3b1b 3aee 3b88 3be7 3b8e 3bc3 3b72 3b63 3b81 3cad 3d52 3c2a 3ae9 3aea 3ab5 3aaf 3a72 39b5 3990 39af 39ec 3d30 215d 14ac 160e 1712 1882 1983 19a8 1931 178f 159d 15eb 1617 168a 16e1 172d 16f4 177a 1764 17cf 1964 186b 17a5 17f0 1911 1ab7 345a 3c53 3ad5 3abe 3a6c 3a26 3a2e 3a68 3a08 3a29 3a4e 3ac7 3af2 3aab
0ce6 0de8 0e9b 185a 384c 37c5 3686 3706 378b 3c10 2656 14c0 1925 1993 1a73 1a50 19bc 18e5 1881 1948 15ff 242c 3c9d 3ab5 3a14 3a50 39ad 3957 3986 39b3 39ea 3ab0 3d37 3405 22e6 1a43 33a4 3e0f 3a94 39be 39ad 39c7 3aba 3aec 39ae 398a 39da 39ce 3bf0 371d 1917 1961 1a85 1af9 1ae9 1adc 1a29 1a8b 1a7a 1aa2 1bc2 197f 2b21 3e2a 3c7f 3e75 346e 1abd 18d1 1a3f 1a7a 1a2f 1aa4 1afd 1abb 1a08 187b 2722 3dbb 3dae 3b8b 3b48 3b65 3b75 3b81 3bec 3e8a 2e32 16b5 18bf 1948 1b33 1ca0 19c1 26cc 3ef8 3d4f 3c93 3c1c 3c6a 3bbf 3c39 3cc1 3c95 3cd7 3e00 3d8a 3927 35d1 36d7 3b7e 3dcf 3c25 3b10 3aa7 39df 3971 38ae 38c1 3998 3cb8 20f4 13fd 1575 1660 17d5 1939 1948 194b 185f 16db 15e4 14d8 14c9 1551 1702 1798 17a9 1752 17f3 18a9 194d 18f0 1944 1942 19dd 2944 3dd5 3b7f 3b1c 3a5c 3a43 3a92 3ab3 3a71 3a89 3ad6 3b44 3b56 3b4a
0beb 0d11 0eba 2bbf 3925 35e1 35ce 368a 37a4 3a32 3aba 208d 157f 19ae 1afc 1b29 1944 17cd 15fe 1436 2048 3a16 3b47 39f4 39ac 39e5 398c 3a2a 3a4f 3a2d 3b23 3d83 2adc 1928 1866 179b 2903 3d28 39aa 3966 39a9 3a73 3a36 3a17 3a0f 3a76 3a92 3af3 3e6f 2b02 17bf 1a87 1a3b 1a1d 19b6 1917 19ac 1a7a 1ad8 19fb 193e 16ed 2242 3d56 3800 291e 19bd 178b 19bb 1ac6 1a9d 1af4 1a98 19ac 19b9 1908 1fa5 3bfd 3bee 3a8b 3a15 3a57 3aa0 3a48 3ab6 3aee 3c0b 3ee1 2510 179b 1a48 1b58 1b06 1cad 387a 3e06 3d29 3cb4 3c23 3bf1 3c5b 3c93 3cbb 3d43 3e8d 3445 2438 1c0b 1aaa 1b0d 1ed3 2b75 3b38 3cc8 3aa5 39a7 38f6 38b5 3978 3a10 3ad7 1bea 157a 16bc 1736 18c7 1946 1915 17df 1749 165c 1641 15b7 1575 1470 1561 16a2 16a7 1659 1738 17de 188c 1939 19df 197a 192e 2317 3cf8 3a8a 3ab1 3afd 3a9b 3acd 3b18 3ab8 3b08 3b07 3b4d 3b34 3b0f
0bdd 0c78 13d4 35e2 36ae 3604 3628 36cc 37d3 390e 3b04 3b73 2950 1a4b 1742 16d7 1556 1477 1746 26c9 3a41 3b34 39fb 39ae 39ab 39d1 39f1 3a80 3aba 3b16 3e0f 2d87 1892 1a48 189e 1761 1c41 3954 3b6e 3964 38d6 3941 3916 3961 39dd 39ff 3a4f 3c77 3a91 1c4c 190e 1a52 1ae5 1ae0 1a83 19ba 1a38 19e1 192a 18ba 21e6 301f 3665 21ad 1ad0 1893 19eb 1a6d 1b11 1afd 1ae3 1b94 1b40 1a8c 1abb 1966 3208 3df3 3af9 3a7c 3a5d 3ab0 3ab5 3b0e 3af4 3b35 3b96 3e25 3669 17b2 193a 17db 1c61 354e 3e15 3ca2 3ca8 3bc1 3b8e 3be0 3c87 3d2d 3d97 3d92 294d 1b18 1a9d 19c6 19cb 19a8 194d 18fc 2284 3a2d 3be1 3a38 3986 3917 39e6 3d42 3390 15b5 16de 1768 17fc 18cf 19f8 195c 1877 17b0 156d 13d0 1454 16b4 1627 1560 1370 1402 1672 1710 1825 17e7 1a08 1b60 19a3 19ef 2386 3d31 3a62 3a56 3adb 3ade 3a9e 3aec 3acc 3b0f 3b37 3b3d 3b32 3b67
0c05 0b5e 1a88 38b7 3619 3642 3633 372f 37ae 38dd 397d 3b08 3d5a 390e 3002 29f2 290d 2d48 372e 3c69 3a46 3959 390e 3916 39d0 39bc 39f5 3a3a 3b4f 3cae 380b 1b17 1957 1985 18c4 17c9 173d 2572 3d11 3bab 397f 387f 384a 389b 3944 396d 3b66 3cfc 2513 1734 187c 198c 1aeb 1b97 1b69 1b17 1a63 1900 1956 2f6e 3d5c 3d87 3e67 213a 16e3 19cb 19f1 1986 1965 19de 1aa6 1aa7 1a94 1a69 1a2d 1e97 3bf7 3c79 3ba6 3bec 3c0c 3b87 3bb6 3be8 3b88 3bea 3c2c 3d84 3e20 1b36 1766 25e3 38b1 3e76 3c78 3c4d 3c27 3bd2 3be4 3c1e 3cac 3d76 3e58 28be 1935 1c74 1c28 1b1b 1a38 1999 19f6 1a03 18c1 2406 3cca 3b95 3ac4 3a3e 3bb5 3e1d 220f 1622 185b 16e6 1818 1885 19e2 1a85 1943 1764 1631 2427 326a 387a 396a 37a3 2ebd 1d57 12f2 165e 1788 1787 19bd 1c09 1afd 1a58 27c5 3e5f 3baa 3ad4 3a52 3ad9 3ad0 3b09 3b1e 3b8a 3bd5 3c3d 3c1a 3bd4
0c2c 0cc2 1daf 391e 3635 3638 3606 36e2 37a1 38c5 39be 3a63 3aea 3c61 3ca9 3d17 3c54 3b62 3a3e 3979 3908 392d 3928 392a 3957 393d 398e 3a0e 3ac1 3d83 292a 17c1 19ef 1a02 1a34 1948 183c 17c1 26c3 3b14 3d2d 3b2e 3a64 3abc 3be9 3dcb 3aab 250c 1764 194e 1a86 1aae 1b40 1b49 1a40 1b77 1a40 188a 3212 3ea2 3b3a 3af4 3d33 2fd6 1663 1999 1be4 1b45 1b26 1a7d 1be7 1c28 1c25 1b83 18ed 2b88 3ed8 3c8f 3c1e 3bc0 3beb 3bc7 3b25 3b7e 3c19 3cff 3ead 3b25 327e 30fe 37c6 3dcc 3d5b 3bf7 3b4e 3b87 3b9f 3b4c 3b5f 3bb3 3c72 3e92 32b7 1a42 1b2b 1ca7 1c40 1b06 1a82 1a89 1a1b 195a 1a14 19f7 3169 3dd0 3b6a 3c55 3f06 2ab0 1672 1808 19b4 18c7 193b 192a 1a00 1a2f 190b 1be6 33d1 3e41 3c5e 3b2f 3a5d 3b4a 3c99 3c56 2828 12c0 1624 180b 1900 1a38 1b68 19e5 32e1 3e7a 3bb3 3ab8 3a33 3aa6 3ad9 3b64 3b9c 3be2 3cb6 3cf7 3d87 3e63
0ce3 0d44 1af4 3965 36c0 370c 3690 373a 3833 3920 395e 398f 39ce 39a9 39d4 3970 391d 38f1 38b8 38c5 387d 38b5 392a 3965 3966 3994 39bb 3a14 3ad0 3c6d 1fe6 18af 1a38 1a80 1aa4 1a42 1925 1825 172c 1ebf 2dd1 3733 3ac9 3aec 36e5 2beb 1d14 1681 17bc 1802 17e7 17be 1887 1805 1795 17c7 16b1 2804 3e36 3b10 3a4d 3a5c 3b13 3c43 20f8 166c 1a2f 1b01 1aed 1afa 1aa1 1ad6 1a87 1802 2037 3b9c 3cbf 3bec 3b46 3b3d 3bc6 3c48 3bfc 3c13 3dbe 3db5 2c8b 1df9 199c 35ea 3ea0 3b73 3b4a 3b34 3a57 3a40 3a7e 3a84 3aea 3b49 3c57 3e0d 22e1 1a60 1af5 1b5a 1bba 1a96 1a98 1ab8 19f7 18db 1986 1999 2483 3f45 3f00 3c93 2969 1719 1771 17b7 1857 182c 16af 1768 1804 1831 1c33 3693 3e10 3a88 39fe 39a8 394b 398f 3991 3ab2 3d55 24d5 12de 169b 17e4 1961 197e 224b 3d5f 3c94 3bca 3b96 3b59 3a98 3afa 3b82 3bd9 3cd4 3f21 3d28 3662 30a5
0da7 0e24 14f7 3636 383b 36f1 36fa 37b0 3839 3885 38cc 3931 39aa 398f 39f6 39b1 3937 38e7 38ea 38ec 38f8 38b9 394a 391a 390e 396a 39c9 3a17 3b14 3ad0 1c32 1941 1b1f 1ab3 1a6d 19f2 1911 17f9 1774 17b0 18bf 1c09 1e5d 1cf6 1a22 181d 17d2 17f1 185c 18e5 18b7 181b 180f 17dd 16ad 16a0 1919 3782 3ba7 39aa 397e 3a48 3a9e 3bc4 396e 1f44 16cd 1a06 1a69 1b51 1a2e 186a 1711 1f3c 3783 3db2 3bce 3b55 3b5d 3b9c 3bc6 3ca4 3cd9 3d8b 3c79 25a6 19f4 1a89 1976 2c4c 3ef1 3b23 3ad7 3ad4 3ab9 3ac8 3a5c 39df 3aa1 3aec 3dcd 3620 1a19 1aa4 1b91 1acf 1b49 1b80 19c5 1a91 1abf 194d 176c 1b8e 2744 3612 2d53 1ef5 172d 183c 1965 191d 18b9 18ab 1669 16f6 190b 1896 3169 3ed7 3adc 39e4 39be 39f0 39de 3997 39d3 3a07 3b7a 38e3 17f5 1558 16ec 1691 1b8c 36d4 3ded 3c58 3c01 3c10 3b9c 3b10 3b9a 3bdc 3ca6 3dc3 306f 2132 1aa6 18d6
0df2 1035 114e 2af0 3b55 376c 376d 37f7 38d4 38ec 3954 39a9 39c4 395c 393c 3914 393a 38e6 393c 3937 3912 3924 397c 3962 3936 39c0 39ff 39ca 3a73 3b5e 1d6c 18cb 188f 1851 18d7 18e4 183c 1849 185d 17d1 17ab 188f 1846 180b 18c6 1849 17f1 189c 19c6 19ba 19ba 1959 1978 18ce 17f9 1892 2166 3d0d 3ada 3a3c 39e4 3a65 3aca 3b66 3d54 3c60 2c62 1d60 18aa 18f2 1873 1cb8 2ad6 3b68 3d65 3ba5 3b0a 3ae6 3b2e 3b98 3bf5 3c54 3ce8 3e2a 26a2 19c6 1bf3 1b4c 1a0c 1f3a 3b68 3dde 3b70 3b80 3b42 3b25 3a98 3a86 3ad8 3c1a 3dd3 23c5 1903 1b16 1bb9 1aff 1b11 1a68 19dd 1954 18bb 1bdb 2f02 3b5f 3da9 1f05 183e 196d 19bc 1a76 1b07 1ac2 1a41 19e9 1843 1685 17f4 204c 3d6e 3c9e 3a5c 39dc 3a38 3a39 3a00 39e9 3a6f 3a74 3aa6 3dec 2368 1219 14e9 1cac 354f 3e09 3bd6 3bc2 3b98 3b80 3b62 3b7e 3c88 3d73 3da2 2772 1870 18d7 1947 1873
0e38 107e 1268 1a11 379c 3ac8 37d1 38ad 38bf 38fb 3967 392f 393c 391f 3953 38fb 393f 38fd 3921 38d1 3884 38f6 3985 3949 3936 39a6 39b5 3977 3a05 3cb4 225d 1629 19bd 1906 19c1 1a23 196b 1945 193d 18b3 1818 17d5 1814 185d 1a1b 1b2e 1b1f 1aa3 1aae 1a9f 1a24 1a29 1adf 1984 1994 19d4 26fe 3df0 3b5e 3a8b 3a6b 3a5a 3a42 3b84 3be0 3c8f 3e23 3b71 3620 3451 365d 3bed 3e95 3ca9 3bef 3b57 3af6 3a71 3aaa 3ad4 3b93 3c07 3e64 32eb 1ab7 1d84 1cc6 1cdc 1aec 1921 26b0 3db2 3dde 3c37 3bb5 3b3d 3b4f 3bb8 3d38 3e47 289a 177b 199c 1a33 1c14 1c3d 1a9d 19da 19f1 18f5 1fcf 3974 3f37 3d6d 3eeb 25a8 17f8 1a67 1af7 1b6b 1b7f 1c48 1ba2 1a4e 1989 17b0 17e8 2db9 3ec4 3bd7 3abb 3aac 3a89 3aa4 3a40 3a59 3ac4 3b15 3cc5 3fbe 2ce5 1b8e 2b70 3b05 3d72 3bad 3b6c 3ab8 3acf 3b2a 3b2a 3b58 3c7f 3eaa 2903 17c4 195d 186b 1854 1796
0e18 101f 1345 15a1 2004 38c1 3c3d 3a9e 3965 3a09 3a3c 39c0 3900 38db 391d 38b6 38c3 38c7 38b7 3890 38d0 38ed 38f8 38ba 38f3 3940 3943 38f6 396d 3b6d 3031 15a2 1945 18d3 1883 18ff 1936 18f0 19c2 1910 18d9 18e5 1984 1996 1a3e 1ab4 1b18 1b39 1aa5 1a0e 197f 19d8 19c2 18fb 1af2 1a57 27ca 3e27 3b65 3a7c 3a38 3a9e 3aff 3b1d 3af8 3b28 3b55 3c29 3d36 3d71 3ceb 3c80 3c50 3ba2 3b04 3a5f 3a94 3a1a 3a61 3ac9 3b2b 3bc8 3e83 2540 1a1b 1cd3 1d63 1d4c 1b24 18d3 1941 25e9 3964 3ebb 3e64 3dd5 3e54 3f00 3a3d 26a0 17e1 19a1 1944 1975 1a55 1b9b 1a9f 19e9 195c 1bf0 38b9 3dca 3ae1 3b52 3d51 34b0 17c9 1a52 1a07 19f6 1a38 1b09 1bae 1b4f 194f 1876 1df0 3b11 3c47 3b6a 3ad3 3b19 3afc 3b35 3b12 3b15 3c4b 3d7d 357f 2748 2d52 3db2 3dfe 3bb6 3a8d 3a95 3a9b 3a0a 3a1e 3a4c 3a81 3aab 3cfd 3558 194e 1aaa 1974 16f5 1794 1841
0e15 1076 1414 1690 15df 1dca 3069 3b00 3d00 3c44 3aa0 39ea 3897 38f1 394e 38ba 386b 384e 385a 3838 3881 38cb 38cf 38c7 38d9 390b 38fa 3901 3949 39e3 3be0 2081 15d1 195a 18f7 199a 19a5 1a24 1938 1898 18df 18f7 1826 1985 1a1f 19b9 1a17 1a14 19f6 190a 1969 1913 1896 1961 1ae1 19fa 254f 3e3f 3b77 3abb 3afa 3b2a 3b2c 3ae2 3ab6 3ac0 3aa6 3af4 3b57 3bc5 3bc9 3bd2 3bd0 3b67 3ae0 3a0b 3a49 39d8 39d6 3a69 3aaf 3bb0 3bfa 1d65 19f4 1b3d 1b12 1b93 1abf 1925 1917 18ba 1d31 2753 2f6d 31ec 3007 27cd 1c92 187a 18f9 18fd 189e 17e3 18dc 193a 1a41 19fc 185f 2de5 3ead 3aeb 398d 3a4f 3b6b 3e5b 2adf 17c0 19be 1abf 1b06 19d2 1a59 19e2 17c7 19ef 34ac 3d2e 3b43 3a41 3a28 3a8e 3b26 3b69 3bb2 3d02 3c51 27d2 1819 150a 247f 3ed8 3b9b 3a32 39c4 3a15 3a12 39c1 39fa 3a10 3a87 3b1b 3e12 2595 17fb 198d 184c 17fe 18ad 17e1
0f0e 11a5 149e 1661 1762 183c 19fc 1ee3 280a 365a 3cbb 39f1 3984 38f0 38d7 385b 3823 3857 38a1 387b 38ad 38a9 3889 38ee 38cf 38be 388d 394c 3a06 3ac2 3c0d 38de 1d6c 170f 196d 1997 19c8 19a3 19fa 19c8 1989 194f 18e8 19c9 1928 1911 192b 1995 1906 1905 1927 1911 1944 1981 1a24 1a5b 1e83 3a73 3c89 3b3e 3c08 3be4 3b25 3b24 3aa3 3a80 3a72 3ab1 3b1f 3b48 3b74 3b71 3b9f 3b44 3b2e 3ad3 3a3d 39e0 39ff 3a53 3afe 3bd2 3b18 1c17 1aaf 1b20 1c6b 1b33 1a2e 19f3 1960 1968 195c 1936 1a15 1af7 1981 1a0b 19b8 1964 193c 18cc 1961 1870 1889 1865 18b2 18cf 1ce9 3a74 3cac 3acb 3a98 3a3a 3b1e 3cdc 3e2f 2d0d 1a4e 193a 1991 1909 1850 174a 1ecc 34b1 3da9 3af5 3a8e 3a43 3a23 3a83 3abf 3b2c 3ca4 3cf9 23b5 16d4 188e 1836 1c3e 3a44 3c58 3a19 39e6 3a2e 3a26 39f2 3a5e 3a3e 3af7 3d66 37fe 18f9 184c 1813 17a1 17f8 16f3 1621
0fed 1134 14f4 1750 17ff 188d 19a3 1a23 1974 1bb7 2ebf 3d05 39b1 3908 387a 37fb 3820 3808 38ae 387e 3877 388a 38b0 3896 389d 3903 3920 39a1 3a25 3ac1 3acb 3c57 39a0 267c 17f0 14dd 178a 18e2 18f9 196b 1931 192b 1847 18b9 1924 19c9 19b0 19d3 199a 199e 1ab8 1932 1964 1988 197d 1aa2 1a7e 2e30 3f35 3caa 3c40 3c40 3b16 3ad6 3af8 3ac2 3a8f 3a94 3ace 3b19 3b9e 3b59 3b6d 3b2c 3ad4 3a8b 3a69 3a50 3a37 3a42 3b02 3ba7 3bf5 1d45 19b6 1acd 1c80 1b5f 19c5 19d8 1a4a 1933 18ad 18b4 187f 194f 19ba 1ae6 1ae3 1a9d 198c 1962 197e 186e 1846 185f 185d 18b4 23c7 3e35 3b56 3aa7 3ab4 3a51 3a97 3b52 3cb6 3ec3 390a 2c27 2378 21e4 255e 30ac 3c72 3d53 3b39 3a72 3a03 3a5a 3a20 3a54 3a7c 3b38 3e1d 2948 16f4 19b9 19bb 18cb 17d6 2a68 3e30 3afc 3a46 3a3c 3a91 3aea 3a8a 3aad 3cae 3d8d 2284 16ab 195d 189c 176e 16c8 15db 14db
109d 11b4 157c 1721 170b 17cd 18fa 194a 18cf 18e1 19cc 304a 3bdf 3935 37e7 380b 3830 382a 3854 384c 3851 3889 38a1 3897 38f7 3953 3968 39d6 3a7e 3a75 3a2d 3a75 3b88 3cdd 37cf 2ce5 1ca3 149d 17a7 1866 1834 197e 192d 18c7 19af 1a95 19ed 1a7c 1a11 1a6c 1a09 184f 199a 196c 199c 1a6d 1b00 1f2b 36ea 3fcf 3cdc 3b7e 3b91 3b33 3b1d 3b13 3aff 3b23 3b54 3bb8 3bbb 3b5a 3ba7 3aeb 3a50 3a2c 3a5d 3a7c 3a76 3a52 3a99 3af9 3ddf 2482 17ad 1ad5 1c06 1ab4 1940 1a62 1a1d 19a5 191e 1950 1823 18c3 19dc 1a99 1a1d 19ee 1997 1a42 1995 1933 18c0 183e 18ab 18e3 2681 3e50 3af5 3a68 3a5b 3a99 3ae1 3b14 3bae 3c7c 3da4 3ec0 3e33 3dfe 3ecd 3e95 3cdb 3b83 3b1c 3a99 39f4 3a25 3a02 3a7c 3afc 3c4c 3823 19af 18a9 197a 186a 179f 17bd 1930 2e78 3e37 3cd7 3b53 3b4d 3bc5 3ce0 3e46 3b97 250a 15d9 1856 18ae 18c1 1761 163b 1586 145c
1114 1283 1598 16e3 1738 184e 19e4 1986 190c 19b2 1979 1d0f 387a 3999 382b 3857 3883 3872 3844 3870 38a7 3875 38f1 38f1 3944 395a 3980 39c6 39fb 39d9 391f 396b 3990 39a5 3af9 3cc8 3ac6 2661 14bb 17d6 1859 1897 190e 18d4 19d8 1b53 1b60 1c70 1b44 1b16 1af5 1a17 1a94 1a32 1a16 19fc 1a41 1b4c 2036 342b 3ed6 3e2e 3ced 3bc9 3ba9 3bb9 3ba6 3b7a 3b8e 3c31 3c02 3bc0 3bc0 3ae0 3ae0 3aae 3a65 3adb 3b18 3b0f 3b64 3b78 3d8d 33e0 17bd 1a18 1c23 1bd9 198e 1a7a 1a78 19a7 199b 1a4e 189a 1907 1a11 1a7d 19b9 19d2 1984 1a17 19c2 1a66 19b6 1906 189f 189f 25d3 3dea 3ac9 3a68 3a55 3a16 3a24 3a77 3aa6 3b38 3b8c 3c06 3c50 3c88 3c78 3c2b 3c22 3bad 3b2a 3ad3 3a53 3a55 3a3f 39ec 3aba 3d87 2e15 1726 1910 198d 1942 17c9 16ab 1644 1900 2607 3602 3c28 3d6b 3d57 3a5c 2fcd 1e15 1720 1887 170a 17b8 1780 174c 16d7 14e9 1441
1174 1368 15bf 1712 17a4 18a1 1a91 19b1 1a12 1a0f 190d 16f9 2c92 3c10 398d 38f8 38fa 391a 38cd 389f 38b8 3932 3998 39c2 3a05 396c 39bb 39fb 39ce 397f 3935 38d7 3996 39a8 3969 39c8 3acd 3d2a 25f3 14a1 1803 1967 1a3c 1a20 1a70 1c13 1d0e 1c52 1bb0 1ad1 1af1 1a79 1a19 1abb 1bed 1a85 1a4b 1aa3 1b42 1d0b 26a4 3287 3c58 3ef6 3cd7 3c6b 3c30 3bfb 3b89 3c0f 3c64 3c79 3bff 3b60 3b44 3b0a 3b43 3b92 3b61 3b03 3b70 3baa 3bc8 3dc6 27f3 16e3 1a37 1ae0 1973 198e 1993 1924 19b7 1b5b 19c2 1978 1a52 19f2 1980 19ac 19d8 19b6 194f 197c 19da 193d 190a 193e 20f0 3cf1 3baf 3adf 3a52 3a51 3a6f 3a90 3a5f 3a60 3b49 3bc1 3bff 3c46 3c1d 3bb7 3bd0 3bcd 3b41 3b4c 3ae5 3a92 3a70 3a42 3af0 3de9 2962 1808 19c0 1a06 19ac 18f0 174c 15ba 1749 17d9 1a79 1f1d 216b 2113 1cfc 188e 1830 18cf 1912 188f 1898 175f 182c 1672 169f 1679
1048 132d 1602 1673 165d 1921 1a44 1928 19fc 1a3a 1965 172b 238a 3c68 3a10 3981 3964 3941 38eb 391f 3970 39b6 3a75 3af3 3ad2 3a37 3a75 3a64 3a2e 39be 39bd 3931 3964 39df 39f4 3a2f 3a12 3b65 3ad3 1b26 1739 1896 192e 1a02 19c4 1a8a 1a8a 1a67 19f1 1a60 1a15 1a63 19d2 19a0 1ab6 1b0c 1b82 1bee 1c4b 1c5a 1b1e 1c37 21f9 32f3 3ec2 3d28 3c9f 3c84 3c1a 3c3a 3cad 3c62 3c60 3c24 3bfd 3bf9 3c2f 3bc0 3bb9 3c0a 3bc6 3bc7 3beb 3ce1 3cc7 274d 170f 1746 1893 190c 1807 1859 1844 19e4 18d2 197c 1a98 1a5b 19cd 18be 1916 1996 18ad 17ef 1886 1806 17d4 1860 1a26 3618 3dca 3ac6 3a3b 39f9 3a74 3a2d 3a17 3a86 3ae4 3b04 3b2d 3ba5 3c31 3b57 3b1d 3ae9 3aef 3b10 3af6 3b03 3aab 3a54 3b19 3de9 28cd 1698 1985 1913 1853 181b 178c 1611 1624 17e9 18c7 1969 18c7 180a 1990 1985 18ba 1925 192d 175c 180c 1766 1754 15fb 15a3 1c3d
0d17 109a 14d6 1601 16c3 18e1 1928 18f6 19de 1aae 19c9 182f 20ba 3c1f 3a73 3a0b 3a37 39ae 3977 397e 3a23 3a52 3b13 3b5a 3b31 3ac2 3b3f 3ac8 3a57 3a63 3a53 3a44 3a01 3aa0 39e2 3a1c 3abf 3ad7 3dbd 2b39 166a 1781 182f 1964 18bd 1964 19f4 19c0 19d0 19d1 1996 193b 1975 1951 1a56 1b30 1bd4 1bb3 1bb6 1bcb 1bd1 1b66 1bb6 1c86 3039 3ec6 3ca5 3c45 3bc4 3bcb 3bd1 3b62 3b56 3ba8 3b74 3ba7 3bbe 3b21 3b6c 3bea 3be2 3bc9 3c04 3bcc 3c95 3db3 3346 2436 1904 15df 1853 17b6 1857 183a 1692 180c 1a1c 1a21 19ab 193b 1949 18bc 18b4 1884 17ba 178c 179c 17bb 17a8 2475 3d62 3bfb 3a25 3a6c 3a8f 3a80 3a32 3a77 3abf 3aa0 3aa5 3b16 3b53 3b6a 3b1a 3aa1 3a3b 3a76 3a57 3ad9 3a7d 3a62 3acc 3cf0 2da8 14f3 1738 17a7 1720 1706 17b7 170d 1756 1719 188e 1927 18bd 1711 1877 19ba 192c 1926 1894 1708 1789 17a2 16ab 15a6 152f 24bb
28e2 220b 1849 12f5 15be 18d0 192b 1967 19b8 1a17 1992 17cf 21db 3c5e 3a4d 39d7 39bd 3975 3971 39a3 3a63 3abf 3ac8 3b1a 3b38 3afd 3b07 3b33 3acd 3a42 3a55 3ace 3aa5 3a65 39bf 3a06 3ae9 3ac9 3cd1 342f 180d 1a4d 1910 199e 19bb 1981 1a33 19a8 19a3 1a42 1999 1986 1902 1984 1a3b 1b73 1ba6 1b3e 1b91 1c24 1baf 1af4 1c40 1c90 1dc8 3726 3d7b 3c3b 3b38 3b2f 3b13 3aec 3aef 3ae0 3af1 3b29 3afb 3b13 3b73 3bae 3c02 3bee 3b8d 3b81 3b86 3bd1 3d45 3e00 3908 260a 1534 170e 183f 17e5 1586 16f5 18c0 194b 198e 1a21 1983 18b0 182b 18a1 18c7 189c 18cc 17fe 17c7 19b2 2aca 3da4 3dd8 3c17 3afe 3ac6 3aa9 3a6c 3a26 3a62 3a56 3a82 3aa6 3ac3 3a6f 3a7d 3a1e 3a1d 39cf 3a0e 3a37 3a5a 3abf 3bb1 378f 16d9 1642 1703 1770 16f2 1685 1695 16d3 1755 177d 1835 1756 16ec 1788 1930 184f 1724 183e 17f0 16f9 1795 1698 14ee 14ae 27f4
38e2 3a8c 3866 2808 14ae 1730 1861 18a4 1947 19a5 1969 1634 287e 3c2b 394a 395a 396a 3964 3966 3985 3a0b 3a6e 3a61 3ae5 3ba2 3c59 3cb4 3d49 3c9a 3bee 3b7f 3b44 3ab0 3a15 3a2f 3a2d 3a35 3a62 3c56 3640 1890 1a15 1941 1978 191d 1915 1a1f 19d1 18b0 186b 17f6 184e 1901 19fd 1b1b 1ad4 1b1f 1b6e 1ba7 1b8b 1b73 1b39 1b44 1b4f 1b1b 28af 3e2d 3c52 3b36 3af8 3af6 3a8d 3a5c 3a4e 3aad 3b09 3b5d 3b76 3b9d 3b9f 3c02 3b97 3ac3 3b24 3b27 3b11 3b33 3ae4 3c2f 3e23 2a31 13ce 16b6 1764 15e4 1617 1700 176e 183e 1926 18e8 188e 16d4 16cd 1760 17c3 18b8 179d 1662 17f1 1a30 2586 3563 3cbf 3e1f 3bdd 3ad8 3ac5 3a6a 39ce 39bd 39da 3a39 3a49 3a41 3a62 3a50 39c2 3967 39ab 3a0c 3a17 3a1f 3a98 3d42 260b 1220 162d 16a3 15b8 14ab 14d3 154b 16c4 16b3 16f5 1696 16a7 1664 162f 16ae 15b8 1770 17a2 158f 1693 14f9 132f 13cf 254b
35e1 3688 3879 3c2d 2ede 1525 16ed 1698 1841 192e 17b6 174f 34bc 3af0 394e 391c 38de 3896 3896 38f1 39a6 3a5d 3a9e 3d02 3bfe 370f 341a 34f2 38fe 3d85 3d7a 3b20 3af6 3a2b 3a2f 39c8 39ea 3a24 3c00 358d 17c6 193b 187b 1911 18e4 184e 18a0 18e5 182d 18a4 181a 1805 1882 1949 1949 18a0 1823 17fd 18cd 19a3 1a2f 1ae0 1a88 1aa1 1b42 202d 3baa 3bf0 3b25 3aef 3a87 3a89 3a73 3aea 3b00 3b32 3b4c 3ba1 3bae 3b5b 3b73 3b56 3ad5 3b0b 3ab7 3aad 3ab6 3a57 3ab7 3b19 3d8f 2216 14a5 1738 16cc 161c 17b6 18ae 196d 19d3 1939 190d 18eb 1828 1792 18d5 1905 1856 1747 17d1 18a8 1901 1b85 21e1 2f7a 3d4b 3d28 3b74 3aa8 3a5f 3a83 39f4 3a5d 3a59 3a8c 3a7f 3a76 3a0c 398a 3965 39da 39b0 39f9 3a61 3b4d 3a45 1e29 127c 14ad 153d 13e7 1454 153f 1672 164a 16a0 160f 1699 16f6 1680 16b3 16ba 1749 1706 155d 1633 13d8 12ea 12d4 1c05
3570 3617 369b 371e 3bf3 291a 1420 17ec 18bd 18c7 1653 2697 3c51 39d1 395f 3932 3927 393f 3976 39b2 39d5 3bb7 3c6d 2e33 2044 1afb 1a95 1b5b 1d2b 2567 357c 3dac 3b77 3a83 3a11 39b5 39d4 39ec 3d39 3008 1769 1966 1a84 19d7 198f 18a6 1899 18eb 19b7 1a15 1961 188f 1745 17eb 1836 1834 18d3 1777 187b 1abd 1aec 1b0f 1a9e 1aae 1b3f 1d97 3994 3ca9 3b76 3b2c 3ae1 3a95 3ad3 3ba3 3b82 3b27 3b8b 3baa 3bec 3b91 3b0e 3acb 3aca 3ad9 3ab8 3a71 3ac7 3a7d 3adf 3afc 3ccc 342b 16c8 17ca 1756 15e8 17bd 19b6 1aa7 1ad8 1a70 1a46 1b1a 1abb 1979 1a56 1aa3 19ac 1a58 1b88 1b23 19f1 1963 19d1 1ad8 26e2 3cd6 3d1b 3bd2 3bfb 3bf7 3b41 3b31 3aaf 3ac9 3a7d 3a34 3a1f 39f3 39b5 3a08 3a34 39e8 3a05 3a83 3ba9 3abc 28af 16d4 11de 132e 147e 1503 1550 155d 15b6 16ad 1702 17a2 17a8 1824 186d 172c 16d6 1625 15c3 1477 12d4 1262 1578
35ae 35d0 3668 3748 38db 3944 1a27 17a1 1775 15bc 22c8 3a6e 3a32 395a 3945 3940 3968 39f4 3a0f 3a15 3b60 3c20 2523 18f3 1a3a 1ac5 1b85 1bdd 1cd9 1a9d 1c7d 3088 3d8c 3b5a 39d7 39af 39dc 3ad2 3df9 2333 189d 1a51 1b43 1b12 19e7 19d1 19e3 19c7 1a54 1884 1886 1dcb 22f7 247c 2195 1bd5 170d 1880 19eb 1a7d 1c4a 1c4e 1bae 1bf6 1c2d 1dca 3a27 3d12 3c25 3bce 3b21 3b45 3b96 3b95 3b97 3b74 3bdc 3c4a 3c94 3c65 3bf1 3bc2 3ba9 3b34 3b1f 3bab 3b95 3b12 3b5c 3b44 3c16 3c63 1d06 18bd 1787 16e1 1812 19d3 1ab1 1a31 1a37 1a24 1a4c 1b85 1a9f 19f3 19a5 19ad 1a2a 1ab7 1b12 1acd 1b6f 1b64 1c0c 1ba1 2a88 3ee6 3d49 3ccf 3c46 3c3c 3bba 3b3f 3b35 3b3f 3b86 3b00 3aba 3ad6 3aab 3af3 3a5b 3a80 3acb 3b0f 3bb1 3d05 39a9 2eb6 19c7 1131 1431 14bf 159a 1587 169b 173f 179e 1830 1862 18de 170a 165d 1615 162f 1528 12e0 11d0 144d
3673 36d1 37db 37ce 38a2 3e19 25bd 12eb 186a 296f 3aec 3ac1 398e 39b3 3986 396b 3984 3a39 3abb 3b14 3d2c 2554 17f7 1b17 19e2 1a26 1a68 1acb 1ae4 19db 1b7a 1b66 3432 3c80 3988 3a08 3abf 3e47 33a3 18b0 1a61 1af5 1c27 1b66 1ab9 1a78 19f4 1a0d 16e8 1fb4 32a5 3c41 3df0 3da6 3d2a 3a6d 2d94 1a00 177e 1a0f 1af3 1bc0 1b6e 1bbf 1b37 1fb7 3c6c 3c4c 3bb2 3b45 3b05 3b65 3b78 3b4e 3c58 3cb0 3cca 3cb5 3d2e 3d46 3d05 3cd4 3c40 3c2d 3bdb 3b90 3b31 3b47 3ba3 3bad 3c65 3e77 2117 1910 17aa 16bc 18a1 195c 1968 1969 18e6 189d 1885 1a86 1963 187d 18e2 199b 19f1 196b 1aa4 1a62 1b54 1be9 1b24 1b83 1e10 37db 3eab 3d30 3c7c 3c0c 3b60 3bc4 3b83 3bc7 3be8 3bd2 3c02 3be0 3b72 3b63 3af9 3aaa 3a9b 3b45 3abb 3a9a 3ac9 3c6f 3a52 212a 1218 1596 14d5 1606 16fa 16cc 1729 18b3 1935 18fd 1859 17aa 1693 1678 1543 1353 11cb 1240
3817 384b 3868 3acf 3bd2 37de 2f39 2eae 384c 3b70 39e5 398a 3953 3941 392a 394f 3975 3a09 3a90 3d23 30bd 180f 1a2c 1964 18c4 18e0 198e 1a4a 1a33 1a8b 1ac2 196b 21d1 3c10 3a54 3aad 3dfe 381d 1be0 1872 1abc 1c37 1b00 1ad7 1a78 1a51 1a3a 1727 2454 3bfd 3c9e 3a76 3a58 39e8 3a3d 3bb9 3e15 3807 1c8c 18dd 1a1f 1c0a 1c52 1b67 1982 2a58 3e17 3bcc 3b30 3aa9 3ac2 3af2 3b46 3bc7 3cbf 3d61 3e78 3eab 3cc8 3c1b 3cd2 3e9e 3e39 3cc2 3c6d 3b6a 3acd 3ad2 3b06 3b24 3c76 3e03 1fc3 1997 18aa 18ea 19e4 1a7d 1a3d 1961 197c 1902 1981 19f5 18f8 1890 1875 19f9 1b0e 1afc 1b16 1b91 1ae4 1cc0 1bce 1acf 1bb1 2ccc 3f5f 3d56 3c9c 3c4c 3bc2 3bea 3b91 3c13 3c64 3c3a 3c73 3c6f 3c59 3be9 3b76 3af3 3ad3 3b1b 3b64 3a99 3a42 39f8 3bc9 3b47 1be2 14cc 14e3 1609 177a 1789 17c3 1945 1a5c 19aa 1944 17de 16e3 16ad 167c 148d 1392 1279
38f8 3978 3c3c 3377 2204 17f6 28b2 3eaa 3a09 38ad 38dd 38e9 38ce 3945 3964 391b 395a 3988 3ac5 3d2c 21a7 18de 19b9 1a7d 1980 19c9 19c0 1a20 1ac7 1b64 1ab0 1a2f 1830 3584 3e93 3d75 33ac 1cab 17a5 1a0d 1adf 1bdb 1a9c 1994 196f 1a4d 17ff 2118 3c3c 3b82 39ea 3919 38f6 38ef 3960 3a6a 3b54 3da7 3670 199f 1b1c 1cc5 1c54 1a35 1d9d 399d 3d68 3c13 3b88 3add 3aea 3b21 3bc7 3c7b 3ce9 3ed9 35a9 2874 215e 204a 21fe 289b 34fd 3e93 3d80 3c49 3bde 3b25 3ad9 3ae6 3cef 3b6a 1c89 1a0d 180b 1991 1a06 1b04 1a2e 1a79 1a64 1976 19ad 19ce 198c 1839 1874 1aba 1a8b 1aa7 1b8e 1be6 1be9 1c28 1c7a 1c0e 1b85 268f 3eea 3d03 3c30 3baf 3b67 3b80 3b98 3c0f 3c7c 3c81 3c9c 3cae 3c91 3c31 3baf 3ad3 3b15 3aaf 3aef 3ab7 3a0e 3978 3a28 3d15 30a7 1344 1501 1600 16fa 168f 17b8 1a30 19c7 18e4 183e 181c 1754 176b 1698 151d 139d 131b
3967 3c71 2ab1 17fb 1720 1768 1fa0 3ba7 3a37 38e6 38be 3915 38bb 388f 390c 38e6 3943 3981 3c8c 367c 1963 1929 19e6 1b2c 19da 19f3 1956 1913 195f 18df 1713 182b 1f2e 2eeb 3042 2479 19dc 18f6 19ea 196c 1b47 1c0e 1b06 1abb 19d9 192f 191b 34c2 3d8c 3abe 3a28 39c2 395b 39bf 3a33 3a67 3b47 3bc6 3ec8 2734 1859 1b4a 1939 1b4b 3401 3e14 3cb7 3c2a 3bb2 3bc4 3baf 3bb7 3c99 3d79 3dfd 29d2 1be1 1b38 1c4c 1d0c 1d09 1d9a 1da9 29ac 3d1b 3d58 3c4a 3ba3 3b2a 3b82 3e6b 31eb 18f3 19db 1965 1a77 1a89 198d 1a02 18cb 1906 18be 16dd 174d 1a24 1a64 18ac 1586 17df 1a30 1aeb 1b84 1b87 1c07 1c12 1cdd 1b51 2592 3ed4 3d0f 3c21 3b83 3b5d 3b2a 3b18 3ba0 3c75 3c9c 3caa 3c94 3cb8 3c4a 3c0e 3bce 3b5c 3acc 3a86 3a79 3a31 39b6 3a01 3b92 3a49 1830 1485 14f0 1664 1738 1866 1a4d 19f2 17a6 1743 1797 175e 1673 15e0 1501 142d 12ec
3d00 2dce 1661 187c 189e 175a 1873 3047 3cf9 392d 38a4 3926 3950 392d 3968 39a5 3952 3aa9 3d58 240b 17a8 1954 1a22 1aca 19e2 1890 189d 179a 1781 176d 2557 36c3 3e69 3158 174e 1a11 1b59 1b0b 1ab5 1ab9 1be1 1c7f 1b72 1b9f 1a94 1905 228e 3dd0 3bfe 3b45 3b36 3ac1 3b0e 3b9d 3b83 3b24 3baa 3bcd 3e37 34cd 159a 17aa 20fe 3597 3dd6 3c5d 3cab 3c53 3c39 3c27 3c5e 3ce5 3d8d 3e94 2933 194a 1bb7 1c0f 1cc7 1e30 1d36 1d9d 1d8c 1ad5 2a81 3ece 3cc3 3bc7 3b4d 3cee 3d71 20a6 186f 1a71 1a20 1ace 1b01 1a89 1add 1a0f 18f1 19be 285d 3575 3a1b 3a90 3901 300a 1eee 163a 19ab 1a2b 1a4b 1bb2 1cac 1c2b 1bce 2931 3e8c 3cc4 3bdf 3bc6 3b87 3b1f 3aed 3b5a 3c86 3ce5 3d24 3cb1 3ca8 3cb1 3c74 3c00 3ba2 3b6d 3af6 3a87 3a18 3a3e 3a5e 3ac9 3cdc 1d00 1408 1565 169f 180f 18bf 1941 1ab7 18ae 1732 16ca 16cc 1614 1555 1526 1489 13e0
390a 1a58 18d8 1966 1968 1790 1712 1c87 3606 3d18 3a8d 3991 3983 39f5 39e8 3a7f 3c10 3e2b 2a2c 186a 19a4 1991 1a1f 1ac9 1944 17f8 1826 18fb 19ae 3073 3d90 3c24 3beb 3969 1b72 1ad5 1b87 1b2d 1b36 1c18 1c25 1bd7 1c26 1bdc 1bee 1aad 2fcd 3e6b 3bd5 3b30 3af2 3ab6 3b38 3bd5 3bd2 3c1c 3cfb 3ebf 3dfa 3690 280c 3287 3d3b 3dd1 3c89 3c5f 3c99 3c58 3c8a 3c58 3cd6 3d6c 3f5e 3313 1abf 1d55 1beb 1c10 1d42 1ce8 1dda 1ece 1e97 1b6f 1bdf 35d4 3e43 3bf6 3d37 3ef1 29b7 18b1 1ab1 1b90 1b14 1b90 1b79 1a5e 1adc 1987 1f16 3614 3ee8 3d5e 3c15 3bd7 3c47 3d67 3d01 2a13 168c 19f8 1a5e 1be0 1c5a 1c00 1bc9 3384 3e92 3c83 3c00 3bc5 3ba7 3b21 3ac6 3b3a 3c2b 3d18 3ee4 3f4f 3ee1 3f12 3f1d 3dc6 3c9a 3c1d 3adf 3a33 3a50 3a49 3ae9 3af7 3d20 1e5f 148d 1654 177a 18c9 1944 18f8 196b 17d5 16c8 1644 15d8 1682 1605 154a 1441 140d
2bf4 177a 1a0d 1a0c 1959 17b4 1750 1872 1dab 31a3 3ca1 3d49 3c08 3c1a 3ca5 3dae 3a0e 26a1 177f 1974 19bf 19df 1a0d 1a07 18e5 169e 1776 1784 2d46 3dde 39fd 39c6 39d4 3d6f 29a9 1763 1a77 1b53 1d43 1d1e 1c84 1c3f 1aa8 1a99 1a00 207e 3bc3 3bed 3b13 3aaa 3ae2 3b5e 3b6f 3c34 3ca8 3df5 3e57 31c5 2300 2112 3d2a 3efc 3cb8 3be7 3c3a 3c50 3c02 3c27 3ca3 3c8c 3cbb 3dcd 3edc 234a 1be1 1cdb 1c05 1d03 1e13 1d96 1d10 1d8c 1d8a 1d00 1a8e 2884 3f71 3f06 3d3e 296e 18ea 1aab 1b5b 1b78 1ba1 1c13 1b3e 1b18 1aa7 1e0a 390d 3e9a 3b61 3aee 3a8f 3a5d 3a7f 3aee 3b91 3e4e 28e2 174d 1a5e 1c0f 1bb6 1b01 22f1 3da9 3d28 3be8 3bb4 3bb6 3bae 3bc2 3b4f 3b89 3d93 3e49 3516 2b95 2790 28b3 2f8c 39da 3f20 3d40 3b62 3a78 3a82 3a32 3a7f 3ba5 3b3d 1a36 15c8 16de 18b9 18d1 18d1 19be 18ef 1719 15ad 16c7 173e 15ef 1568 1574 143f 13c3
217c 17f1 196b 18a0 18a6 1784 171f 1857 1900 1a9b 22f3 2da4 32eb 33e8 309a 27de 1cd6 17ae 1821 19b6 1a57 1948 1938 1927 17b8 15cf 175d 2067 3c20 3a1e 387d 388d 38a4 3a81 3aa8 2041 17f0 1bdf 1c2a 1ca8 1c8d 1b19 1a1d 1917 1ca3 369e 3d8f 3b8c 3abd 3abd 3b58 3bd5 3c48 3cbd 3dc8 3d81 27fd 1aba 1aeb 1c3b 3747 3e24 3c23 3bbe 3b90 3ba8 3b8b 3bab 3c69 3ca9 3c6f 3ec6 37f4 1bb6 1c99 1c43 1c43 1d12 1d8c 1d40 1d76 1d01 1cab 19ea 1ac4 2565 38d1 2fce 2059 198a 1a46 1ac0 1c2e 1bb8 1bf2 1cc3 1bff 1b2f 1abb 3206 3e70 3b74 3ac4 3b1f 3ae8 3ad9 3b53 3b48 3b62 3d33 3bb1 1aa8 17f1 1a01 1979 1d59 3750 3e8a 3c7a 3c12 3bb1 3b97 3be3 3c4e 3c2c 3e46 394d 24ae 19e1 1a1f 1b9d 1c13 1b13 1efe 2f56 3e78 3c50 3b1c 3a4b 3a42 3aa3 3dcb 3306 1591 16d5 16d2 185a 19e0 18d9 189f 1831 164e 15b7 15da 1424 138e 1390 115c 11e0 1308
1e34 17b8 1856 1869 179a 161a 1636 1951 19c8 1a00 1928 1965 1a2f 19cc 1919 188a 189f 1820 1862 1945 18fb 1917 1922 1883 16d4 178e 16c6 2dc4 3c87 38d0 37e6 37b6 3897 3a01 3bef 3ad8 275d 1954 191c 1a61 1a7c 18af 195c 23ac 37a2 3e30 3c72 3be2 3b7d 3b87 3bc7 3c9a 3cd8 3da6 3e35 27b7 1a5b 1d24 1d9f 1ade 29c4 3f3a 3ca5 3bd0 3bbc 3be7 3c1a 3c77 3ccb 3c87 3d73 3f7b 2748 1a2c 1bca 1bd6 1be4 1cf1 1c46 1cc5 1d12 1aea 1bd0 2995 37ce 3bc6 1ff7 19a0 1a60 1a7b 1b5e 1c90 1dca 1d08 1cf6 1da8 1cf0 1bc2 22b3 3d74 3ce5 3ba5 3a9d 3aca 3aeb 3b29 3b5a 3b96 3b97 3c08 3ed8 2723 1527 186f 1f2d 3626 3efc 3cca 3c5c 3c07 3b91 3ba3 3c7c 3cc6 3e1e 3904 1e0f 1921 1a5a 1b8e 1b99 1c14 1bae 1b3b 1b4d 2ded 3e23 3b33 3a67 3a77 3b6f 3de7 2143 166d 183c 184a 1947 19f3 1923 18a4 187e 15e8 1713 23a2 2f7c 3525 34b2 2f2b 20ff 119f
2096 16c5 1902 1828 174d 1609 1724 189f 198f 1a9e 19ab 1a3c 1a2f 19dc 198a 192e 191b 18d1 18cd 1998 1954 1a5e 19b2 17f6 179f 17d1 1863 3491 3a68 3821 37d2 3897 38f2 39cb 3b2f 3c1c 3e08 36cf 2c49 26c4 263f 2bc9 35ab 3df4 3dba 3c5b 3c36 3c48 3c26 3c57 3c82 3d0c 3cf9 3f15 324f 1b2b 1de7 1e83 1d3b 1b90 1cfb 339b 3e7f 3c99 3be1 3c0e 3c92 3ca9 3ce0 3d6c 3f87 30f8 1984 1ba1 1bf0 1be0 1bc3 1c90 1b6d 1b08 1b72 1e07 3557 4011 3eb8 3f23 250a 1a7c 1bd7 1c2a 1cd5 1dc3 1cd8 1d17 1c5d 1ca9 1c91 1ab2 2dc6 3f4d 3cf7 3c0a 3b01 3b46 3b61 3b1c 3bae 3c50 3cbd 3d17 3f03 312d 1f7f 2da3 3b92 3e50 3c6f 3c50 3c0b 3c25 3b96 3b79 3c86 3d9c 3d8a 2287 1925 1b4b 1afc 1a92 1af8 1afe 1a76 19f4 1984 1af9 3771 3ce6 3b14 3bac 3e37 2e64 160f 1823 1809 1900 1969 1826 1802 17a2 1735 1e16 3500 3e93 3d42 3c3d 3cda 3d86 3d7c 308a
input_data/pattern_160_120_16.dat 0 → 100644
View file @ 043d4849
//
// autogenerated from ../input_data/pattern_160_120_16.tiff
// GENERATOR = ./x393_tiff_verilog.py
// WIDTH = 160
// HEIGHT = 120
//
6e9a bd0f cbd7 c9cf c860 c836 c962 c9c6 cbc3 cd12 ce30 d110 ca95 91b2 52a2 3d26 52b1 b9df ccca c86f c749 c794 c7ff c6d7 c628 c7c3 c916 c98b cbd4 cf76 c559 6118 3c2c 4015 4227 4350 436f 450f 473d 473c 4497 42d1 400f 4c5b a3f0 cd66 ccca cf59 cb7b 8989 4004 37a3 397a 3b39 3da8 4051 3f16 39e5 330a 31a0 50fc a611 cb62 c9fc c8f3 c836 c913 cd25 c809 8896 3961 3080 3a18 3da7 3f1e 3f9d 4001 475b 9f3b d630 d381 cf79 cdde ccef cd87 d024 d391 d618 d743 d812 d944 da73 d97c d803 d5b9 d321 d1a5 d0b9 cf6e ce4d cb2c c9d6 c8df ca14 cb46 8117 3269 3304 35dd 35a6 377a 3894 396c 382d 3b1a 3af5 3a14 38f3 382a 39df 3943 3986 3aaa 3ca5 3fe0 409f 4312 4413 44fd 510b 97d7 d5c7 d5ce d479 d43d d4f2 d397 d1a7 d11b d11b d21e d33c d347 d3e4 d3ac d199 d0d1 d018 d0c0 d006 ce92 c575 88f8 4978 2baf 2922 2fbb 2ffd 2de6 2f77
bd9b cada cb0e cb5e ca5a ca5f cb0e cbf2 cd9a ce82 d0c3 c9cf 8837 4e74 4093 3e2b 46d9 9f66 d001 ca19 c725 c716 c78d c61c c6a1 c8a6 c895 c7c5 c9de ce9f adb8 485c 3bc2 3fc9 405e 3fe6 405c 4136 429f 448c 4303 4029 3c5c 3e65 84b2 cf1a cfc4 bec2 86a8 471a 37dd 3a95 3d6a 3e71 3e5a 3d68 3a56 340c 3057 492d a18b c771 c87e c8d9 c8fd c98f c9e0 ca62 cb30 c559 84d9 392b 3901 4029 42e3 4355 4097 56dd bc08 d71e d2f0 d126 cf6a ce63 ceca d15c d3d2 d628 d81d da4e db35 dc57 dc20 db31 d850 d5e5 d41a d208 d028 cee8 ccef cb2d caf7 ca72 cc24 8d13 350a 31c9 3669 38d6 3ac2 3bff 3c23 3c4a 3cd3 3a4e 3a07 374a 3703 3953 3ace 3c38 3df8 3e70 40d3 4155 42e8 4441 43f4 47ee 6644 c21a dae5 d7a3 d59a d571 d39b d2ad d22b d27e d2c1 d399 d40f d398 d3db d1b8 d0d6 d04c d026 cfdc ceaf ce16 c92f b436 8466 4530 2c6b 2e1e 2fc9 30a8
cbbb cb08 cafc cbdf cbb7 cbf9 cccb cd2a ce67 cef9 cf95 9965 4825 3e28 403f 3e33 3eb0 6d17 c505 cf33 ca37 c7c5 c6ee c65e c81e c9d1 c9f0 c8d8 cae3 ca78 7ea5 3b78 3a0f 3c00 3adb 3a93 3b30 3dd7 3d15 3f08 401b 418d 4c43 67ad 96b4 ab0a 8f11 6113 3fd9 3973 3bf8 3e44 3e48 3eb4 3cd5 3a74 3713 32ac 3a76 8fb9 c907 c858 c695 c7aa c86b c8f6 c98f c96d cae5 cdce c42c 6d69 380e 3edb 40f6 3fa5 4217 8320 d057 d306 d016 d0b4 d04e cf7f cff0 d269 d4ae d788 dc2d d842 c12d aa69 a440 af37 c589 d54e d6e1 d3e3 d104 cff7 ce34 cc43 cafa c9d2 caa0 8ba4 35e0 3248 34f8 3798 38da 395f 3acd 39e9 398a 388b 3a7d 3afd 394d 38ea 3878 39c1 3bb5 3c3c 3c87 3fcf 4299 43fe 4456 45d1 50a8 9ed4 dc1f d8d0 d5c2 d5eb d4df d359 d2c9 d370 d41b d4e8 d53a d498 d4f8 d243 d075 cfdf ceb6 cdf9 ce5a cd4d ccca cc38 c8e6 a5a9 5079 2b74 2dae 2fc0
ca7a cb69 cbc3 cb7b cc21 cc8f cd14 cd4b ce32 cf65 c21f 5f08 3a32 3bbe 3d08 3c65 3aa3 4907 8fb0 cce5 d048 cc7c c975 c7f8 c85b c99f cb39 cdd0 ce7f a78a 4cfb 373c 38b6 3abf 37bf 3697 3582 3839 3801 38a2 4112 7354 af3f cc3b c8e9 6b31 41c7 3cc0 3cb7 3da9 3ff8 3fd5 3e84 3e7a 3d9e 3cf3 3959 363c 5b43 c0ac ccd0 cb0f cb78 cbce cbd4 cb87 cc7c cc0e cbd3 cd99 d11e ab28 45bf 3c38 3de2 3d4c 665b be27 d1ef cefc ce4d ceab d01a d051 d0db d317 d667 d900 bfdc 86ad 5fb0 53c8 527b 573a 6919 925f c6b8 d750 d43b d1d4 cf87 ce1b cd00 cc14 cb27 7c17 3356 3295 35e8 384b 36a0 362c 36f9 353f 35fa 3681 3634 388f 37be 35ea 3449 33a7 370e 38ba 390f 3c90 4028 410a 4183 429f 4820 802e d677 d872 d511 d36d d165 d041 d00b d153 d3e0 d4c7 d4d9 d489 d4b8 d2fe d1c5 d088 ceaf cdfe cd71 cd97 ccb0 cb42 c95d c90c 9f1b 3dbb 2a0d 2dde
c928 ca43 cb4a cbb6 cc9e cd63 cdb0 cd2f cde4 cf87 a73f 435a 3add 3ef7 40b4 3fbb 3ccb 3f90 50b6 92b4 c7dc d258 cef5 cd3c cd5a ce64 d083 cfbb aae1 5bf7 39c4 3a0f 3c40 3dd6 3973 3662 3535 363e 3614 3e95 8071 c657 d424 d3de cfa1 7a9d 3a09 400b 41cb 41d9 42ea 4017 3e87 3d3d 3bc3 3b9b 3b22 3d10 883c cf36 ce6d ceb0 cff4 d01c d00f cf60 cec5 cf4e ceec d10f d586 cd4a 63e3 3e58 488a 7296 b8e6 d3cf d113 cf8c ced9 cfe2 d121 d15d d238 d4a9 d845 b37a 66d5 48c5 479c 47af 4891 49ce 4982 4f76 78b6 c1b9 d65a d170 ce6e ce0f cff4 d169 c639 5f6f 341c 366f 3aa9 3bb0 3c02 3a34 370e 3500 3550 3755 36d1 3676 34e7 338a 32a0 335e 371e 399d 3a63 3dda 40ea 43df 45d0 43c7 44b3 7086 d092 d6f3 d238 cfbc cee6 cf1d ce9c cf8c d248 d3b0 d3b0 d3bb d409 d34c d1fc cff9 cd8d ccc8 cbe4 cbd4 ca6a c80b c674 c791 c432 71ca 2ce0 2d72
c940 cac8 cbb4 cbfb cce8 cdac cd66 cc9b cd4e cdde 8dfa 3bea 3bc5 418b 4236 3ee6 3dc0 3e59 3ead 4c26 7626 a99e c51a ce77 d0ac cc42 bb11 8f13 5604 3d0e 3af1 3c8e 3beb 3a5f 365f 35b6 368d 3806 37ec 7133 c2c8 ce7e cc7d cbf1 cbbf a741 4813 3d78 404b 3f33 3eae 3cea 3bba 3b78 3b32 3ad3 3bc6 522a b521 d434 d19f cffc cf9e cfef cfa3 d04b d10e d28a d47c d782 da3c d2be 9203 7e92 a520 cacb d57b d3b8 d16a d0a6 cfdb d0e1 d1f0 d286 d52b d940 c177 68e8 46cc 45fa 49b9 4aef 48db 4781 46d4 482b 4fae 7f3e cd16 d562 cfc1 cf05 d3c5 d6c2 a5ca 4382 3432 37f0 39ea 3b45 3dcd 3e6c 3c56 3835 3535 3ab9 52ad 73bf 8592 872a 76de 540c 39c5 3567 39a6 3cf7 3f41 436d 45d6 44a1 44eb 6f88 cfcf d4a1 d0d2 d122 d151 d046 cf8f d0d6 d2ac d440 d46f d46c d4c4 d36c d16b cfab cd9e cc23 c9fb c904 c7ce c55f c4c0 c49b c740 a2dc 3980 2a5b
cb21 cb8f cbc9 ccae cd65 cd56 cc79 cc91 cd84 ccea 85b8 39ea 3a29 3f39 4086 3d86 3c7c 3b5b 397d 3c64 435c 50da 64d3 7702 7ba3 7005 5abe 460c 3ce5 3949 3a72 3bec 3c07 3a43 383d 35c0 351c 3712 4919 adf7 cc4d c800 c6cb c853 cc04 ca4c 84c3 423a 3e54 3e7e 4033 3e58 3cdd 3c5c 3b67 3a6e 4520 8a56 d212 d453 d1e1 cfe9 cee8 cf0c d0ad d2f1 d512 d65a d9d0 ca44 a173 821a afea d615 d845 d511 d2c2 d0c8 cf8a cf60 cf87 d0d3 d14c d20e d618 d62e 88b7 4899 46ca 4727 4726 471f 46e8 45f7 4455 44c5 465a 5586 a782 d92e d4b4 d4d8 d942 c649 69c3 392e 368c 3831 39de 3afa 3b25 3ac8 3bf5 39d0 4b48 898a bd82 cf65 d0f8 cfd8 ce7d be0e 872d 42f0 33e6 3bad 3f59 4405 45b9 454c 4897 819a d463 d351 d03f d244 d35d d267 d107 d1cc d346 d601 d6ef d7ab d730 d598 d44e d298 d06a cdac cac8 c971 c855 c639 c484 c3ae c6a4 ba16 4d3c 2ba2
cc30 cbc1 cb47 cc4e cdc3 cd4b cce1 cd80 ce26 cf3a 9374 3c06 3a3c 3ed3 41b4 4169 43f4 4359 3e6f 3e21 3dee 3f01 402d 41dc 42b7 40dd 3e07 3a72 3982 3a85 3d31 3cd7 3c47 3d9c 3b76 37b3 35d1 387d 6e7e c6b1 c90e c690 c655 c9ba cedc d465 ca09 8151 47d5 3def 405e 41da 4099 3cb8 3b5d 43b8 7caf c92c d737 d3f6 d1b0 cfee cea7 ce5c d0f2 d4c2 d850 d7f5 b1b9 6f87 4ccb 48e5 94db d873 d41d cfdc cf0b ceba cdcb cea9 d001 d02b d0f4 d2ce d761 c1ac 5bec 4188 42a7 4164 40fd 4246 42d8 42c8 4259 42fe 4183 46b1 7d21 d788 dd0b dc13 c61d 7b91 43f6 3ad8 39b9 3a4c 3c5d 3ab9 3983 3886 384b 4e03 a1a2 cfb6 d291 d0bd cf21 cee4 cf5f d157 ce25 9d10 47d4 39c2 3fb5 447a 47be 476a 4fba a648 d907 d4a0 d0be d28e d3e9 d3cf d2b6 d21e d2fe d5c5 d80b db16 db00 d92a d838 d721 d411 d0ea ccd7 ca60 c91b c813 c5a0 c433 c869 c218 5531 2b40
cca6 cb96 cb00 cb90 ccf3 cda8 cdab cd40 cec4 d139 ac8f 4465 3ab2 3f47 4318 42fc 41df 419d 41e4 3fb8 3ee8 3ff7 3f9f 3d0e 3bdc 3bbc 3ae6 38b4 3b3c 3f70 3fd6 3f6c 3d7e 3cd9 3b50 385a 379c 3e64 9218 ce30 cb05 c963 cab6 cddc d271 d67b d944 ce44 98b2 5e37 459f 3df8 3dc6 437e 5bc7 9334 c7f0 d434 d310 d2c9 d1fe d140 d071 cfc5 d194 d5b5 d967 af13 5f10 46a8 43ca 433d 6fe2 cb2d d322 cf8b cf44 cfa4 cf43 cfbb d08d d015 d11f d373 d6b7 9908 469d 4048 4198 3fa6 3f39 4183 41a2 4100 4207 423a 4361 4b88 73c5 cb3b cdcf a818 6c8c 45bc 4012 3e0b 3b0a 3bf9 3d14 39bb 391f 385c 421f 942f d12f d119 ccb5 caf0 ca90 cb2d cd46 cf5e d3e1 d327 8bae 3f91 3dbf 3fa5 43bd 46b2 6c6c cb13 d8d8 d4ae d149 d22e d472 d67a d610 d46e d4f6 d63c d2b8 c38c b3dc af48 bbc2 cf7c d808 d637 d16a cd75 cbbc cad0 c7d8 c693 c9ba c104 51c5 2d73
cb95 cb6b cb88 cb9e cc7d ccc5 cd28 ce40 cf47 d1ba c679 62e5 39d8 3ecb 40fe 40d2 3fb6 4175 424a 409c 3e87 4023 3efc 3cbe 3c59 3bbc 3cc3 3d64 3ee7 4183 4168 4265 4153 3d97 3b91 38e0 3a93 43a0 a3ac d07c cd74 cc43 cd62 cff6 d276 d4c3 d58e d509 d16f c29d ab5c 9754 94e8 a7c0 c1c3 d235 d3c5 d108 d0c4 d200 d206 d344 d2d0 d1c4 d2b9 d723 c537 6821 45b7 4747 469a 4624 567e a5f5 d92f d558 d16b d023 d0d7 d0c8 d0cf cfe0 d116 d58f c2c6 639c 401c 3fa3 432c 4219 3fe5 40ae 3f0d 411a 407e 49b5 700f a11c be45 9808 68a5 5456 4791 412d 401f 40b3 3fee 3f73 3eb6 3d61 3c7e 3d69 6894 c789 d3cf d01e cda3 cd2a cd14 cdef cf00 d0df d473 d90e c293 578f 3a18 3bb7 42d8 59fc ae7d d965 d806 d41d d22f d175 d399 d6d7 d8b8 d969 d852 b722 7edf 5e36 5511 564f 5d81 76d8 a6eb d2eb d89e d235 ce6d cc2f c9fe c8f2 cba9 b69d 44d2 2fef
cb70 cc23 cc2c cbde cc51 cc8a cd2d ceac cfb8 d190 d12e 9c6b 43c9 3b4d 40dc 43b0 431a 4429 42b8 40a4 3ec0 3e0d 3e37 3e8c 3cc3 3b45 3b2e 3e13 4150 432a 4184 3f7f 3d4f 3bf0 3ada 3934 3c83 4488 a2fc d066 ceaa cdff cd8d cfbe d1fc d29d d247 d220 d1ea d1c7 d38d d392 d2ef d517 d5a5 d55a d40c d30a d334 d339 d355 d472 d3bc d3a4 d5f4 d6a0 9567 4a80 47db 49ee 4922 4860 4dab 6f6a bfc4 dbdf d787 d4a0 d405 d404 d34c d2e9 d56a cb21 80c7 469a 42e9 43e9 44e9 421f 3f1f 3e71 3de1 3e6f 4d88 921a cbd6 d9d0 d9b8 8e3d 4628 440f 455d 4513 4417 4314 4210 3f8e 3ea5 3f13 3df0 4716 9a23 d5a1 d352 d1e2 d11e d07c d082 d09e d131 d237 d411 d82c d6b7 7c4c 3a5a 406c 5faf ab96 d8e2 da64 d68c d36e d2a0 d241 d312 d56b da66 dafc ad45 5e09 43f4 44f8 4715 4857 4947 4aee 5ae4 949f d383 d63c d04d cd41 cbf2 cb47 ceb9 97f5 3858 3306
cc78 cd0f cce5 cc99 cdf5 cddf ce06 cfa6 d01a d166 d2f2 cc47 84e4 424b 3d4a 40ea 41c3 41f4 3e99 3d2d 3cbc 3b08 3ceb 3d4a 3cd1 3c37 3c5d 3e29 410b 41ab 40e9 41a3 4111 411b 3f3c 3bf0 3c03 4370 95bd d411 d0f5 cfa6 cea5 cf77 d0df d07a d02c d06a d05f d141 d2b6 d3f0 d539 d6e2 d785 d7a5 d66b d4b4 d489 d498 d4dc d555 d4cc d402 d667 cfa6 6f23 46a4 4924 4b1b 4cb6 4a72 4a3f 527b 751e b6e7 d989 dda7 db76 da8d dace d911 c450 819f 46f5 3f8f 42eb 44aa 451c 4320 3fd7 3ceb 3ca2 4658 948e d18c d4bc d381 d676 ae4f 4d56 4168 4342 46dc 46bb 4347 42ac 40a2 4119 406e 3fb3 5d4b c09c d676 d33f d2e1 d2ed d2b2 d375 d28e d2d8 d39b d630 dad2 d8fd 9e4e 65cc 8bbd c124 db7f dad9 d83f d5ef d3e3 d2ae d1b2 d215 d4bc d936 b868 5e34 41a1 4418 464b 46f5 47dc 4832 46df 4b13 5c72 a50b d7b3 d2b4 cf8d cec4 d1e9 c62e 6431 33f6 35ba
cdb7 cd7e cd42 cd84 ce93 ce6d cec1 cfe9 d080 d17f d359 d583 caf1 8cc9 4f02 3f4a 3cf4 3c8c 3cb9 3e3c 3d51 3d12 3d18 3e26 40cc 404b 3eb4 3dec 3e18 3fa2 40ee 42c5 40a2 405d 3f19 3c9f 3b1b 4365 7a28 d1ff d477 d0ea cf48 cfe0 d060 d02e cf1d cfa1 d0f6 d2dd d451 d578 d72e d892 d8db d958 d7f4 d6bd d4ba d371 d3fe d46d d552 d403 d4c7 c5c4 5b7a 4564 4847 47f7 4b14 4a8c 4873 49cf 5104 64a4 8cbb b22b c357 c526 b9d2 9770 6a79 4a4c 3e3d 3ef3 3f7d 40de 42a6 41c6 4004 3d49 3ef5 750d ccf6 d3ee cf64 cf10 d121 ca79 76fd 3e65 405b 44d0 4741 4748 44b7 4501 4665 444e 4a4b 9238 d6ac d771 d575 d4dc d48b d547 d618 d576 d592 d81b d55f bb3f 9675 a327 cdcb d8c7 da93 d935 d655 d47d d3b1 d390 d224 d128 d15c d515 cfe9 77a6 428c 4514 48b1 4926 48e7 4962 47a4 4652 46ee 4bd5 7002 cb25 d7f4 d371 d513 d2ac 8fcf 3ebf 361c 3817
ce6b cd43 cd0e cdcd ce8c cec2 cf64 d036 d16a d255 d2ee d37c d5b2 d1e6 b406 84ad 58d8 3cb8 3aab 3de5 3c08 3ba6 3db6 4048 3fed 3e20 3e13 3ccc 3d1b 3e50 3e47 3cf3 39b2 389a 3a0b 39ca 3b02 419a 5c52 ba94 d915 d24a d02a d0c9 d10e d19a d1a4 d24b d370 d646 d871 d97d dad6 db21 dad1 d988 d908 d746 d565 d469 d542 d562 d662 d5f1 d635 c464 57ea 431b 46f5 48f4 49c8 4ae5 4b67 4b39 4ae5 4d9a 51b4 5c01 6296 6352 5c4e 5172 49db 456b 4360 43a1 41b7 3fd2 4051 4021 3f9f 3ecb 4a52 aa2b d444 cf4a cd49 cd47 ce46 d14b ba09 63b2 3edf 41e7 44df 46b0 454a 4480 459f 4f76 8517 d099 dc3d d92d d84c d7e6 d78f d721 d7ed d947 db1d cea2 8fbc 5775 4a5a 8281 d8eb d883 d674 d4b8 d340 d2d2 d2ea d41a d34d d21b d232 d806 b703 4e50 40af 4494 454f 464c 4746 477b 46ed 45a6 442a 413c 5341 b2fc e16c dd45 d1a6 993d 4da9 3b48 3afe 3a97
cdbd cdb2 cdd6 cdab ce7c ceb6 cfb5 d11c d216 d1c5 d1ad d25f d46a d634 d6a5 d2b3 bd07 8204 4234 36dc 38f9 3b46 3f08 41a1 3f2c 3da3 3e9f 3ddf 3e63 3f1b 3ccb 38ed 3652 37d1 3670 371a 3835 3ca0 491c 7ff6 cdbf d6d7 d377 d46b d4dc d620 d6cd d688 d79d d99b da27 da79 db28 db59 da1c d8f7 d878 d6a0 d694 d66a d5a9 d617 d5c3 d60b d6b9 ca5f 61fb 3f7e 4462 470f 4926 47fb 4709 462b 4700 48d3 4809 4b85 4a5f 4c16 490f 463c 4725 45c7 43ab 4293 4249 4281 404c 3e1e 3c0f 3c80 5d81 c5d6 d288 cddc cc26 cd1e ceaa d243 d3f4 ba69 7836 4d46 417d 3f4a 3ed5 43a9 5b7c 9685 d28d dfe5 dcdb da2e d8e6 d896 d915 d86f da5f dc8a d191 85ab 4c69 4280 447f 683d c912 d6c1 d2cc d176 d146 d21e d268 d3b6 d391 d26a d4d3 d783 8be5 4115 3fb4 4208 4508 45ec 45c3 474f 4665 44b7 4365 4122 53af a3a4 d446 b84e 7f2f 4b9f 3d8e 3ef4 40ce 3ddb
cda3 cd13 ce18 ce06 cde7 cf3d cf74 cfa0 d05a d0f5 d180 d20f d2e7 d2cc d2ba d209 d1b7 c9fc 8db8 40fa 3931 3c60 3ee2 3eaf 3e59 3e35 3ecb 3ef9 41a5 4295 401d 3df6 3e5c 3f6b 3bf6 3b4b 3b98 3f45 4247 4fc4 8b81 cc02 da5e da56 d8cc d875 d832 d77b d8ff d9dc d8ea d895 d8e2 d831 d6e4 d6af d549 d4f0 d64e d6a5 d60c d559 d46d d402 d468 d1b9 7dc9 40ea 42bd 4635 482a 47d4 46d9 4636 4778 49ff 488d 496b 48b1 4558 4307 4063 40b8 41b9 4356 4418 45f2 469d 43e4 4006 3b10 3c1f 7074 ceb8 d064 cd11 cc88 ccba ceaa d1c5 d3b7 d53a ce7f b0b1 8bd5 7820 7b82 955c bcd2 d759 db94 dc33 daaa d971 d905 d91d d9ba d9ef dc62 dc38 9922 4e6b 4495 46b5 45bf 4f7e 9d14 d4f3 d14f cdb4 cd0c ce85 cf6a d140 d32d d4b4 d83b bb93 57f8 3cc0 40f9 432f 44ee 44c8 448e 4651 43ee 41bb 563d 8886 b420 b6d8 7363 53cc 4427 3e29 3b89 3d12 4108 3f1e
ce0f ce13 cea0 cea7 cf8a d06f cfe3 cfcd d021 d08d d108 d152 d0c0 d025 cf98 ce2e ce98 cfed ca90 809b 3b04 395f 3c47 3d03 3d8f 3d9a 3deb 3f9c 4242 442f 4336 459a 4593 44ae 451a 442b 425b 44d8 4383 44f0 51d6 7e3c b7b4 d604 dd91 dd17 dae2 da29 dbf7 db6b d9c6 d930 d830 d6f6 d5a3 d558 d44f d47c d4eb d532 d572 d531 d47d d374 d495 d783 ae5b 4e1f 42d7 476a 4697 4827 4a8a 49d8 486e 4718 45b7 4594 45ca 44ce 430d 41c7 40fe 4079 44d3 4505 44df 4583 44ca 4271 3ed0 4160 79b5 cfe0 cf47 cdc0 ce0e ce16 cf42 d133 d3eb d5a4 d7b8 d91a d7ab d43d d4f8 d7ed d7d8 d647 d69d d848 d874 d942 da4f db29 db15 dbff df15 c745 61e0 46b9 479b 4a2c 47c2 476d 636b b349 d52e d267 cfb8 d0dd d23d d326 d619 d94a c7f0 733f 3e6d 3cfc 41bc 446c 445e 4376 4265 43da 41c2 677c b392 d86d dd37 c6af 5a82 3e7c 3fff 3fbd 3dde 3f04 3fe1 3c4d
cf40 cfd6 cfb3 d13d d1b9 d156 d0c1 d08a cfda d012 d076 d0e3 d082 cfd4 cf51 ceb8 ce00 ce2f d1a4 bb43 5302 362e 38e3 3ac7 3d27 3e78 3f6b 4160 4370 45d0 4576 47f0 488e 491d 4735 43f9 443b 454e 474c 4772 4704 4ead 61c0 8292 ad1b d553 e05a dd93 dd1f dc75 da0d d7c9 d6f0 d5a7 d470 d459 d482 d41f d408 d468 d5a7 d59a d5ab d68c d8e1 dc25 d505 831d 4751 45a8 4772 47fa 4a44 49de 4a3a 4a06 4a33 4903 485c 490f 4716 46f3 44de 4490 4632 4586 431c 4235 40b3 3f18 3d8b 4155 72eb ce25 cfc4 ce4d cfcb d040 d0e0 d26b d476 d567 d674 d839 d9bd da4d dad3 d9b8 d8f8 d80f d6c6 d70d d63a d618 d6fb d845 da3d dac4 ddbc a199 4cdd 472d 482a 4ae9 4b74 48d9 4cf6 69c7 af13 d3f7 d994 d9df da3b dae6 d86e bccf 755f 4041 3dce 40a7 43ac 44f7 449f 4462 41a9 4291 623f bd36 da2b d8b5 d89e d41d 7bc2 3e37 41c2 43fe 4375 4372 4238 4004
cfdd d09a d13d d283 d2b0 d258 d28a d180 d0f4 d1de d1a5 d1d6 d1ad d1b8 d127 cfa4 cdbb ccf9 cef8 cf2a 7e88 3613 36bc 3af8 3d57 3f69 41b3 43ec 453a 4865 4723 466b 46fe 46d0 437e 41ce 4277 4510 48c7 49c3 4779 478e 4be1 5290 6103 8cdf cf36 e208 dedf dd56 d930 d689 d642 d567 d463 d4ac d52e d5bb d5ec d681 d7e5 d7a5 d780 d8be da34 db5e dc1e c68a 7463 4933 4321 433d 43f9 4424 449c 4653 4760 46b6 4701 476b 46f2 467b 4526 45d8 4673 4721 462f 43f0 3fc7 3da8 3cbc 4018 626c c718 d4b2 d1b3 d1d8 d22a d2ee d369 d3b9 d50a d610 d73a d7a7 d885 d959 d949 d925 d8ca d7c4 d751 d54c d375 d372 d416 d6cb d941 d860 828f 4789 4667 46a5 46e7 462f 4742 47ea 4a79 5e41 8780 af5e c043 c053 b0b9 8c11 5e53 427c 3ee6 40e4 4393 4436 444c 4458 42f4 418a 50ba ab7e d9b6 d69c d501 d7b6 db07 b5c1 55c5 427c 4346 43b7 4422 43ad 4271
d06c d024 d0a6 d156 d2d8 d402 d422 d412 d408 d3d7 d394 d3bf d2aa d17d d0bc cf7b cd2b cbfe ce90 d208 9f66 3b69 3719 3bd5 3e7d 3f81 40fb 4387 45df 4591 40b2 40a5 410c 4102 3f6f 4235 4449 47af 4a44 4917 4a39 4b47 4bc4 4e3e 514f 5bf1 8c9f d826 e1ae dc1c d889 d63f d64a d67a d585 d59f d69d d78e d816 d82c d7c7 d837 d7ba d851 d8c0 d8c6 d956 da16 c9c7 91b2 5bfb 4600 3eef 3de4 3e62 4052 42b0 4374 4386 44cd 4565 455d 460f 45b4 4442 44ef 4419 4037 3f07 3eb5 3c66 3d31 4f39 a8b8 d7e1 d356 d1f5 d23d d2a5 d22c d297 d3f5 d501 d6b6 d707 d7e4 d832 d85d d84e d7c6 d680 d5db d4ca d38b d2ae d32a d479 d767 d46a 75dc 42ff 46d5 44ff 44d6 43ca 4249 4154 41d0 45e6 4a8b 52ca 57e0 5708 5002 44ba 402b 3fe6 40c6 3fae 4263 437d 4454 430f 4093 443b 7822 d329 d740 d404 d576 d75e da6b d8e0 9c94 4f71 4036 4168 4073 40ad 3fd7
cfc7 cff0 d181 d2e3 d4a6 d4f9 d4c0 d5e1 d7a4 d6df d553 d5db d4ff d2c3 d1b6 d073 cd60 cc28 cdb0 d0eb a949 3fdf 3a25 3cdb 3dfa 3e45 3f26 3fdc 402e 407b 3ee2 3fd2 40f9 41e5 4168 4402 4641 47ed 48b6 4821 49f4 4d2a 4ed6 50eb 4f72 5048 615b a9e7 df5f db10 d83d d62c d5bd d553 d534 d4dc d493 d5a7 d645 d708 d717 d7a9 d79b d7d1 d778 d6be d7ae d7ec d997 d6d0 c37a 9a87 6058 3f26 3d66 3fb8 412d 425e 41c3 4328 455c 45e1 450b 4479 41d6 4135 41b1 4066 4051 4366 4250 3fb0 42de 73d8 cabe d8f2 d4f2 d492 d344 d2da d3d4 d505 d591 d693 d6c8 d7fc d87c d8df d8d6 d81e d69f d5a6 d4b0 d46d d446 d421 d48d d74a d4c9 7e7e 4319 4670 4670 45bc 4724 4647 45d8 4402 4374 410a 3f5c 3ef3 4165 40b1 405c 3dfb 3f12 408f 3e9d 3f18 4027 3faf 3db1 3d14 4920 9e55 d9c7 d514 d253 d3e0 d5dd d81d dae4 d6ca a7bd 6916 48f6 40df 3e96 41e3
cfe9 d292 d53c d1d0 bcef a178 90a8 90fd a283 bd71 d384 d969 d75a d51d d33c d154 cd4e cb74 ccf8 d05a a7ea 4002 3c50 3ea8 3e51 3ec9 3f05 3fad 402b 4187 42f8 435f 4429 4580 44ee 4599 4590 470b 4643 463d 4715 4a52 4d6e 4e74 4ba3 4c33 519d 788d d0fc d8ae d5a7 d517 d4d2 d4e4 d504 d46c d41d d5e3 d6f9 d789 d7b4 d7df d938 d987 d88a d707 d6f9 d7b2 d82d d90f d8f7 d6c0 c12f 7b43 4382 3e3f 4013 41cf 4355 440f 469f 459b 45af 46db 4666 4424 4688 463b 45f9 484d 473d 447b 423e 4cf3 8d22 d293 dcf6 d8cb d576 d4d4 d5b5 d636 d6b5 d771 d7cb d7f8 d838 d86b d7f8 d6a5 d524 d4a9 d49a d4ab d553 d5b2 d615 d73c d773 9ac0 4457 43d2 4707 449f 45b6 460c 46f2 466d 4566 4069 3ed2 3dad 3e8b 3dcb 3e58 3d18 3ea9 40dc 404f 3fac 40ef 3f1c 3af7 3c0d 4ddc b211 d6f4 d0ef ce55 cf92 d21a d4b3 d656 d94d d9e8 cc08 aeba 9729 9421 a2b7
d16e d4cc c700 8c9b 5a6c 49dc 46bb 4761 4e65 5f82 8bd5 c713 db81 d7c6 d45f d068 cbd9 c98b cbfa d032 9b57 3f90 3d9e 40a7 404b 3f19 3fcd 40e3 41c7 4144 42cd 4396 4520 4759 46aa 456c 466a 469a 4772 477f 48ac 4d48 4ec6 4d0d 4bd0 4d69 4e21 6004 bd61 d9ab d623 d51a d46d d538 d5d6 d5e7 d68d d746 d884 d93a daee db69 dae3 da3b d84b d70e d633 d540 d58b d559 d506 d5ef d86c c8fa 6fcf 3e40 3dce 42a2 45c6 4638 4675 45a0 46ab 466d 46df 45db 46e6 47e6 4880 4848 4979 4842 4644 44e1 52d5 885f c481 d891 da83 d927 d7a4 d6e4 d721 d74e d83e d8a4 d7e4 d7d5 d71b d673 d5c3 d4b9 d4d3 d4fd d4f8 d4e9 d426 d441 d5e1 bda0 565c 3c70 4031 4199 4335 44b8 4425 442c 439f 412d 4014 3e88 3f20 3f05 3f5a 3e40 3f8c 4117 4082 3fe8 445f 4394 3bcb 3a3c 4c1d b58c d41e ced0 cd2b ce07 d017 d275 d463 d5e4 d754 d877 d88c d889 d91a d99b
d3c5 c2ac 764c 4697 3f5e 40c3 4297 43d5 489b 4bc3 54a1 7935 c24a d915 d4e7 d085 cbe8 c933 cc8b ce35 7cdb 3df6 3ed4 3ffc 405e 402a 40ca 4278 4227 4235 4237 43f2 45d0 4691 4592 44b2 43c7 4381 446e 451c 4a11 4ecf 5086 4fa5 4e9b 4e47 4e37 582c af54 dbeb d85c d6f6 d550 d5e7 d5af d4d9 d4f5 d570 d780 db16 dd0d dd11 dbe9 d91d d659 d5de d4a4 d398 d3e7 d3e0 d42e d476 d5b4 d87e b407 4f21 3db9 3f64 427f 43ca 44f4 43ee 43ef 44e4 4679 475e 47a7 48c6 496d 4910 48c7 4988 49b3 49bf 48f1 4dc9 66f2 8c71 b959 d988 dd5f d8fe d849 d7ae d82f d976 d915 d891 d7ae d718 d827 d7ce d72f d6fa d60e d4ea d33f d2f6 d47b d343 9218 4252 3987 3dd4 41d7 4413 4559 464b 441e 4229 4104 3e77 3f10 3fa4 3ecf 3e51 3d3f 3fdb 3f78 3f28 4423 4560 3f37 3a89 49f6 af3e d7ea d0e3 ce05 ceaf d036 d17d d35f d34f d448 d5c9 d6aa d6e5 d7d9 d7ea
cb92 7cbe 3faa 3c2d 3ee1 3eaa 41fb 448e 450f 47f0 47fe 4d41 7aa4 caf4 d66b d1f9 ceeb ce06 d3b4 bb01 5ad2 4051 3f80 4025 402a 3f9c 4057 418d 4079 4061 41de 4c79 6c0f 8aed 9736 9434 8036 5e13 448b 42cc 48d7 4ca9 4d9a 4d22 4d5c 4f8a 51cd 5864 b049 de5d daec da85 d970 d8aa d7cc d75e d7bb d929 da8e de45 dfe2 df19 de53 db9a d94b d790 d6d1 d6c6 d79f d7d8 d77d d66c d642 d668 d244 781b 41b4 3f9d 4315 43c8 45ef 4804 4a45 4aac 4a0c 48c3 47bf 4688 4774 48d4 491b 4b01 4cbd 4f33 4f18 4bb4 4bea 5021 6428 9822 d4c8 e003 dbfb daca da06 da45 d9b0 d86e d7f8 d810 d88c d9a6 d930 d8b3 d8bb d7d3 d637 d4e1 d52a d658 ccc9 8540 42ff 374c 3a41 3dd2 4264 445f 462e 442f 4107 3e19 3ce7 3cc1 3e4d 3dc7 3ca0 3e27 3efa 4058 443d 4622 416b 3b7a 4822 99ae db3e d476 d0e5 d12f d16a d1c2 d2d3 d1ec d289 d439 d597 d50f d5de d63c
a3cc 471c 37e3 3b16 3de6 3d5e 3f28 42b1 4450 4708 4571 461e 5098 9dd1 d49f d1f8 d2b3 d782 cc2f 7eea 45d6 422e 420a 4271 41f4 3fb0 3f6a 4069 40f8 4598 6831 a736 cc94 d6e9 d65c d25d cff2 c127 9190 54b8 4268 48d3 4ae9 4b02 4c0a 4aa6 4c64 5d4b bfbe de84 dc08 db8f db40 dae0 dabf db09 dc96 dcce dc1d df01 e156 e2d7 e2fd e072 de64 dcd0 dbaf dbc5 dbbc db96 dacc d9a7 d764 d770 d8e9 9fb9 4b9f 44b7 4602 4911 4a1a 4b7f 4e04 4f83 5008 4e4b 4bcf 4abd 4a0f 4a93 4c31 4dd9 50bf 53c5 55bb 562b 547b 5078 510b 5c5d 9777 dd4b e04c dd4d db9f dab5 d96d d7f2 d735 d7dc d7e0 d92e d9d1 d97e d9b9 d9e0 d94c d851 d81d d764 d73b cd8a 9ada 618b 43ab 3c4c 3f1f 42fc 4657 44b2 431c 421f 40f9 3fad 40d6 4150 3ec6 3e76 3fc4 3f5d 4276 4640 431f 3dfd 45b5 7672 d0c3 d867 d408 d37a d2f4 d2b1 d32f d3a4 d43c d3ca d54c d570 d58a d729
6d79 38e4 3af8 3e42 3f08 3f3c 3def 4242 4788 482e 42c3 41f3 446b 6f69 ccd4 d562 d5f9 c710 8431 4900 408d 42f8 4267 4231 3fa8 3fcb 41ce 42ac 4701 7117 c05e d715 d507 d3a9 d287 d16c d2f6 d453 d341 aeea 5ae3 4380 48e6 4d98 4df8 4c3a 4cde 70cf d0a8 dc74 da59 da00 db04 dc6d dd18 dd6b de8b dd62 dd8e e01c e2f8 e4c9 e5a6 e562 e35c e0d9 df15 de35 dbd7 d9e7 d856 d7ca d73c d7c8 d931 afe2 4cbd 4475 45cc 46be 4687 472a 48f8 4c1e 4dae 4bb2 4895 4863 46af 4642 4833 4b6f 4fc6 512b 52a9 5693 56bd 569b 52f9 5056 63ed b877 e2c9 ddb8 db48 d9dc d8b9 d73a d6b3 d702 d796 d895 d9a0 da8d da3e da53 d978 d959 d8a1 d748 d730 d7eb d558 c90b a827 6c1b 45bb 4369 463d 4586 448d 4570 4642 45d6 45da 4675 42d5 4181 4210 4095 430c 46f9 4596 4057 42d3 56f8 a28a d81e d878 d535 d448 d3fd d302 d390 d486 d3bc d515 d5d5 d6e1 d73a
41ac 370a 3a84 3db0 3f1a 3f7c 3edf 4341 464b 4331 4045 3f85 43a4 63d2 bbfb c742 a524 6c4f 442f 3fc5 41a3 41f4 4340 4340 410b 416c 4224 41d4 5a32 b5da d5a2 d213 d0a6 d0f4 d1b4 d18f d1e3 d247 d54e d7cf a65b 5072 4936 4e46 4e8c 4d22 53e6 9d61 da8c d98f d63f d746 d9fe dbdb dd87 dea9 e031 e03c e296 e334 da2f ce4b c9be d107 dd61 e568 e50d e120 dbce d7e9 d649 d5e1 d60c d835 dc33 b367 4e3f 4600 47b7 4558 4486 444c 45d5 47d4 4976 48bf 4731 460e 439a 42c1 43ca 452c 471d 4808 4a80 4e2a 50e8 55bf 54c4 527d 5539 8871 db7f dd76 da2c d911 d783 d645 d5ad d596 d708 d820 d8ce d994 d91e d9f5 d965 d8cc d74d d568 d60f d552 d3ba d425 d694 c7b8 8308 466d 4171 422a 4363 4491 4660 4678 45c0 4616 4364 414d 4061 3fe8 41d8 45c7 463a 419c 40a1 4648 6274 ac0b d857 d9be d84d d706 d382 d2e8 d2df d365 d4fc d648 d727 d6ac
3039 36ad 3a09 3cc9 3d6e 3dcd 3da9 4031 41a2 403e 4473 63ff 9534 b940 9da6 6456 4c88 4246 409b 4444 46a3 4689 45a7 4514 43d4 4155 40ba 456a 8ef2 d2ff d163 cdff cea2 cfb2 d131 d167 d13a d160 d2e4 d733 d33e 7ce5 4687 4625 4793 4c58 7a41 cde5 da92 d65a d3fe d535 d72c d8ae dab1 dd7f e065 e229 d2b6 a5dd 8024 7022 6d4e 751f 8a7c b4b4 de3a e449 de19 d907 d68e d641 d827 dbaf df7e a9e8 501c 46c9 4844 4787 4877 47d3 4759 46a1 4631 4559 443d 435c 42a8 4541 43da 4254 4242 45b2 485f 4c11 4f04 53c4 5671 561e 5467 6b34 ca88 db28 d882 d843 d7f5 d6eb d61a d63a d7c5 d947 d99f d9e6 daf2 db6d d991 d8b6 d760 d649 d5f1 d431 d19e d0ef d370 d7f8 cb8c 740a 4268 4144 4111 4317 4417 4284 4199 42e0 41ac 3f3e 3df8 3f60 4184 4385 45a8 42df 4074 410e 436f 5bbe 966b c3b5 d5dd d9bb d722 d54f d3ca d4fd d649 d6a0 d6c7 d70d
2fca 357f 3a63 3d4f 3d16 3f30 3e6e 3d6b 3efa 4b68 8812 c376 d46c d980 a7a0 499b 43c2 4692 49d7 4c10 4d2f 49b8 474e 4628 4360 40bc 41ec 57d4 bc93 d65d d02a ce21 cfa3 d055 d246 d2ae d260 d2f5 d41e d633 dce4 ad9f 4cef 4519 4e85 7b47 c413 dd2c d7d3 d48a d337 d448 d5f1 d726 d8ed dd0f df1f bfde 7aef 5c60 58d8 5996 58e6 5ab5 5f9b 6b00 9481 d4c2 e15a daee d761 d8ff dac8 ddcf dd0f 8a7f 4c08 4536 4836 4a02 4b72 4924 48ac 47ab 454e 43c4 41c3 4107 42f9 4449 4258 404e 3fb2 431a 46b4 4934 4ce6 5326 5774 5938 549b 5ec6 be5a db2f d7dc d7f9 d7d4 d723 d67e d693 d857 da0f dacf dc07 dcba dcb5 db06 d982 d80f d760 d63f d444 d256 d142 d2dd d59e d93a b36c 4edd 3ec9 3fba 41e8 42db 42b7 4195 421e 4146 4020 40bc 4017 4425 450e 443a 4568 44a2 41c6 40bb 414e 4e10 643a 8a9d c068 dca2 da6c d752 d786 d744 d692 d73a d69f
3372 3759 3bf8 3e1a 3ee9 3ec7 3d03 3c80 434e 8b3f cddb d3b4 d2ff d717 c54f 5fd4 4146 4828 4b73 4a9d 4ae9 48db 461f 4377 41f4 4177 438f 78a7 cfe1 d2de ceee cf30 d184 d2f1 d3ae d3db d40f d67d d7f2 daaf df03 c7b5 6fbd 7309 a271 d221 df9b db5b d7ab d699 d5a2 d49b d4ab d5cb d7a4 dc21 c6e4 70af 4ed4 51e8 54bf 57a5 5740 57fd 5963 59b5 6147 91cc d82e dd8a da30 d9bb da44 df04 c6a2 638f 4928 49db 4d97 4f43 4df8 4b51 4917 4710 4481 40b8 4ba7 66a3 7d23 822e 73b0 58a1 41ee 4009 454f 47df 4a65 4e06 520f 57ef 54eb 600e c134 df67 db2e d9cd d836 d769 d6d6 d6c4 d860 da8a da97 dbf6 dc5d dc5d dbf1 da9f d9c1 d87c d7c3 d5cd d435 d2a8 d28e d1c1 d4b1 d0a7 6c66 3bf3 3d42 3e6f 40df 42ab 4141 420c 4283 420c 4385 4354 4618 46d3 423a 41dd 46f6 462b 401e 3e17 427d 460f 4f24 6e03 b294 dce8 db14 d8fe d849 d7f6 d80d d596
36d8 3985 3c5c 3d90 3f0b 3e8f 3e4e 3f89 6d91 c7a6 d345 cfc0 d059 d393 d4bd 97f6 4762 41da 45fb 47c7 493a 4867 4895 44fd 41c5 40c3 5461 ad1d d4b8 d078 cdf5 d00e d2a8 d401 d4f4 d5e9 d6d2 da1a db01 ce07 afd4 a0e8 c22a d3b3 db03 db07 d92d d7cf d66d d663 d628 d543 d55b d6ad da2d d899 8cb6 502a 4df9 519f 527a 5563 55e6 56b2 56d1 565f 5608 644f b216 dfdb dc8e dab1 dcb0 d6b5 8ac4 4c70 478e 4a63 4d57 4d2b 4a08 4792 4483 41b7 4850 7475 b0f0 ce4c d509 d626 d2b5 c477 963b 5ae0 497e 4bdc 4b59 4cd1 4e49 518b 5483 6d29 cedb e2b7 dde3 db12 d92d d787 d773 d7fa d969 db32 db4f ddb1 de66 dd4c dd80 dc27 da28 d915 d816 d538 d469 d338 d216 d0a0 d382 d71f 899b 3be0 3d63 3fce 42f6 4417 42f5 4301 439d 4140 4032 4067 445d 47b0 4272 3fae 479f 4a5e 40b2 3f14 42ac 44e4 4802 4f9c 6fde c2a1 df75 dc6e dadf da79 d9d2 d7cd
3a57 3ac0 3c4a 3f34 3e43 3d8d 3dbc 4a5e a455 d2d2 cf4c ced3 d0a4 d357 d687 cc9a 84ea 4729 420c 4697 49e1 4b9a 4a26 4622 42d2 4e89 9356 d1cf d460 d143 d005 d195 d393 d500 d662 d7ce db65 d8c8 ad8a 73e8 5afc 694a c6bf ded5 d8c1 d6eb d590 d5b9 d5c4 d5a1 d659 d5bf d72b da35 e033 c719 64ca 509d 51d0 50c0 52cd 5493 54bc 5343 535c 521c 51ee 55b0 8622 dbf0 e2a0 e159 d73a 9972 5446 47fd 4621 46c2 4735 4757 46c1 4550 435d 4a06 8704 ccd2 dae2 d7cf d70b d7ca d7d0 da7b da1e b67c 6724 5023 514d 50c5 5107 52f5 5731 888a df4c e3fe df70 dce6 da49 d7ad d705 d8b4 d9f8 daca dd8d e0bc e2a5 e1c9 e0f2 df7a ddc0 dbfa da57 d8d4 d67f d3a4 d115 d159 d566 da1a 95ac 3e64 3ed8 41ed 4472 45c5 45f6 460a 44d1 435c 41ae 42ce 4698 4840 438e 41ae 47ed 4c66 45f2 434d 45dc 47df 48be 4bfa 55fc 8d8d db2b de1e dc76 dbdd da73 d8c3
3b33 3c99 3e7e 3ffb 3e73 3e08 3c4d 59a8 c29d cff6 cd93 cf06 d1e9 d5c3 d81c d909 cd9f 9383 59c2 4939 47c8 46b0 45b6 49cf 6002 9df9 d10b d67b d451 d416 d365 d45b d51b d5b4 d822 dac9 d99e a06b 5cb5 50ee 512d 5b5f a8b3 df2b d9dc d6c6 d4f0 d582 d5ec d66c d682 d6f1 d909 de0f e1fa a331 59c9 54d4 531b 52fd 54e0 54b4 51a8 50c4 516e 51e2 5338 569d 7376 cf2a e122 c77f 8b6d 5833 4bef 49e0 4803 47a0 476a 4563 46b2 482c 4c85 812d d1c8 dc4d d955 d768 d65d d6e7 d712 d8f0 dc23 dda4 af29 5a62 528e 55d4 5466 53b7 6256 b7d3 e5a2 e32a dfe6 de0a dbf7 d978 d808 d8f9 db08 dd5b dd81 d2d9 c122 b6ce bcf5 cfcb dfec e159 ddac db28 d88f d5a8 d349 d3d1 d7c8 db8d 92b2 406b 418f 4672 482c 4727 4688 45e0 457a 4449 42ff 4301 4623 46f8 45dd 4603 47c2 492c 448c 43b2 474b 4a6b 4b5d 4bc0 5169 6bfc cbd7 e0a7 deaf de1e dc25 d9dc
3bc6 3d3c 3f48 3e9d 3ee1 3fb8 3e7e 6833 cdae d0c8 cde4 d0c7 d3ad d657 d7f8 d8b7 da61 d738 c12b 9dda 8338 77bf 8375 a051 c3ad d910 d89c d6b9 d5e3 d50d d469 d4ba d4c4 d594 d938 dc66 b48b 5d1e 4cbc 5236 528d 566e 7ceb d073 ded3 d907 d666 d5d1 d63c d71d d80f d8ac dabe dff7 cee0 7349 5569 5679 57c5 576c 5520 5215 5114 51ba 4fb5 5232 6793 9160 b3a2 acb5 8a3e 6af8 53af 5073 528f 513a 4da7 4ce4 4cfe 4bd6 4db7 502a 65de c51f e242 dc1f d8bb d7e7 d688 d6f9 d6d1 d7f9 da36 de1d d966 8526 525f 5542 510c 5600 913d dbe7 e2ce e03c dddd ddba dc9b db3a da91 dc50 e162 d40b 9dd7 71bf 61a3 5f1e 630b 7375 98fd cdf3 e353 dff5 dcd4 d9ce d622 d57e d898 d8a5 7fbc 41a4 426e 45e6 492c 486e 45cc 4455 4396 41bc 42e5 444d 466b 45a6 44f3 4634 47fb 47d4 430d 422e 457a 48a0 4d69 4dbb 50ba 608b b9b7 dfb4 de9f de87 dcad dabd
3dec 3fcc 40a9 3e1b 3c91 3cc2 3dbc 6dc7 d0a9 d125 cf45 d1fb d413 d538 d66f d79b d95d db20 dbd3 da54 d805 d58c d58e d6fd d9a3 d9fc d7b1 d73d d658 d5f3 d5e9 d721 d67d d70a d9cc d452 7acb 4c03 50e0 50f9 5233 5365 5dc8 97df d958 df0b d8c6 d791 d818 d8a0 d9bb dc52 dfd0 d78b 9019 54a9 511e 546e 55ad 53ea 50cd 4f7a 5128 5073 52ef 8294 c35d dddd e27d a431 5cf1 5959 5830 558b 528d 519b 5088 520f 5228 5231 517f 54b6 8cd7 df91 e0ca dd0f dae4 d992 d851 d847 d769 d618 d7ae db2a e03f b280 5401 4d00 580c 8d04 d379 e0a5 dda0 dc2c db8e dc4c dcaa dc6b dd45 e14c d15c 8624 56e0 51fa 53d5 544b 53dd 55de 5c8e 812c c7f2 e496 e019 dc4b d8d4 d9e2 dcf2 ca21 614a 4287 46bc 483a 490c 4a2a 45fa 438c 4289 40ff 4304 4771 4f4f 55ac 4fa4 470b 47fe 49a4 4505 42b3 43bb 4764 4d1a 51d9 4eec 595c b172 dec7 dd6b dc6d db8f db1a
3e3a 3e44 4162 4079 3d1c 3c61 3f90 690a cd89 d33c d09e d1f3 d347 d47f d597 d687 d7d8 d94e d970 d908 d97a d8aa d5e4 d50c d6a1 d67c d677 d61e d5ac d5f4 d6a5 d813 d82c d91a db24 c07c 593f 4d68 5390 50e5 51b4 5124 5302 6368 9710 cef6 de10 de7e df29 df3a e018 e1f8 d321 957f 59b4 4ee2 4ff4 5229 5273 50ed 5076 5052 50ea 544a 89da d39b e094 dd4d df4b c061 6393 5a4f 5d1e 5b23 55f1 54aa 53ba 54b2 5420 5288 4faa 5b89 b4e8 e1dc deca ddb4 ddd4 dd0c dbc5 dc96 db92 d962 da2c dde3 e251 ca89 7188 7647 ab4e d834 e0a9 dc8e dacb d90c d940 d9f4 daee dcab df65 d770 8874 5196 4db1 5255 5461 53da 537a 5181 5233 5c6d 8790 d631 e232 dcb2 da77 dd4f de8d 9cec 4cc8 46e8 4913 4af5 4b30 4d53 491a 448a 40d7 4692 6333 910b b066 bd3b b673 9baa 72f3 51a6 46f6 4313 4400 4a40 507d 538a 516e 5a8a b964 dfa6 dc5d dab9 da3b da7a
3adc 3d52 4288 440c 40a9 3f79 43f3 5ba9 bebc d6c7 d1ea d1a7 d2f5 d3e0 d4b7 d54c d5df d717 d7b9 d7ba d6ca d691 d5e9 d5d6 d682 d682 d701 d65f d51a d4ed d6a2 d837 da24 db17 dd7a b032 513d 4fac 522d 5147 4fd5 5089 5175 54bd 5c7b 7976 a716 c848 d58d d567 ca11 ab3c 7b74 59da 5027 4ed0 4e70 4faf 50a5 5015 50ee 5269 534a 7736 d0ae e3de dea8 dbc9 dd5a d9e8 8d3a 574a 5ab9 5cda 5c53 5cb1 5a15 597d 5660 512f 50fc 803c d82c e1b3 de88 dda2 ddf5 de2b dd6f dee6 de44 ddda de8d d111 b0ab 9fe3 c523 d7e5 dfa1 de77 dc1e dada da5a d8bd d8ab d99a db2f de07 dfa6 aca0 53c4 4aca 4e7d 514d 502f 4f46 5334 4f7d 4e0b 51d3 632b ae53 e58d e072 df17 e033 b95a 5fe2 4762 479a 49c6 4be2 4c9c 4c4a 46ec 4313 4baf 87f3 c8c6 dcd8 de64 dcdd dc9a db70 ce1d 9613 51fc 3fd6 441a 4a0f 4ffd 52f6 52b3 66d4 cb71 df73 dc4d db58 daa3 db2b
3ca3 4055 43d7 43b3 4005 3fbe 4498 5197 99a3 d6c9 d3ba d315 d3b4 d3d8 d3fd d3e8 d47e d58e d707 d794 d5ca d582 d535 d452 d4db d566 d568 d5ed d58c d65b d739 d705 d7dd d8ef daad aa2d 4fed 501c 5395 52f4 51ed 54aa 53ca 5377 552a 568c 5f2c 6e0a 77b7 760c 6b5b 5dcc 5493 512b 50aa 50a7 4ff1 515b 5377 5195 5288 5388 5b98 ae6a e481 e083 dd22 dd56 e02c e458 cdd2 7a93 58c7 58c0 5ca3 5d56 5b7a 5906 5465 5120 6d39 c110 e0cc de48 dc8e dca8 dda8 dd58 de4e e084 e382 e0b5 b63b 7573 592a 6cf3 cf26 e428 de20 dc38 db1d d992 d9a2 d949 da39 db28 dd5e e08b d970 7a9c 480b 4a97 4d3a 4f50 5024 5108 5209 517e 5033 51ec 583e 8a58 e2ea e746 e02b b818 67ff 4933 4a8a 4b68 4cab 4dae 4d0e 4a48 467c 4bc1 8e1e d4ec dd4d da12 d9b5 d794 d6ff d7da da55 d665 9981 47dd 427a 4897 4d4c 5287 55d0 8993 da1c dce1 da58 da11 d9e0 d943
3c5a 3e4e 41b2 3ee4 3c7a 3d2b 41d3 49b8 683c c03f d848 d55a d466 d3d9 d41b d431 d4c7 d589 d671 d663 d572 d5b6 d55f d40a d4b4 d586 d553 d57d d54a d6b9 d69d d688 d6f1 d8b3 da8a b37f 525d 4dbe 53ca 5547 554f 5521 55ff 5495 5501 55af 582c 59fd 5928 58a7 5691 52c6 51d5 4fb9 50e2 5302 5303 52ef 549c 569d 5644 57ff 704a d044 e200 ddf4 de6b e0ba e32b e553 e6b7 cc5c 8945 5edb 5802 573d 54bc 53f4 59aa 7e97 c129 e0dd de21 db4e d9be dacc dadd dadc dd31 e0f8 e313 b04f 6927 53b0 512c 61fc b4a8 e501 dd7f dacd d9c7 d8cf d78c d75f d8a1 da04 dd88 e340 c1ec 5ae9 4a31 4eb5 50f3 4f68 51b5 5131 50e0 4f37 4de2 4ee6 58f9 852f ccd0 c4ff 9606 6285 4d16 4c49 4e06 4e60 4d5a 4e35 4d44 49bd 4b02 79e9 d1c9 dc8e d8cb d819 d8c3 d7d8 d65a d574 d6ca dbe3 d4d1 7717 4362 4acc 5062 50f1 6b04 c16f de12 da6e d82a d824 d828 d74c
3bee 3e86 40eb 3e8c 3d76 3dff 3ed9 433d 4de5 7ccd c78d dadd d8ad d72a d707 d6d1 d683 d59a d5ea d5e6 d4e3 d589 d567 d530 d602 d647 d5d9 d549 d4b2 d536 d705 d92d dab5 dcf0 dea9 cab8 6437 4efb 5304 5352 5286 5253 5466 5287 50cc 50cf 514f 4ff8 4ffb 531a 5404 531d 4fa2 4dc1 4e22 50d6 52a2 527d 51d5 53a6 544f 596f 8365 dd26 e127 df42 e032 e1fe e2cd e307 e330 e454 da00 b684 91cc 7e1d 7b88 8cc7 b0e3 d602 e378 e1af de8c db9a d95b d87c d899 d87f dbda e02e c164 69d1 5510 55b1 560c 5cbf 8877 d869 e2ec dce2 da76 d90a d73b d6cb d7b8 da6f e051 dc24 8b40 4d5d 4cd4 5116 553d 5207 515c 4fc2 4d71 4d4f 55a7 7f64 b23c cb91 90f0 609e 53de 50f8 4de2 4d56 5051 50d0 512d 5252 5012 4c47 5a05 b55e df6a d927 d695 d79f d94b d92b d819 d7fc d7ca dbd1 e014 ad94 4cee 4c19 53bd 688b b2bc e136 de68 dafc d90e d898 d783 d6e5
3d74 425e 4332 3dc8 3d37 3f28 403e 4399 4a8e 522f 7c1e bb72 d913 dcbc db20 d8c9 d6d9 d5de d636 d5f2 d5ad d60a d5e8 d5b6 d675 d695 d597 d4b9 d4ac d526 d85f db4a dd2a df4d e1c7 dc96 8a64 4f77 513b 5319 535b 51fb 5162 4f99 4f00 4e95 4dd5 4b5f 4c10 50e4 5472 556c 557b 52d0 5036 50d8 5235 543b 5499 530e 5308 55fb 87fc df6c e077 de4f de8c dea6 de9a df1f e010 e1db e183 e02c df2a d9e9 d910 dcc1 e10e e273 e106 dff0 df79 de2b db50 d9c9 d99d d9ea dcf3 da33 87c1 51a9 5203 539c 5591 5745 65de a3be e0af e430 de52 db53 d987 d99c dc0b e0aa df41 a697 5983 4c18 4df4 4f10 531b 5207 4ea7 4b46 4a25 5b4a a37a d4ba df48 dfeb 96bc 4bd1 4c0c 5224 510e 4d8e 4f4c 50c7 50be 51b9 505a 4e74 785d d7e4 df39 d950 d6c1 d6b5 d849 d8e6 da2f dbb5 dc68 dff8 e40f cda5 623b 5603 7c56 bc5a e279 e0fe dcad dbb4 d911 d947 d8b9 d86f
3f4f 43e0 43bf 3f5e 3e57 41bd 4365 457b 4762 4938 5059 64e3 89bf affe d21c dcc5 d8fa d874 d81a d6a8 d68b d6da d6cd d63d d665 d68b d529 d3e4 d4f5 d6b4 d940 db9b dd94 defb dfca e0b7 c2fc 6617 4e3c 507f 4fae 4e78 4d90 4caa 4da4 4f64 505a 4ecb 4fef 52dd 5402 5484 576f 566d 5410 54b0 5544 56a0 56e7 5563 5492 578d 825f dd71 e0e3 dd85 dbe3 dbe8 dc47 dc83 dda8 de8b de83 de52 dfe5 e0fc e1bb e235 e1da e102 e035 e049 e182 e060 de33 dc99 dc48 dc9c de26 c926 6398 512b 54f3 55c2 5807 5470 57ae 6b1e a10c d649 e407 e2de e07a e142 e214 d43a 9caa 5df5 4c06 4c6e 4dfe 4cc2 4f3f 4f18 4cba 4964 5385 a310 dc4f dbfd db1a dfb7 bdd5 58d8 4ac1 5101 52c9 4f71 4fe7 4ee8 4e03 4cf6 4a2e 5372 a6dc e332 de8a da0c d97b da0a db8d dc1a dd13 de1b e1b7 e37a daf1 c36c a7d1 b85e d792 e37c e1aa dd8e da90 d96d d900 d928 d929 dba0
4037 4437 432a 3ff5 4047 4319 44ec 47a6 4795 46e1 4855 4c00 509f 5b81 8019 bdb8 dc86 dbe8 d8c6 d743 d746 d6e6 d686 d637 d6f2 d627 d533 d493 d54c d73c d9a2 dbda dd37 dd3f de26 dee9 de54 afbe 63b2 4d70 4cb3 4a62 465d 48d8 4a51 4bac 4ba3 4f0a 5258 52c5 52af 525a 53d2 54fd 54d8 54ad 546f 558c 53f9 5512 53a5 547c 7311 d3c8 e2eb de07 dbc9 db68 dc80 dcc1 dc6e dbcb dbb7 dcfe de36 e027 e1f3 e27b e2bf e246 e161 e215 e32e e157 e1df e181 e019 e048 e23c bd54 5a41 55ce 59d1 5a84 5bb7 587b 5645 59c6 6376 7f8e a578 bff9 c6eb bedc a2c9 7625 53c9 4cdd 4bd5 4a90 4922 4acc 4c08 4b85 49d9 4d1e 81c4 d690 dd5b d949 d874 dbc3 d836 8d3d 4c3c 4b8e 4f49 4f77 4e4a 4e29 4cb9 48cb 4938 7b64 d319 dfb5 db10 d8a4 d90e da02 dc50 dfcb e248 e441 daef ab6e 7c0a 76c7 ce15 e32c e100 e004 df60 ddf7 dc14 d9e7 d9a7 d9de db0e dddd
41f8 4370 4088 3e4c 4059 4294 4440 46f8 47f6 4978 4a9c 4b57 4e2a 4fba 55ee 715b baeb de4c db84 d944 d8da d87a d818 d724 d7e9 d6a3 d53c d5f4 d5bd d6fc d8d7 d9d9 dac3 db1e dc2e dd4d de46 dec4 bdbd 7cd9 588d 4aec 467f 4b4e 4f27 5052 5033 4e7d 4f10 515f 52b6 516f 5204 53b6 5418 5341 50fc 4ee7 50b8 51e0 52dd 5428 62cd b4ce e4c9 dfcd dcdd dc93 ddcd ddf3 dd7a dc82 dbc5 de1e deed e0fb e2eb e40c e42d e358 e302 e252 e1e3 e134 e0ea e115 e1cd e292 e375 ba14 58d4 52ec 54e2 567e 5753 57da 577c 5399 54a0 590d 6142 6930 6985 6532 5e68 543f 5042 5185 5177 4fe0 4d3e 4d8b 4ce0 4c34 4b86 59a7 b6dd dfd8 daef d8a2 d826 da78 dd25 cda7 7fa5 5023 4bb9 4d79 4f63 4ea9 4aa4 4de4 76d5 c423 de80 dc67 d97d d7cc d847 d8fb db44 e094 e64c d806 8fdc 5ae0 4ff6 5c36 bba4 e3b3 dd99 dc86 dcc3 dbcb db32 da9b d93b da62 db6a deac
42b7 422d 3f81 3ef3 4013 4322 44ff 48da 4915 4a01 4b77 4da6 50c2 5268 52aa 5684 7c90 d021 de8a daf5 d926 d854 d792 d69c d768 d6c5 d5d8 d6c1 d770 d85f d9c9 da8d dab3 db1c da06 da4e dc02 df19 e1ca d8d9 baa8 896c 56fc 48e9 4b15 4d81 4d24 4e6b 4ff9 5166 52b6 5239 52eb 5482 5483 54c4 5621 5381 528e 51de 5303 5456 5a0b 8222 d4b5 e3e9 dfa2 de45 dde4 ddab dde6 de3b de1e dea4 e055 e185 e131 e0de e1b5 e215 e2b3 e282 e1cb e165 e096 e0fb e238 e3ae e4d4 c123 5dd5 53a0 539f 541e 535c 54de 57a2 552d 5490 5556 570e 58c3 5699 553c 55ec 53fd 537e 54bf 53f3 5114 52bd 53b0 4fa5 4dc8 5097 6bc7 d033 dc63 d8b3 d8b7 d8af db62 df32 e163 d31c a050 6f1b 5aae 556f 591a 6b39 98fc cf40 e084 dea6 dcbb db06 d8ee d910 d8fe dc0e e19a dbcd 9141 5908 5067 4d81 5290 91ef df0e e0e2 ddab dbf0 db3c da80 d9f9 d97c dae8 dc35 e286
3f75 4002 3c65 3bbc 3e95 40cd 4420 492a 48e9 4957 4b4b 4ef7 5201 531b 5237 5156 5a3b a728 de66 db60 d8be d8be d79d d6a9 d766 d786 d853 d882 d944 d9bf da1b db54 db77 dc2a dacc d98c dac3 dd80 df8d e08d ddc9 d7cb b43c 679c 476f 4b1f 4dec 4ff7 53c6 5343 51ab 53b3 548f 54c8 54f0 56a6 5b0c 5a82 57b4 563b 55a0 55b8 5820 60bc 95e7 d7f8 e4e7 e1bc e040 e027 df7e e057 dfe8 dffb dfec e0bb e097 e15e e183 e24b e2e1 e358 e304 e29d e1d6 e1ee e31a e550 e7d1 d406 70dd 58ff 584f 5a3c 57e4 5909 58ae 5867 558f 53cc 55e3 559d 5473 51b8 5063 4f05 508d 52e0 5257 4f2c 5298 5273 4e96 4eef 54ef 7f98 db49 dc63 d8e0 d9f9 d8dd da14 de04 e0a7 e1f7 e0de d3ea c124 b7d6 be7d d194 df91 e11c deef dc6b db6f dc2d dab9 d9e3 da7e de6b e142 ac76 5d5a 5304 4fe0 4e01 4ede 65d7 b9e2 e4d4 e127 dcfe dd09 dcc5 dcef dc94 df10 e135 cc0f
3ee4 3ca5 38d1 3983 3bae 3d54 420d 4734 47b6 4a23 4ec8 4fa1 504a 50a4 4f87 502b 5394 8088 d757 db8d d9dd d91b d887 d815 d86b d922 da01 daa9 dade da66 dab4 dbb4 dc21 dcd2 dd6e dbf3 db7a dd24 ddbb dced da61 da67 db29 bc70 64ec 48e7 4aea 5011 53c4 5450 54ec 568b 5484 552f 5627 56e5 57c3 5836 57f2 56bd 56c7 574b 57e2 5936 61d9 8e0b c8d7 e1db e63b e453 e3ec e3c5 e2dd e2b4 e2b0 e2e3 e33a e346 e36c e2b4 e24a e29d e22e e25e e2eb e3a9 e381 e47c e8ad e4eb 9691 5df3 5cd8 5df1 5b54 5bfb 5cc3 5ab8 59ab 57e3 579d 5604 54bf 5373 50c8 4e25 502f 5215 50c1 4e3a 4fce 5029 4dd3 50f9 571b 865c deff de36 db71 db1f d9ae d9e0 dc63 de48 e057 e103 e0fe e0ce e175 e128 e1eb e0ac de89 dcbc db85 dad2 dc13 dba1 da45 daac dd08 d6c1 7982 5392 53e4 53bc 5265 4f88 5007 73c9 be07 e1c3 e40e e1ed e0d3 e1fa e458 e2ab bee2 732c
3ebc 3b3f 393e 3718 38bc 3ba2 417f 4670 4636 4753 47d0 4b17 4f75 5135 4fda 512c 52c9 6cd9 ce06 db04 d9ce d8db d962 d94a d92c da02 dae6 dc03 dc76 dbc6 dc25 dd37 df03 dfbf dfe6 ddfc dc3d dcb5 dbe9 dae9 d907 d823 da49 dd1e a7e3 52f0 4d3d 51a1 5315 548d 5561 565e 5587 553b 56da 577e 5605 54b1 548e 5476 577b 5857 57ed 5637 56a3 5ce0 7291 9503 bfeb e1e5 e8b6 e698 e5bd e515 e3ad e3c1 e41f e3a4 e324 e29a e20f e222 e1d7 e2a0 e3f3 e3d6 e26e e261 e5d9 e941 cdbf 7781 5a88 5e7a 5fe2 5d22 5dc5 5b27 5822 5849 592a 5886 56bd 545c 52a1 518f 53d3 535f 5016 4eaa 4ec3 5187 505a 51e5 56cf 7d7b d967 dd82 d984 da0a d9ce d962 dacd dc35 dd39 dc6f dc67 de47 df42 ded8 df27 de8a dd48 dd98 de96 dd4b dd9c dd15 dc55 dce7 deda c81b 5e04 50a2 55ae 54bc 5267 4f90 4b57 52fd 6c9b a00e c9e9 dac0 dd0c d917 c7d7 9c87 6882 4b34
398d 385d 4483 5778 60b8 5b26 4def 44a1 42da 478b 4a0a 4c0e 5284 54e2 51a1 50de 5119 6804 cb8b dc3f da5b d908 d8b9 d8a4 d94a da3f db8a dcca de0b dda9 ddfe df50 e0fd e15a dfab dd6a dc90 dd00 dbdf da74 d816 d6df d7ff dbad d01c 6d1b 4ec5 5316 5317 52c4 52a3 5448 54e3 5665 589b 59b4 57b7 577a 57be 5845 5b47 5ad1 59fe 5893 55c0 559d 5cf5 62bc 71a5 9aaf d85a ea64 e897 e6b6 e57f e5ed e529 e449 e33b e325 e322 e312 e279 e39e e464 e44d e338 e324 e59b e73b e7b8 bf14 7430 5aac 5bbe 5d1e 5dc8 5f6c 596f 5a21 5a6b 5b29 58c5 54d9 53ba 55f7 59a1 59d3 5556 557c 54ad 5528 5675 5483 57e4 6ffe ca85 e045 da1b dafc d9b8 d903 da7c dc7e de01 dde2 dcfd dde2 dee7 deee debc ddbc dd60 dda7 df51 debf df1c df38 dfdd e102 e358 c07e 5836 4fa3 51f3 5241 5327 4f4c 4a28 4cfe 5370 5e91 6f54 7e3a 8248 7a83 66b8 565a 4dbe 489e
53d8 85a2 aff3 c2dd c86e c55a b838 9494 610c 4608 48ae 4ddc 5065 50b9 4dd0 4ecf 5063 6fc3 d1f9 de17 db90 d933 d898 d8a3 d8fa da86 dc18 ddb0 de50 df04 df9c e263 e294 e19e dfd7 dcd0 db36 dafc dac8 d9bf d7a0 d72b d8d7 da65 da52 8e3d 4e5d 5100 5591 5582 5520 5727 584c 5a86 5a4c 5927 56b9 5670 5772 58c0 5b4c 5bb4 5d89 5d9c 5c9a 591d 58ec 5c07 5e37 686f 9657 dfdf ed57 ea1f e834 e6fe e568 e4de e4ac e370 e2fc e2aa e208 e261 e385 e41c e278 e28b e319 e37f e726 e7c3 cc97 9668 6e2c 5c83 5c56 5e74 5c46 5c4b 5d29 5b22 599d 5604 5516 54e4 57ca 5a85 56ed 574f 5649 55a1 56ac 55b9 5773 6428 a613 e2db df40 dd00 dafe da99 dbcc dcd6 de5f e006 df89 e077 e154 e074 dea4 dd73 dcd4 dc83 dd19 dd89 ddaa dfa0 e1eb e3d3 e53b c345 5be4 5240 501c 4fa5 538a 5008 4a8c 4def 53b7 5792 5a2f 5da0 5ceb 580a 50c6 4f1f 4e25 49d2
b763 cb58 cd6f cdb3 cf3f cf7d d1b5 d205 be37 7cdc 4b9b 4b98 4ee7 504f 4d31 4c0f 4f8c 85ac d870 dc25 da5f d967 d8c3 d853 d91d dbc0 dd76 ded3 dfab e03b e104 e40c e45d e32a e030 ddfa dc58 dbc4 da23 d9af d8f2 d797 d832 d945 dd11 a389 50f5 4ff8 53c8 5512 551d 558b 5832 5a3d 594d 5647 5778 56bc 569b 57f8 5908 5890 5d56 600b 5f0c 5fcc 6087 5f0a 5d8c 61f6 6fb2 b23c eb2b eaf6 e898 e83a e6a7 e658 e64e e449 e380 e31a e30b e2a2 e34a e2d5 e268 e18c e082 e19d e44b e57a e68f e35f d3ab a7d7 7136 5c46 5a33 5b56 5c75 5af5 5832 55e1 5614 563c 5878 5a4d 5538 535a 51cc 5112 505e 5012 51f1 57a1 73b3 c5e4 e610 e1b7 dec9 dcd4 dcf4 dd3d de47 dfbc df6b dfa4 dfe5 dfc6 df3c ddb8 dba5 dad3 dc46 ddbb dd10 ddbb dfe6 e18f e30c cef5 6671 50ff 4fb3 4dc0 5240 4e57 4630 47df 4e7a 561b 572a 5984 5a41 546d 4da8 4d39 4e74 4cbf
ceec cca1 caca cb64 cc3b cdb7 cf13 d17c d5da cacc 7a19 4c82 4f12 50f1 4eb1 4d59 5972 ae44 dbf6 d9c6 d85e d8da d9b6 d9bd da35 dc73 df44 e040 e137 e0d7 d8d8 cf2e cdbb d557 ddc2 e13a dfb5 ddd0 dbac dbd6 dac5 da1c da71 db06 df8f a882 545f 5257 5594 566f 551b 524f 53b7 55a1 55c5 5500 5738 56fd 5535 560e 5818 5ab9 5bea 5ec9 5fe5 6288 650c 62ea 61de 634f 6658 8542 dc12 e8b0 e697 e752 e716 e60a e5fb e4f7 e3eb e2c3 e38f e34d e373 e353 e31f e2b3 e128 e129 e215 e333 e4e4 e72f e918 e674 c46d 75d1 5825 591e 5a15 5a6f 598d 5686 542a 55c5 57b9 59d7 5757 5324 50e4 4f69 4ea1 4eeb 4fb5 50aa 586c 7f49 c4b4 e37f e42c e10a e0d0 dfa4 df18 e01b e04e dfa2 dfd4 e005 df50 ddd3 db6f d9bc dab1 dd0b de2f dde6 de40 df2a e1a5 dcf7 8809 4f36 4c77 4b8c 4e48 4dfa 47d0 4563 4a0f 5136 5705 5950 58fa 5604 4f46 4eb1 4e4c 4b65
cd61 cc7e cd1b ce0a cee8 cffc d12a d18f d47d d89c bbdc 5d44 4a4d 4f57 4f04 5080 845e d31a db54 d772 d691 d729 d883 d895 da94 dd58 e0cd e10b cc58 9f7b 7d38 6fc5 7072 78d7 9025 bbde de66 e2bc df68 dd65 db3e dab4 dbcc dc68 ded9 9bf3 5591 53b7 57dc 56dd 5527 53e8 569f 54ef 5562 57b4 5ab7 580a 53c4 536c 557f 5901 5b9e 5e7a 60e6 62c8 62a0 62cd 6384 63df 6561 7016 c69b e6d4 e504 e590 e4cc e394 e410 e423 e3a3 e3ab e423 e4a9 e4f7 e4e4 e36a e1da e0ef e183 e2a3 e3d7 e46b e531 e556 e6ad e7af b8fb 6595 58db 5695 56f0 5a40 58da 5468 5469 5487 5486 5282 52ff 5320 5248 515e 5167 547e 53bf 532a 5aee 7358 a2f2 c908 df5a e58a e276 e094 e051 e059 dfae decc de3b def0 df21 dce6 da35 daa8 dc8d ddfa ddfa ddc1 deee e132 e1ff be16 5eb2 47cd 4b97 4dfe 5379 4d67 45ef 497f 4fb3 5735 5bdd 5d48 5a1b 53e1 5273 50f8 4d08
cc07 cc82 cf37 cfe5 d06a d1ec d289 d24a d3d7 d715 d70e 88df 4c51 4d9a 50b4 7c3c c7d4 dae6 d934 d740 d868 d8a3 d986 d94f db7e df24 e0e5 ba94 759e 5b5b 5722 5709 5c1a 5b40 5bef 6c1f 9fba d9dd e2d8 de53 dc54 db8a dba8 decf db42 81f9 528a 52e1 579b 5649 5324 5436 5480 52e9 53d0 54bb 565e 53cb 4fb2 50e9 533b 54fa 57f5 5af2 5cc7 5da0 6001 625c 6141 63d9 647a 6a06 b945 e8f2 e743 e5f1 e447 e3df e3f1 e420 e3d6 e36a e49a e620 e670 e611 e564 e3d4 e27f e378 e3bc e338 e3e9 e3aa e1aa e250 e78a e3a4 8d6d 5ab6 572a 57b2 5aca 5850 542f 52cc 52b9 5461 53f5 554d 553b 54b2 5542 5519 565a 55bb 536d 546d 56ac 608c 6fff 93bc cf8d e724 e42e e25e e0ed dfa5 ddf1 de0b df41 dfc3 de4b dd6e de48 dd3d dcea dca2 dc38 dd86 deae e0a4 dd4b a299 5762 48b0 4c0b 5139 5164 46a3 464b 4ab9 5435 5b81 60c8 5f46 59d4 55c1 53da 5094
ce0a cdaf cfa2 d092 d250 d313 d464 d634 d7b3 dc68 e111 b2ea 5fbd 6924 9869 cca6 dc7e d943 d8c8 d919 d8cb d878 d930 da82 dd3b e229 c170 6deb 53db 5306 5411 5723 5b6e 5944 5a41 5dac 68cb a1f0 e14d e3c6 e067 de1d dfbd e583 c32b 6484 565f 571d 57fa 552c 5259 53f7 54d9 5563 538b 533f 62b5 7ddd 9308 98fd 8fb6 772b 5e88 5908 5d52 5f30 5fe9 60bb 5eea 606a 5e53 6899 bb5e ea09 e897 e6ea e542 e43f e469 e64c e64e e690 e7e6 e782 e6f0 e741 e771 e75d e5d6 e525 e42e e2df e37b e2a4 e1fd e2b7 e627 e9f1 b4ad 5f74 5846 5875 5b1f 58da 583d 577d 553a 5412 54a3 56cc 5681 5385 5505 574b 55d7 52fd 4ffb 4ee0 518a 52dc 5635 5d7f 82fb ceed e712 e45d e285 e0f1 df16 de2b de07 dea7 dea5 df48 dfc8 dec7 dd6b dd39 dce5 dca4 dd4f deaa df96 dba1 b0d4 70c5 5160 4bac 4fe7 48a5 4589 470d 4feb 5701 5ba9 5d61 5be4 5787 54d3 51a1
d175 d121 d0bf d280 d55b d777 d96c db9a de37 db50 c781 b593 baef cd51 da16 dbd7 db95 d99b d8f1 d834 d75e d6f8 d7b1 d98b dd29 d654 7f47 5179 52d5 5436 5694 58ec 5a1f 59c6 5beb 5d7b 60b4 732c c36f e7f3 e495 e271 e62e dce9 8da3 5bb1 5bb6 5ed7 5e04 57fb 52c6 5368 540b 5443 599f 875c c11e dac6 e222 e3c1 e383 d9a8 b455 76fc 5b87 5f4e 6185 62f2 6146 5ef8 5c60 6dd9 cc86 eacc e8f3 e780 e5ae e508 e489 e5c4 e614 e703 e923 ea3f e99d eb8d eb99 ec1f e9e7 e7ce e57a e33d e280 e2c2 e167 e1bb e466 e778 c81b 643a 579a 573c 5989 5843 59be 59cc 5638 515c 522c 557f 5784 5305 531c 574b 5882 5384 4d6e 4e28 5196 5496 5576 5608 5f12 8f05 de66 e55f e27e e18c e0b2 df10 de65 dd53 dc8d def5 e239 e196 df49 de77 dc87 db49 dc17 ddda e078 e27f e2c8 d629 b627 845e 5903 4c4d 48e7 4783 4cd5 55c2 58ad 595d 5929 56da 5577 529a
d230 d368 d402 d55e d7ef db5d de8e dc18 bd69 8af3 69cb 8251 da14 dfab da12 d900 d941 d916 d956 d949 d8a3 d812 d962 dbcf de63 b5fc 5747 4d1f 521c 53d9 526e 52f7 559f 5927 5a0e 5ad9 5e47 61bc 95c7 e4cb e95d e93b dd5c 9c9b 60d7 5a98 5d97 5cc5 59dd 54b2 5159 52a7 5328 5b53 9d12 d8fb e2b7 e02a e02e e1ec e36e e474 e480 cd9f 8025 5efd 60bd 6458 649d 6201 5fe0 84f1 df5b e943 e7f4 e830 e6c5 e62b e68b e658 e807 ea36 ed79 f0a0 f04c eff1 f058 f0f9 efaa ebcb e8a3 e5fc e59c e473 e1fc e269 e5a9 e8f1 cfb2 691e 588c 57d4 5961 577c 5918 5910 55bb 51ed 5315 575e 585e 52de 53aa 59a3 5c56 5781 515f 519f 5465 5902 5a07 5790 5833 68b2 bc22 e5af e392 e34f e18a e070 e05c de41 dd5b e021 e2a7 e317 e29c df16 dd77 ddad ddfc def9 e158 e233 e173 e0e3 e0ee d9b4 a23e 5c5b 4d97 496f 4db6 5681 5946 584c 5761 56ce 579f 543b
d35e d4c7 d5d2 d810 d9f6 dc2c dce4 ac76 69bc 5797 5590 697b c55d e097 d9bf d7e3 d794 d77d d688 d792 d87c d8df d98e dc83 dac6 8d63 4ded 4e96 5443 53ce 5358 535d 539e 5896 5b05 5ac9 596d 57ef 7aae d682 de1d c07b 8c03 639c 5b10 5e1f 5f57 5b9b 5605 52e8 510a 53be 5aa4 9418 de78 e54a e1c5 dfc8 e046 e075 e164 e314 e523 e8e0 cd06 74b8 5eb3 61c2 630d 6298 68bc b487 e73f e598 e4c1 e67f e620 e630 e787 e8e3 ec7b f084 ed4c d9ee bf8a af36 af9c bf2a d9e7 ec06 edac ea3d e87c e647 e3ac e306 e555 e9a3 c967 66e5 5a83 5b4f 5b6a 59a0 59e3 5a06 55ff 5232 51ba 54d5 5787 5174 4f8e 52dc 57c7 58f8 55ff 534d 5492 58de 5bcc 5d93 5c33 61f5 9af0 e6ee e7e4 e5e7 e368 e1b5 e08c dfeb decd e0e2 e2ad e3c5 e3cc e190 e1cb e13a e0fb e12e e09d e07c e024 dc5c dd57 e0c3 dd29 9c0e 555b 4b8f 4d53 5431 5860 569d 56df 57ab 5926 56ba
d498 d6b1 d7db d985 db50 df15 bb0d 669b 53d4 56d5 5786 5b37 9950 dda5 dde1 d95d d63e d4b7 d40b d61d d881 d9e4 dc47 e1a4 c969 6731 4e72 5133 5541 5591 5412 52ce 524f 545c 564c 596e 70a9 97ec b91d a6ea 8116 6b34 621f 5f97 5f59 61ba 60f3 5d84 55da 51da 53aa 59a5 75ad d084 e777 e38b e123 e143 e125 e050 e101 e3aa e60f e80d e773 a3eb 5df5 5d09 5e2d 6435 97a5 de69 e6a3 e288 e227 e3b3 e4b2 e5d6 e75c ea53 ee9f e12f ac04 8355 7382 6f46 7096 7452 85de b099 e1e8 ed81 e8f8 e426 e0e6 e071 e48d e9fb b40a 60c2 59f3 5bc7 5d0a 5bae 5a85 5b04 572e 522b 5233 551b 553f 511c 4f4d 4ff2 52da 56b2 578e 53f5 51d4 5698 5cd8 60de 610e 63f1 8bcd e44f eb02 e6f0 e3b7 e1e8 e07c df86 df4a e0e9 e22a e429 e456 e33b e376 e252 e1ff e10b e066 dfa7 df66 dd56 dcd5 de89 e2d0 d2ae 7075 4e50 4daa 5335 5a03 5a0c 584e 5724 5776 5686
d830 d994 dba8 dc9a dd27 d64f 7ff9 5279 5454 58de 5852 553f 6b32 b34f de54 dbd8 d7fc d6fa d717 d874 dc64 e06f e4b8 db07 9073 5718 5349 53f7 557c 559d 5362 5439 5598 53f6 586c 8ef3 cefa e623 e6d1 a0d6 5f6b 6234 6430 6373 60dd 6139 5df8 5a8d 5462 5546 5ad9 6150 9c0c e57d e606 e377 e155 e198 e1ef e26d e2ed e540 e670 e7f5 eb22 ccd8 688e 5e52 6b8d 9afb d9e5 e746 e4f8 e228 e124 e28a e396 e449 e681 eb03 dbbd 957c 6ea5 69fe 679d 66c6 6755 6738 69e7 71dd a0c8 e249 e76d e19f de5e de79 e358 dfcf 8976 59a1 5667 575e 5a55 5a11 5b91 5bc9 5823 53e0 5322 5534 5fa5 6bd5 7019 67ed 589b 53be 56c4 564c 5471 5446 5a39 5e79 6243 646d 8a7b e3d7 eba3 e80d e517 e35f e0ea dfe5 dff8 e19f e266 e3fd e499 e3fe e3d6 e2df e0cf dea8 df37 dfd5 df4b dde2 dce1 dc92 e040 e228 97a7 5097 4f0d 54d7 5b9e 5c9e 5948 56c2 585d 57e1
d99f dcce de9b de3a deb3 b999 595d 4ef3 51b6 5708 580d 573d 5ac5 6eec aee2 da92 df68 de2f dd03 df45 e3a3 e592 d7ed 9802 5d9c 54a1 54b7 53f5 567e 57a1 5548 550b 53d4 5859 9297 d76a e41b e4ae e668 c32a 676f 61e9 6660 6523 614b 60a6 60c2 5d24 57d6 5a83 5f6a 6ef1 c3d9 e8b0 e4f7 e342 e27d e26d e29d e386 e565 e860 eb25 edd7 eca8 d7ff 91ab 98e6 c447 e2c8 e754 e48a e2cb e1e7 e035 e068 e1cc e1dc e50b e241 9b2c 66e6 605f 62fa 6838 6768 6757 65db 636d 6546 7184 b639 e772 e3bc e116 e3d8 e5c6 b8cc 6192 5488 5665 5688 5952 5aee 5db0 6002 57ed 5696 6e9b a0a1 c68e d450 d60f cf14 b3de 80ab 581d 544a 5471 53b6 58d7 5d44 61f3 6689 9844 e82a ea9a e7d9 e579 e324 e105 e01a df83 e222 e388 e509 e6a2 e7f7 e782 e630 e297 df7d de8b de8b ddff dd2b dbb9 da05 dea7 e466 b29c 553e 4e47 51a4 583f 5ab3 59ce 5996 59ab 57ec
db9a de22 dd6b de3f ddf7 9c6e 4b2a 4e14 536a 5681 55fd 56db 56a9 5723 6612 918f be66 d4f0 d8fb da44 d109 b078 7f84 5d3f 5606 5606 540b 5298 56d3 578b 562b 5402 5537 8023 d5b0 e1f9 dfdf e08d e373 e0d8 960d 63f9 66a1 679f 6500 6210 6121 5e30 5b5b 598f 5e79 95f9 df36 e43a e184 e220 e2fa e38a e320 e479 e6ed eb1e eb64 d52e aca3 9865 ce7c e915 ea67 e774 e453 e36f e24b e1ee e127 dfed e0e4 e3a3 e7cf c4e2 6dad 5f84 6058 637d 6867 6721 63fb 635b 61b5 6311 6439 8573 dcaf eb72 ea0c ea75 c993 7591 55e3 56ef 5c06 5ac7 59b7 592c 5b49 5bad 5ac7 86bf cacf e360 e436 e145 df4e e044 e346 d72d 9a84 5733 5265 5643 5940 5dc4 613b 6c18 b6c0 ebe4 ea93 e884 e65b e346 e239 e0c7 e02b e34f e67a e988 eb17 eb7f ebc4 eabb e78f e328 e09b df71 de8f dd73 db1f d908 de25 e37e ba95 589b 4e80 5163 550c 5a5f 596d 581e 578d 57af
dc2a dcbf dba3 dd65 dcfd 9094 48ea 4e05 57f4 5aba 5685 585f 54f9 53c9 5583 5b0d 683b 7425 79f9 7cf9 72ac 645a 5ac8 5718 576b 588f 554a 53fe 5480 5151 4ff5 514e 5dfd b581 e501 e20c df9e e06a e3d6 e879 d499 8655 61c5 61d9 6141 5fca 5ba8 576f 54a5 5d0d 8774 d2a5 e4b6 e069 df2b e183 e3e8 e4dc e582 e813 ebad e60f b3af 7d92 690e 6f1f c5d0 ec45 e572 e3f1 e3bf e3a0 e34c e309 e180 dfab e139 e6b0 e7ca 9c7c 6071 5ee6 6288 64dc 65a9 650c 63dc 62eb 638b 6139 615b 70e3 c662 ef18 e5f1 c046 7e0f 5f5e 5d3f 61b4 61c0 602a 5db5 5bc3 5897 59f0 8276 d552 e6c7 e39e e1e7 e009 df55 de8e e133 e364 dc40 9402 53f9 55fd 5cc6 600c 6420 869e dd5e eed2 eb07 e880 e5fa e329 e2d1 e22d e218 e52f e7bc dec4 c7fd b88c b827 c6dc dd92 e90a e6c8 e294 e03d ddc5 db11 d9fb dd60 e3f6 b52f 5825 4eaa 53f4 5747 5aa0 592e 5621 5616 5910
da18 da97 da9e dc70 dc97 9802 49a4 4db9 5692 5602 54a3 54fe 53ed 5558 5318 4f42 4eb9 4fa5 52ac 5707 5780 5762 56bc 58fa 59a1 5b46 5a05 5758 556a 51e5 5219 5544 7163 d3f7 e489 e144 de17 e072 e43b e870 eaf2 d5a4 9b1d 6d2e 5e1f 5afe 5658 563f 6707 984d d468 e6ff e428 e121 dfc8 e0ea e321 e49c e80b ebea eac7 af20 7019 63a8 5f34 6433 9e09 e436 e430 e204 e0a9 e160 e24d e22b e1fa e1a5 e322 e951 d5d7 778e 5db4 5f40 62a9 647c 629e 618f 6182 5e9b 5ee0 6039 6e45 8e8f b6fd b014 910c 6eae 5df4 5c21 5ed6 6264 60c9 5f24 5e13 5d42 5d32 6b82 c162 e8a2 e4ad e1da e0de e0ee e186 e02e dfd8 e145 e4d0 cfe9 6ada 5245 580b 5d66 72f6 c18e ebaf eaf1 e934 e7a6 e576 e279 e30f e3c2 e64f e151 b965 836b 6a56 66ed 6694 6cb3 862c bad4 e4fd e72f e24d de2c dc09 db12 dd0f e213 9b12 5259 4e6e 5366 5707 5716 571f 55ff 5559 55cb
d8de d969 d992 dafa dc31 b08e 4dfe 4c79 5568 543e 54d3 52cd 51a0 5085 4ee6 4b43 4bd4 4ade 4c1e 501c 5247 5163 5227 5654 55b4 5a68 5934 565a 5730 5761 56dd 58c6 847b dfc5 e355 e05f de69 e1e7 e467 e708 e986 e96e e3dc cd11 ad3e 9d38 9d29 aafe c9a3 e124 e727 e655 e353 e121 e045 e110 e36d e58e e9f3 ed46 ca10 76e3 653d 6374 602a 5f7c 73c0 c629 e8ef e50c e20b e197 e189 e191 e314 e3cf e82a e3d1 9e56 61a3 5abb 5cc6 60f6 62f2 621b 61cb 5dc8 5a65 666e 9a1c cdff e2cf be4d 676e 5eaa 60b3 5da6 5b60 5ae6 5b3c 59e7 57cc 5636 56fa 5de9 8ee3 e3e0 e8b6 e3fa e235 e228 e20b e1a7 e12c e10a e256 e70a e78f 930d 5295 5647 7067 b5ff e68c e7bb e536 e510 e49f e497 e408 e4bc e818 e285 a358 657e 595f 5a74 5bc7 5b27 5d8a 60bb 7080 ae6d e568 e491 df89 dcf6 dbe0 dfbf d4fa 7247 4c4a 4c40 50f6 55e1 57a0 5615 547b 5222 4ff9
d85b d919 d8fb d973 db33 cccf 69d7 4c61 5480 55be 5588 5285 4fed 504f 5255 51c0 511d 50c0 52ce 5571 58cf 598f 56ed 5587 55d4 58bd 5824 580d 5795 5999 57c0 5bef 8f25 e524 e459 e177 e100 e2d5 e407 e62c e730 e77f e6d7 e6ed e5d0 e51e e470 e535 e5c2 e521 e4e4 e4c0 e3d4 e124 e1dc e261 e436 e606 eaa8 e750 96ae 6996 6831 66fb 6606 63ac 65c4 897d d24b eac0 e974 e738 e5a6 e531 e6c3 e914 e26b aa62 6a81 5d6f 5a03 5b8a 5ddd 5e66 5df2 5d6f 5c1a 6914 b1d9 e463 eb90 ea1d d457 6e7b 5860 6189 62ba 606e 5dc1 5de1 5c07 58c8 55fd 578f 66b5 ba08 eca8 e888 e512 e484 e414 e3fd e41f e482 e34f e494 e87a e993 aff6 70f0 9248 c827 e56b e6f7 e4f5 e42b e3df e3d7 e465 e492 e70f e8f8 b3ef 62b5 55b1 58d6 5a90 5aa4 5b4b 601e 5f00 5e8b 7239 c1ec e5c4 df23 dc69 dd4b defa a7fe 5525 4cf7 4fa7 54ad 5948 579a 568f 534e 5192 5195
d6f7 d793 d7f2 d871 db06 dd2d a7fd 5731 51f3 556c 5402 51a3 52b6 54f6 577c 562c 563b 5570 560f 5a6b 5c92 5b1b 5838 56d0 58be 5ceb 5d27 5a34 58ff 59fd 59a9 5efb 8b08 e2a6 e4ce e254 e222 e325 e2ec e322 e24d e1fd e231 e371 e40f e432 e3d9 e294 e2cd e329 e43c e526 e37b e28c e385 e392 e4b2 e52a e8b6 d713 7702 6730 6902 69b1 677a 666f 6733 6bca 86b8 bc32 df2d e966 eae0 e9a8 e4f7 cef4 99b8 695e 600a 600d 5fbb 611e 5fb3 5fa5 5e63 5ce5 6318 a5b0 e6a7 e960 e742 e6d0 e4c8 9c4a 5d1b 5e5b 6268 63b9 61eb 6211 6148 5f3f 5d37 5dbf 8a7c e105 ed01 e8a6 e6a8 e56b e5f5 e763 e7f0 e871 e846 e478 cc0f aa18 ac3d d60b e363 e661 e470 e499 e4b7 e468 e48e e538 e525 e516 e7bd d4da 760d 570c 5864 5b26 5d31 5d52 5d7c 5f4b 5df7 5c6e 5fb6 910d e036 e0e5 e188 e21e bc3d 67b8 5087 5229 5392 5956 5c1c 5b47 58d1 5679 59d2 85ce
d5e3 d7ed d898 d93b dbe8 df3f d984 981e 5a32 51d1 508d 4e19 5003 52fe 573e 5647 55c6 5402 567f 5a87 5a6e 5837 57b5 57c0 5aca 5d6c 5cd3 5a5f 56e0 5813 594a 5e2b 7926 d4aa e67e e30a e185 e1b2 e2ce e32c e1a8 e10b e0ed e04f e03a e074 e02e e028 e0ed e230 e586 e5c3 e416 e2d5 e2a5 e3be e5d9 e7b8 ea3d c962 6b5b 6732 6890 670a 650c 655b 63c5 669d 67e6 7348 890f 9e95 a941 a339 9178 7880 656c 5da3 5eb9 5f79 608b 6127 6226 6282 61c3 62b3 82e0 dcc8 ed08 e7d8 e602 e721 e929 d5a9 8326 6067 5fb6 601f 5f11 60c2 60d3 5f27 5dac 7745 c97a ed44 ec34 e9b3 e743 e606 e766 e8f9 ea84 eb87 dfb6 a50c 7058 6498 91da e74f e9cb e478 e1c6 e12e e1a4 e29b e3d0 e3c6 e477 e606 e752 ac0f 594b 563b 5a0c 5b25 5ccc 59d5 5aae 5b02 590e 5855 591a 70a0 cfe4 e57d dcea b45e 6d0d 512f 556a 5415 530b 5855 5d67 5bd3 5b43 5f02 94eb db4d
d623 d7ec d816 d913 dafe ddc3 e047 d848 a2a5 674d 50b3 4b40 4d19 4f6e 53ba 5588 5607 52c5 55fd 5982 59b8 56b9 574d 59c8 5b83 5c76 5bd2 5a3a 5696 583f 591e 5c66 6930 b2d0 e733 e46b e1e4 e24f e312 e2b4 e18a e1f0 e0a9 df65 e006 e027 dfd4 dfc3 dff1 e233 e505 e4ad e3bb e2db e37a e593 e69c e961 eb8a c8ee 69bd 6590 68c5 66a8 65d6 6533 63b1 65c9 6401 6518 6796 673e 66ba 66bd 655c 6305 5de9 5bed 5d92 5c10 5af3 5c78 5e1a 5f70 5ebf 669e abfa eaf4 e9ad e8c7 e76a e863 e94b eb21 d1ed 8f0a 6973 606e 5f0f 5fa6 5d58 62d3 82cf c3fe e89b e99d e900 e8dd e88f e700 e7a6 e99d ed1c e24f 9c88 6633 5c6b 6107 7db4 d729 eb9b e596 e1c2 e0e8 dfe4 e095 e1bb e249 e4be e93b dc72 7c54 5262 55f3 5a49 5c42 6025 5a39 563d 537c 5229 55de 6762 89a9 b7e5 a700 80ab 5fd0 53ca 547c 572e 555f 5295 55ce 59d8 5bc5 5df6 8070 d8c7 ea0a
d515 d60c d655 d879 dab5 dccb ddf1 df84 ddce cafe a50e 77da 5371 4d4e 517e 539c 5451 545a 576b 57c6 56ef 56a3 5804 5a9c 5dab 5caa 5bb4 5a1c 5829 59ec 5868 5aa5 6286 80ca d159 e793 e44a e35b e211 e0e6 dfcf df59 de33 dd6a de33 dfe9 e03e dfa7 df9d e0d1 e182 e0e9 dfd4 e0ca e326 e593 e639 e6ae e83d d2aa 6fe1 6168 659f 67da 665d 65e7 6706 6682 6320 61e4 609e 5e5d 5b63 588f 5a22 5ea1 60c3 5d7b 5ce6 5c95 5a2c 57d3 5a5d 5d1b 5f84 6d0b c5f6 e8cf e5ac e56e e581 e648 e759 e900 ea17 df6c bc0f 982d 8590 84a4 9244 b3b8 d912 e618 e488 e3ed e3c2 e40b e541 e4f4 e6a0 eada eacb ab71 6698 6031 61aa 63c5 6e16 acb1 ea95 eb48 e57e e31c e227 e284 e298 e488 e8f6 e745 a8e0 580f 50cb 5796 58d1 5b82 6147 5e11 58e8 57f5 6713 9b55 ce11 e197 aa02 5a7a 501a 5135 54de 5720 58bd 58d5 56be 56f0 58a0 5a06 66b1 b34d ec26 e826
d4a1 d506 d5c2 d7aa d901 da75 dbf0 dc84 dc49 dd2b dc6d d3fe a6ed 6320 4e5f 5240 53d2 5546 579a 589d 5861 55de 56e8 576a 5956 5796 592a 5919 57fe 5aa6 595b 579a 5b4c 6236 8cc3 d25d e6bc e4b7 e1a8 e0f4 df07 dbfe da72 dab3 dc41 dd22 dd51 dd46 ddb2 deee df4b df3d de5b dede e06b e25b e375 e57f e801 e1c8 894e 5e54 61e8 646b 61e6 60c5 61c9 60b1 5eed 5d3c 5bbb 5db5 5c39 578d 56fb 5c5e 5f8c 5e16 5e18 5d50 5b7e 571a 566e 57e4 5d8a 6fec ce34 e83a e494 e343 e302 e2c1 e2df e3e4 e570 e80b e636 e382 e064 e01e e417 e7d6 e80c e441 e022 df02 df9e e026 e0c9 e131 e47c e99d d53c 78a3 5def 5def 63c9 636d 64f1 79fe bf54 eacf eb4c e625 e568 e5ea e561 e810 e4bf b626 6779 5038 5032 55f8 5883 5a50 5d12 5c6f 5ac7 703a bb6d e547 e874 ea61 c16b 60be 53dc 5854 58c6 5ad6 5d2a 5d81 5c90 5c00 5a52 5bb4 7a5b d845 ea83 e566
d1a4 d335 d401 d513 d6fb d8fc d97d d7fd d837 d893 d937 dc47 dd98 b5f8 61fc 5177 51a8 525e 5565 5c26 5c7d 55af 5568 5431 55bb 56bf 585c 5814 576d 5901 59b0 5833 579f 59ca 5f36 809b b6e8 d827 e303 e44c dfa7 daab d891 da27 dafd da5f d9e3 d9d8 dac3 dbe3 ddb9 dd3f dc7c ddc7 df91 e008 e138 e30e e653 e882 bac0 68ba 5bce 5e4d 5b93 5af1 5d31 602d 606f 5ed2 5c1f 5a89 5980 5653 568f 580a 5bc3 5b85 5c0d 5bcf 5b42 570a 5594 5640 591f 6a93 c9ec e755 e42c e25e e12e e04b e013 dfc5 e075 e1fd e253 e331 e52f e63f e5c5 e474 e1f9 df8c ddc2 dd28 ddf5 de2d de85 deb0 e2dd e691 b21e 661c 5e97 5c96 603b 600c 5e87 6290 78c3 b0f6 dc32 e925 e916 e7d7 e42e d32d a02c 6613 52c6 5186 5259 561d 5820 5949 58f5 592d 6545 b75c e812 e72a e394 e64d dc7f 836b 5487 5691 5d4b 5ece 5db1 5ea6 5cf9 5d14 5c8a 659e a96a e86a e6af e38f
d173 d220 d332 d38d d4b9 d7b4 d78f d6d8 d669 d665 d5fb d734 dbc2 dc33 9f8e 54b4 4fd1 5293 559f 57d9 5565 51be 541b 567c 5835 5923 5734 557c 54a7 5603 574c 57d3 55e1 56b3 574f 5c29 65ea 7c1e a2b5 d117 e1b2 dd00 da3a db6b dbc8 db23 dae5 da84 da51 dc1d dd9d dced dc1b dce2 dec3 df7c e006 dfd4 e2d3 e683 e183 9f7c 64ab 5cff 5b63 5ba5 5db9 6223 6289 61bd 5d60 5a23 5a7f 57e4 56b6 582c 5a14 5a37 5c23 5bc1 5bb2 5a4c 5d35 5b11 5960 651a b8ee e508 e145 e025 deca de54 de3c df28 df4f df4f df6e e018 e1f5 e33c e343 e25f e0d4 df57 dec6 deb6 deb3 df05 dfcf e040 e402 e41f 97e4 6027 5bd4 59d2 5b08 5b85 5c43 5c77 5fef 6aea 8214 9cb1 a700 a21e 9056 7425 5e0f 54b1 54b9 5590 554b 56eb 5900 5948 5852 5942 8eb2 e1c4 e685 e1cb e106 e332 e4dc c19d 6abf 4dec 530a 594e 5bf1 5cd7 5a61 594d 61cf 95a8 dc6b e780 e32d e14b
d1ff d263 d28e d2e3 d3a8 d605 d5fa d58d d4eb d4bd d40b d4cb d6f4 dc92 cf4d 6cfc 5085 52f2 545a 5596 51ef 5169 5684 5a3c 58b6 54e3 5208 50e2 519d 54c3 5458 549e 56f8 583b 56f8 56fa 56b1 5af7 6148 7e53 bf00 e1bf df67 ddfc dd61 dd51 de31 ddc7 dcce de66 de8b de86 debd deca dfd3 e065 e1ad e339 e3c2 e4be e702 de7d a4eb 6b8c 5b10 58d1 59d9 5a99 5cc3 5d8f 5cfb 5d65 5d87 5b86 58e1 5939 5979 5951 5b3a 5cb5 5bd2 5d7c 5f35 5e87 5a68 5f2a 96e0 e3e7 e564 e1d3 df6e e01c e038 e191 e1f5 e18b e0bc e0f2 e261 e218 e2e2 e1d9 e19f e040 e053 dffb e05d e0a2 e16c e2aa e5d3 e48f 9029 5ffc 5e72 5b84 5b11 5980 5bc5 5d00 5b9b 59f2 5d12 6147 613f 5e75 5af9 56c4 52de 5104 5444 54e0 541d 5640 5840 5b31 5c97 6158 bbd1 e757 e229 df94 df2a dfd9 e1b2 e354 bcba 73f1 556d 5434 59b6 5d8a 5fd5 6ea7 a1e5 dc01 e6cd e3a3 e0e0 e0d8
cfe7 d158 d256 d239 d241 d4c6 d462 d480 d514 d4bf d3f1 d418 d667 da31 dca0 8f14 5154 526b 54ee 5751 547b 570a 595f 5892 562b 5153 4e45 4e2a 509c 5264 5318 553f 5944 593d 5687 55ea 589a 59ff 5cff 5fa2 7c43 ccfc e5df e2e5 e0ba e01b e10c e1e5 e142 e155 e164 e11e e1c9 e165 e093 e192 e315 e4b5 e4f6 e50f e612 e6ff e347 c83f 9ec1 746a 598d 5409 56a4 595e 5d96 60ed 5fc8 5c6d 5a0f 5a17 5b3b 5ce7 5c83 5b80 5a73 59ed 5b7d 5d3b 5a7e 5b4d 6fec c658 e9af e582 e380 e444 e3eb e37c e44b e355 e36f e3d7 e4dc e3f4 e3ce e345 e3ac e2f2 e0d6 dfb8 e068 e247 e309 e436 e6e9 e737 9ed0 602b 5e1e 5d09 59af 5a2f 5d97 5dd0 5e04 5ae2 586a 5b29 59ca 57ee 579c 5920 5777 54e4 556f 5508 54a4 56b7 583b 5b13 5ebe 728f d466 e5d8 e158 e06b dfdb e087 e240 e5f2 e7f4 d5fd ada4 8e83 8658 8fb8 a9e7 cef4 e91d eb20 e71a e3f4 e263 e1de
d088 d276 d45c d43e d5cd d734 d6ab d5b1 d65f d60e d63e d6e9 d8f1 db20 df19 a627 55fa 5512 5956 58dc 5671 5804 5847 577b 5986 5866 5597 515b 5300 568d 5819 5c0a 5cfd 5d18 5b94 5cd1 6066 5fa5 5ff7 5ee8 6516 98b2 e39d e848 e68d e601 e4f8 e544 e49c e42e e3ed e3c1 e4bd e53d e446 e3f5 e4d2 e59d e419 e38d e377 e38f e554 e7b5 e75a d794 a261 6581 57ab 58cc 5b44 5e2f 5fa4 5dba 5c36 5df7 5f61 60f7 6009 5e71 5ca7 5c5b 5bfa 5add 5a07 5842 5efb 85af d19d e9fb e9d3 e9ce e975 e77a e75a e5a0 e4d4 e4e3 e5c5 e4fe e51a e4aa e485 e43e e2e4 e196 e1d4 e2cd e36b e4ba e7ab e909 bd63 65ae 5cc9 5dff 5a2f 5809 59f4 59ce 5c4a 5b30 58f2 5d4c 5c00 588d 58a5 58da 57e6 56a8 56f7 5657 5683 574b 578f 5a46 5f9f 7f0f de16 e637 e20a e1e4 e26e e34c e4bc e568 e759 e911 e99f e6bd e622 e8ed ed27 eeb9 edde ebfc e984 e6de e548 e506
cb8e c80a c953 d141 d9d4 dc3e db52 d9a7 d839 d8ba d9d2 da14 db80 ddc5 e229 ae21 59d7 57b9 5999 562f 545f 54fd 5446 5330 55b0 5626 544e 532f 5736 5bde 5cc1 5f89 5edc 5e13 5cfb 5c41 5f71 5fb3 6003 5f44 631b 7789 cfa2 ebb2 ea46 e9ab e7e3 e6be e5d0 e5b7 e663 e71c e7eb e8be e793 e707 e652 e5f6 e51d e406 e27c e338 e526 e716 e9bc ec22 e834 b061 6b8c 5e24 5ad8 59eb 5c5b 5df9 6029 6157 60cd 6029 5f88 5e5f 5d21 5d62 5ddc 5fcd 6155 5f9b 5e3e 64ce 8492 bf67 e302 eefb f08b ec9b e95c e809 e6de e745 e6cf e602 e681 e6ae e710 e5e1 e599 e4d0 e3d8 e356 e397 e49a e7ed ea63 ddaa 84dc 5dc0 5e8b 5d01 5b68 5c06 5c6b 5b7b 5bb1 5900 5c2f 5b67 58c5 5944 5a31 56d4 5536 55b8 565c 5583 55e1 56b9 5af9 5df1 7eb4 dee9 e8d0 e3c2 e2b2 e27b e348 e3c4 e412 e57f e6f0 e8dc ea58 eb9e ec5a ed37 ece1 ecec ec5d eade e862 e805 e870
6916 6073 62ff 75ea 9a04 c581 dd27 ddcc dbf0 d9e0 d8ec d957 db4f dd24 e208 a299 58e4 54ba 5317 5299 51f4 523d 51ac 5057 511f 5225 5316 5510 57b1 5aab 572d 572c 5752 571f 594b 5af5 5c45 5daa 5fa5 6263 64ac 6c16 b87f eb4d eab0 e94c e7ee e6d0 e61c e698 e7b7 e921 ea23 ea5f e8a1 e905 e855 e659 e534 e549 e4e1 e5b3 e647 e746 e897 e934 ecf8 e6ae 9b45 65bb 60b7 5e6b 5cd9 5e7c 60ff 6177 60d4 5fc8 603b 5faa 5da6 5e12 5c96 5ea1 61c4 6355 61eb 60ff 64f1 756a 8e38 b1e0 dd75 f071 ee3c eb5d ea25 eb27 ea5a e93a e88c e738 e770 e741 e6c0 e754 e6b6 e585 e5b2 e545 e730 e9e0 ea7f c3c2 70a3 5c6c 5d08 5edd 6010 602f 5d82 5d64 59e5 5acd 5bf3 59e6 59a4 5b6a 57f0 5636 54b0 53f4 54f4 5569 56a0 5ac3 5ccc 74e8 d255 ea18 e439 e3a0 e3d1 e37e e39e e368 e34a e40e e49e e70e e7c8 e925 ea7c eadd ea5d ead5 eaa0 e851 e77d e8af
3ab4 3c20 4048 4975 54be 6e41 a966 dae4 df0a da9e d82f d8ec db97 e012 ddaf 866b 561a 537e 517b 540a 549a 52fd 5246 50cc 5051 5107 513f 528b 54fb 58d1 567f 53fb 54f9 56ae 58c5 5d07 5f4d 5e8d 60b5 6391 648d 6a89 b0f9 ebe5 ea03 e866 e73e e70b e755 e7cb e835 e9c7 eae8 eabe ea1b ea71 e922 e7e0 e805 e864 e85b e9bc e8e3 e871 e8a9 e821 e9e9 edec cadf 6f4c 61da 6099 5d07 5d2a 5f28 60e5 610c 61fd 627f 638f 61ab 60fe 607b 6218 6075 6296 6427 6614 652f 67ef 6a8d 7086 8e10 cba0 ee07 eccb eb69 ebed ec83 ebee e9e5 e85f e75d e757 e6ef e6cc e6b6 e7c6 e759 e6ca e697 e812 eab8 e982 c0fa 7da5 5f21 5d61 5fce 6063 5ef6 5c78 58b3 589e 59ac 5bda 5c36 5cab 5a15 5984 5609 5466 5605 574b 5939 5e39 5ee6 67f8 b16b e969 e451 e22f e360 e357 e392 e347 e2bf e417 e4f8 e63b e78d e852 e890 ea11 e97d e97d e981 e841 e7db e86a
3978 3c4b 40f0 4779 4f83 5521 65ed a70c dd53 dba7 d857 d97b dd79 e45e c603 677c 562a 5699 55af 59f5 5c27 5aac 59d2 57ad 5563 561e 688c 8d07 a563 af8c a73d 8f4a 6da6 5c27 59f8 5e99 62ce 637e 6417 6513 6547 6d94 b6f8 ee8c eb52 e943 e760 e6fa e6cc e701 e7db ea13 eb23 ec9e ed38 ee72 ee17 ed4a ec45 ec03 ebe6 ebad ea6e e911 e783 e80f e98e eb40 e1b3 80ee 5ffe 6160 6035 5ec6 5f9d 623f 6543 6415 63aa 67a4 67ae 65d5 6608 66d4 6598 6454 653f 6939 6a70 6cd6 6ba2 6b2a 6da1 8976 d639 ef86 edbc ecd6 ec06 eb93 e908 e797 e6f9 e649 e5c5 e61d e672 e706 e64f e58f e5be e760 ea25 ed13 edac db8d b535 8bfe 69be 5fd8 5f2e 5d52 57f2 55f3 5773 59fc 5bee 5dda 5e1d 5e8a 58cc 5382 5428 569f 5974 5fb5 5fec 62b1 83ba d6dc ea16 e5f6 e49c e52e e48c e3d6 e2bc e4ce e661 e6fd e790 e7a8 e7be e969 e808 e7ce e7ae e7a7 e809 e916
3c87 3d72 40e1 4886 4f8f 5713 5b5b 6f5f c0bb df75 dc17 df0b e466 dc16 8f02 5c0e 5b69 5de7 5f95 61a0 637f 63b4 60a8 5a57 60bf 92c5 cb7e e1ed e53c e5a1 e64a e306 ce5f 95fc 6032 5b61 611c 65e8 653b 6582 67d7 7406 c999 ece5 eb1c e945 e856 e80b e87d e8ca e9f9 ebe1 ee10 f0ee f157 f29c f314 f281 f168 f048 ef11 ecf0 ea9c e97a e76a e643 e814 e9f7 e7e3 8d8e 61cd 646f 6366 61d7 61f9 64be 6725 64ae 64d3 68a0 67f0 66f5 698b 6898 68c6 67b8 676a 6914 6bef 6ed9 7029 7087 6d60 725c a48d ecd4 f055 ee01 ebb6 ea94 e9f0 e7e9 e6ba e6dd e6f1 e6b4 e6c0 e738 e795 e6d7 e78f e889 e939 ea69 eca1 ec3f eaaf e341 b9bc 78f1 5e60 5e62 5af7 56e8 5991 5c4b 5d28 5da8 60f1 61ef 5dc3 5697 5338 5474 56d6 5ccf 60b1 6317 6b21 9886 dc04 ed64 eb02 e805 e5ec e43a e3b9 e4f2 e656 e71d e709 e6db e6fc e6e5 e667 e667 e713 e870 e886 e957
3de1 3ed4 428a 480a 4d70 5342 597c 5fda 94e0 dfcc e436 e716 dd25 9e3b 647c 5d0e 5fa6 60b0 6286 6177 6158 5f05 5b04 6147 a29f de8d e786 e48c e2f3 e302 e3b7 e3e7 e5ef dfc3 a161 5f94 6048 6731 668e 66ef 67a4 8af7 e042 ea12 e875 e85d e8a8 e9bc e8ca ea7a ee14 f0c1 f256 f3ca ee5a e811 e6b5 e950 f0c5 f4b0 f391 f116 ee45 eb2e e880 e617 e7f3 e963 e712 8ffa 64b9 651d 650d 6379 63b7 66fe 682e 6472 6269 6327 62f9 614c 6270 6220 626d 6674 66fc 6540 69b3 6bde 6c95 6fd2 706b 70a1 8479 dadd f119 ecdf eb68 ead7 e977 e874 e804 e840 e92f e8fc e8ae e997 e9f0 e912 e99a e9bf ea73 eabe e99b e872 e8b8 e9c8 e9c0 c34e 6fcf 5d93 5f78 5a6c 5aa7 5e85 61ff 6185 62a5 62bc 5ec0 58df 54f1 569e 5778 57a6 5c68 5f8f 6330 6cd5 8fbe c372 e1c7 eaf2 e9fb e773 e6c9 e730 e7e4 e7e7 e7f4 e7ab e771 e731 e646 e5b4 e778 e921 e9ac e98e
3a9c 3f68 4187 4522 4b91 5123 5489 5b03 797f d5af e207 c715 9066 64fd 5fc2 62a2 640b 63e1 62e5 6174 5d72 5957 5dff 959e deff e68f e331 e1fe e240 e16d e266 e396 e46c e8cc de83 89c5 5cc8 64f0 6717 666a 720e bf51 ebd5 e9f0 e8d4 e894 e81e e858 e940 edb2 f089 f2b0 e6b8 c350 9fb0 90eb 8f1d 93db aaf3 d2a2 eff1 f404 f053 ebd9 e89b e79d e9f5 ec67 e4ae 871b 64e0 6414 642e 62e4 62d5 6572 67b9 684e 67e3 66ec 6272 60cf 5f92 5f88 5fb1 6202 6506 64a3 6649 6c0b 6cd6 6f1b 6fe2 6ed8 77fb c57c f051 ecd1 ea1b e92a e9c9 ea01 e983 e9c4 e9a4 e96b ea1f ea81 ebe3 eb94 eb9c eaa0 eadf eac6 e8a8 e7f8 e76c e77a ea09 e9b0 a5c0 6101 611f 5dcd 5aa6 5e1f 63a2 65f7 6538 61f6 5e85 58ee 56d0 57cd 57a7 555f 5895 5aef 5e44 630f 66cd 730a 8885 b107 ded2 ebeb ea7d e8d5 e83c e855 e903 e95e e92b e8dd e839 e6aa e765 e8fa e950 ea65
3825 3c12 3f69 4661 4c6f 52ba 6683 8b05 ae26 ab89 8899 7244 639f 602a 64a4 676a 65e6 64d0 62b1 6018 5e78 5be3 71b4 cc94 e6a2 e1ea e036 e119 e1f6 e1f4 e2f3 e446 e40b e594 e9d3 c141 65fe 6259 6767 7191 acd2 e83e ed11 e9ec e8ae e888 e907 e8bd ea62 efd9 f193 d3ba 975d 785c 71a4 7236 739b 7272 749d 838a b7ce ec1c f11b ec29 e902 e818 ea2d ef31 d192 71f1 652b 64fa 64c2 64cf 6639 681b 681a 69b4 6b39 6a5d 66ca 6483 646c 61f1 60a0 6108 6348 6583 66e6 6c2e 6f04 701d 6f45 7031 76e7 bc8a ef9f ec92 e97b e964 e9cb ea20 eb07 eac6 e934 e9cf ea67 eb4d ec90 ecd1 ec1c eab5 e9f8 ea02 e9c2 e845 e66d e7c4 e957 edce d14b 6f52 5f74 5b36 5a28 5fa0 634b 6531 6542 624e 60f0 5ca0 5b9f 5c9e 5bed 5ba5 5d4f 5ff9 60c5 61f2 6272 6241 6296 6c5f 967e db02 ecd8 e9e1 e8ca e93d ea57 eb18 eaad e9f6 e964 e835 e87d e95b e95a eac1
3618 39fe 4090 460f 4fde 840a c2d8 dff5 e555 a732 60a1 5edd 60e2 64d2 66d2 63c5 5f63 5fa1 60bd 5f5e 5e06 5eef 9257 e298 e544 e25f e216 e278 e240 e2a8 e3c1 e538 e695 e6f9 eba8 e03d 7efd 6417 80a8 bbc9 e7a3 ebcf ea1f e82c e755 e757 e75e e842 eb90 f099 d817 89aa 6e48 6ed1 70a4 7410 7359 7017 6e8d 6eba 7c33 ba14 ecfd ec64 e924 e8da ec62 eb7f a443 65ac 648a 65eb 641e 6453 6403 658b 645e 63da 66aa 75ec 98de b2c9 bf97 bbd8 a5a5 8190 65bb 5f53 6266 671f 6ab0 6bf3 6e3a 6db9 780e c61d f235 ef41 eb5c ea76 e991 ea38 ebd8 eb30 eb02 eb0a ea93 ebca ec84 edbc eca4 eb23 e9db e9df ea98 e8ac e5eb e6f4 e927 eaf1 e2a1 827e 5ce0 5998 5a6e 615a 6500 660a 6609 5fe2 5d44 5d55 5d46 5cb5 5bf9 5b57 5e63 604b 6014 60ad 62e4 60ed 5de8 6021 6c13 9f4a e5a8 eb13 e91a e9e0 ea8c ea2c e9c3 e973 e8d1 e8da e99c ea16 ea83 ea63
363f 3b0f 40dc 490d 86d3 d281 e12d e08f e34a c740 6c17 5fbf 6418 6775 67ce 64a3 6220 634c 660b 65bc 62cc 6d91 bef6 ea45 e71f e57d e530 e43d e32d e48f e579 e6ef e9ec ec89 e77d d5d0 b252 b88d d969 ea77 eaf1 e874 e896 e8ac e867 e712 e6a5 e804 ec18 e94d 9da4 69d2 6c42 726d 7100 715d 7167 6f75 6f8c 6ddf 6ea1 842c d50b ec6b e933 eb84 ed69 c50e 7539 62c9 65f3 67fd 660d 6616 65b1 6603 6787 6c69 9a19 d438 ec24 ef17 ef47 efee edec de78 aa17 6b51 6153 66e7 6a09 6cdf 6dbd 6cd8 80e6 db05 f42e f139 ee02 ecc5 ec1c ede0 ef42 ee7f eeeb ee8f edf6 ed1d ef05 f127 efb9 ed0a ebeb eaf5 eaa1 e942 e6c7 e612 e6b5 e8f9 e6e3 8adb 58eb 57fb 5bee 618a 657b 6635 648c 5e9c 5883 584e 5894 59b3 5aef 5c39 5ca0 5e0c 5e08 5fd6 6416 61f8 5f6a 608f 64fa 7881 c96b ed04 ebe3 eae9 e9d0 e8ef e90d e981 e88e e8d9 e99f eb16 eba9 eafd
33e4 37a3 3f84 6d63 cc01 ddcf db8f dc4b e010 e23e 9cf3 6197 6270 6688 6968 68d4 6624 6348 61ea 6278 6430 9846 e37c eafa e856 e85a e6a7 e5c0 e613 e6d3 e830 eb1d e7e6 c64f 9507 80f4 c294 ebd1 ea48 e822 e73b e7bd ea24 ea82 e77d e6cc e782 e8a8 ed03 d06b 74d6 6654 6a09 6c32 6bc5 6b31 69d4 6a9b 6ac8 6afe 6ca4 6eff ae76 ee7b efb4 eb05 c524 7bf4 663c 67fb 695c 6938 69f8 6a8e 69b6 6787 6c15 a112 e433 f20d ef36 ede8 edfe ee45 eed1 ef61 ea4c b30c 6abd 633f 6687 6ca9 6fec 6f70 a258 eefc f55f f255 f077 f09b ef4e f0c0 f264 f261 f35c f1ee e977 d9e6 d021 d38e e1a0 ed01 ef2b ece4 ea8a e7bf e59c e373 e3fa e79a e505 889a 56c0 5668 5a67 5fee 6484 651c 642f 6072 5b01 57ad 54a3 5457 5609 5b07 5d7e 5df4 5d4d 5f7f 6279 642d 6399 64a2 654b 6e15 a8d2 ece3 ee1b ebfa e9ec e953 ea2a eaa7 e9e2 ea40 eb45 ecb8 ed0f ecd4
3087 34dd 47de a546 dbf9 d971 d80e da9e df47 e738 d973 8de3 6520 6694 69d6 69b0 63c4 5e59 5a46 5fa1 8c64 d78c eb17 e86f e713 e77e e6c5 e84c e8fe e960 ecdc e6cd ac47 75c6 669f 6773 a477 e987 e8cb e606 e687 e8ab e89b e862 e82b e92f ea06 ece4 edae ab0f 6922 6886 6954 6903 679c 65d3 6738 697f 6a1d 6836 6953 6cb9 998d deab d297 a5f7 761f 635d 66d8 6a7f 6ab0 6b81 6a76 67f6 676c 6856 8ad6 de03 eeaa ebb6 e96d e9ed eaab ea33 eb41 ecab f0d0 e9a1 99cd 65cc 67a7 6b9f 6ecd 84c1 d54f f49c f49e f25c f078 f01d f139 f260 f35e f436 ecce c917 9a0a 7e04 76ad 78c8 8810 af18 de9b ef08 eb51 e71c e470 e36b e5da e8f4 dc10 7978 591d 5a67 5d38 625f 64ff 642d 6084 5d91 5995 57c9 5627 55c0 5399 563f 5948 59e1 5a34 5d12 5fdf 624b 6519 675c 660c 69e3 9585 e87c eb8e eada eb68 ea96 eb13 ebdf eb0e ebd3 ec33 ed05 ecdb ec85
2fc7 34b5 5ae4 c704 da5d d883 d8c0 db5e df53 e4bf e990 dc99 a6c9 79bd 6a2c 6528 5fed 5f62 6e3f 9e11 d860 e9af e849 e6c3 e6c7 e73f e7cc e9a5 eb06 ed45 eccb b3da 7231 67f6 6297 60b9 7d42 d4bc eb3c e705 e463 e500 e4ac e594 e72a e813 ea6b ef00 d89c 7f15 65f5 68b0 6b15 6b50 69ee 67af 686a 6755 6682 7005 90a0 b969 caad 965b 77c7 6af6 67ee 685a 6ab7 6b56 6b95 6d46 6c47 6a19 69f3 71dd bfeb efef ed66 eabe ea35 eae5 eb4e ec1d ec1a ed18 efa4 f3c7 ccbc 6d40 646e 690f 8363 ca04 f0d8 f32c f253 efb3 eecf efc9 f219 f47d f522 e6be a9c5 7bea 6f74 6945 67cc 675a 6849 6fb1 951d d969 ed16 e991 e682 e53f e910 ee39 c265 65d9 5b84 5d39 5fc1 6334 66e2 6595 61fc 5dfa 5768 5802 5f05 6772 66d1 636f 5b2f 561c 5857 5c10 5fb4 609f 6764 6be7 67c5 6bd8 9647 e92a eb40 e9ec eb18 eb43 ead5 eba1 eb78 ec5f ed04 ed58 ed40 ed99
2fee 34ed 6f56 d3e3 d9a7 d8df d920 dc4a df04 e356 e6ef eb68 e9bf d765 bc00 a971 a5c6 b29f cf6d e4d9 e81d e636 e4d0 e4e3 e6b6 e6e1 e7b2 e938 ecf0 ef69 d375 7ca7 66ea 6627 6381 600b 65a3 9b11 e1aa ec60 e782 e3bf e2a5 e3d3 e64a e82e ebe1 e115 9a6c 6634 6326 6717 6b83 6d91 6ccb 6bc0 6921 6604 7695 b77c e487 ef36 e99e 91c6 630a 65ca 6839 6759 672f 6869 6af3 6b8f 6b30 6a1a 6ae6 8747 e192 f17b eefd eefe ef34 ee0f ee3d eee3 ee68 efd1 f1b7 f44f e38d 80f1 723a 9d33 d529 f186 f23d f115 f07a ef37 ef49 f055 f2ab f58e ebeb a7f3 732f 70b4 6fb5 6bf3 68ed 671e 6783 676f 6c9b 99dd e482 ee2d eb13 ea2c eecf e4f1 903f 5f5c 5ffe 5d90 608b 62d8 6742 68ba 649a 60c5 699d 946b be6a d2cb d627 cf0a b265 8026 5add 58a4 5d46 5f4c 66c4 6dd0 6bac 6f65 a538 ee8f eef0 eb38 e9d4 eb1a eb4f ec2a ecad ee14 ef72 f0aa f099 f041
3121 397f 792f d734 da3a d922 d8db dbc3 def1 e328 e6a1 e977 ec32 ee4e ec2a ea72 e7df e6a2 e6e7 e695 e4b2 e490 e49a e4cd e577 e576 e68a e86d ec00 ebcd a7e8 6917 66f3 6806 67fa 64d9 61ca 6ab1 9ef3 daa2 eaf5 ea05 e90e ea2f ec3c ebdd d87b 9a13 693b 643b 67bd 692d 6b6d 6b7b 6922 6b3c 6835 726f be62 ecd8 edd8 ed8a edc8 b9eb 694f 655f 6cdc 6c5b 6b9b 6a97 6e22 6f4d 6ee7 6bf0 6f97 afa4 f091 f279 f003 ef0e ef87 ef0c ed87 ee87 f0e7 f346 f049 dfd8 c696 c014 d43d ea1f f19b f072 edb8 edde ee12 ed3f ed9a eefd f253 f38c c4a6 7881 6cd3 712c 705a 6c3d 6a25 69ab 6829 65ff 67ce 750c c0d3 f0b4 efe8 f06b e9c3 aa2c 6743 5fe4 6494 6292 633e 63f9 66d5 67ad 67fc 7f51 c2a6 e842 ec09 eac8 e90c ea9d ea46 dd15 9f99 5cd2 5839 5f03 63f1 6910 6c2a 75c1 c5e7 f30b ef86 eb77 e9b1 ea99 eb91 ed56 ee65 f007 f31a f376 f290 f28c
33c2 3ac1 71b8 d62a dc57 db95 daaa dd0c e08e e3da e55c e673 e785 e7d4 e85a e75b e5e6 e4c4 e3b7 e35a e293 e325 e499 e54b e57d e61c e6f1 e87b eba4 e4ea 8a88 66aa 6886 69d6 6a0b 6835 6436 611a 66a5 85cd b2d3 d0f2 dd8b dd60 cf29 ad65 80a9 63df 5f79 60c6 60fd 60bd 629b 6156 5f73 5fc9 64c6 a1c0 e926 ed4c e9b8 e9fa ec78 e13c 8fa6 6471 6776 6b4e 6b9e 6bb5 6af8 6ab6 6903 68e9 8e4a df4a f1df efdf edb6 ed8b ef2a f0bd f025 f122 f424 e705 b32a 860a 7d3a cb36 f29a ef83 edd6 ecc0 ea3f e9dc ea4d ea53 ebb7 ed88 f1cd e9c1 9588 6dd4 6c13 6db1 6e62 6b40 6a2a 6a62 680b 6479 6582 6c82 9db7 edac f208 e04a a6ba 6b8c 5f1c 5fb6 61bc 60ad 5c8e 5e42 6110 6431 7fb2 cc3f ee47 ebe3 e8fb e764 e628 e6f0 e7f5 eacd e21b 961f 57ad 59d7 5f9d 6479 6b85 94c9 e6dc f266 ef81 ee2a ece1 eb05 ec2c ee14 efdc f318 f3a2 e764 d152 c041
36b3 3bc9 5f9c c8f4 dfac dc9a dc3a dea4 e105 e27c e3b1 e524 e686 e664 e73a e659 e4dd e3c4 e3b5 e3bd e3a6 e35c e4e7 e4af e49c e5dc e72c e883 eb87 df34 7e51 66d2 6a2f 69c5 6901 6744 63e9 604c 5eb7 627d 6c13 799d 8192 7de8 7422 696a 622d 5fef 61b8 634d 62c8 610e 60e5 5f97 5c20 5d06 71ff cfcf ec2d e83a e6e3 e915 eb09 ecad d58d 8ba2 69bd 6975 698d 6b66 683c 6523 696f 8b20 d139 f120 efb2 ed98 ed72 ee45 ef68 f207 f341 f421 e231 9f71 74c0 6be0 6eab afcb f0d4 eeeb ec07 ebae eb0e eae3 e996 e87f ea9f ed42 f1c4 cc95 76ba 6b25 6d70 6bff 6d0c 6c8c 6853 698e 6968 66cd 6a5d 7d8f a5b5 ca4d b232 8787 68a4 624f 64eb 6487 6377 6222 5b98 5c81 62bd 6f1a bd8a f010 ed28 e847 e764 e7a7 e73f e6ac e778 e911 ebd8 d1df 6e25 56c9 5add 609f 7f7c cf2a f274 f1a1 efea efa1 ee2f ecb1 ee72 f019 f1c2 e8a2 bd9f 8fdd 7772 6e45
38a9 3ffa 50fa a5d3 e233 dffe de12 e01d e2c2 e3a8 e512 e62d e696 e58d e538 e4a7 e4bc e3e4 e49d e486 e418 e471 e5a6 e55c e50f e6b3 e79a e781 e9fa e0bb 81b1 64b1 6389 62ea 643e 643d 620d 6178 613e 5fc4 5fcd 6306 637e 62c4 63df 6266 616b 6339 6678 66e5 6687 656e 6582 6315 6093 657c 8c79 e5d0 ec45 e909 e7f3 e974 eb07 ee0a f0f4 e0ed b090 8421 71db 7051 710e 8192 ac62 de01 f055 ef57 ecaa ebc9 eca1 ee0f ef9c f171 f3d4 ea95 a297 7333 6efa 6d2c 6b6a 884f dd0b f3a9 ef4a edf8 ed0d ec52 eac2 ea91 ec91 f006 e499 96c3 6a57 6b61 6e5c 6cad 6bf3 69d8 6784 6600 68e0 7f70 b687 ddd8 e177 903c 6d0d 6870 66ed 693c 6b4b 6ad4 68fd 66c4 60d9 5c02 637b 8b8d e5a5 f1da ea96 e820 e8b7 e8d6 e81c e7ef e971 ea15 ecb9 e9e2 9153 5657 5fbc 825b c92e ef80 f057 eee7 ee45 ee0c ed9d ee21 f1b4 f44c e5fc a33a 7165 673b 6515 6204
39aa 4193 4c90 74e1 ccce e5ec e20b e2ff e367 e468 e5af e53f e503 e49c e4f4 e416 e492 e3fc e436 e358 e2ae e3f4 e587 e504 e4f1 e650 e6a0 e621 e8c7 e5ee 9275 6073 64a3 643c 65ff 671d 6548 649b 6488 6298 60b1 603d 6102 6267 67a0 6ae6 6b01 6a19 6a3a 69b8 684d 6864 69a6 661f 663c 6c5e 9e75 ec5f edfa ea4b e974 e986 ea06 ed96 efb8 f124 ee62 e0d5 d052 cab6 d0e4 e21a ef75 f160 efd5 ed3d eba8 ea1f eabf ebd0 ee33 f0de f310 c5df 79e7 739a 731e 7227 6bc2 6d5a a06c e517 f354 f1b6 efc6 ee37 ee59 efe0 f1c2 e6a9 a558 6b2f 6626 6941 6eca 6f7b 6aeb 67f8 6747 691f 8c43 d4b4 f15a f493 ef73 9e4a 672f 6862 6aec 6c86 6d76 6f70 6db1 6987 6530 5fbc 6ae7 b4ec f13b f00c eb47 ea85 ea47 ea6f e96c e9b6 eb83 ed1e ef4f ebf3 b119 8420 ac14 dbcc eef5 ef3d ed70 eb52 eb5f ec50 ec8a ed9e f211 ed2b a7f1 6d92 64ed 61ab 6121 5f41
3952 4135 4d03 5c63 89d2 d16c e811 e97a e754 e874 e888 e6b9 e433 e3b9 e456 e328 e315 e2ff e2d3 e25e e2fb e3a1 e3e8 e356 e3ec e4f4 e500 e463 e683 e7dc ba03 670c 62ec 6389 6311 6490 6500 64b6 6610 6418 632d 6355 64c9 6605 68b7 6a8d 6bd4 6bee 6a41 6814 6684 670f 66bd 6556 6a38 6edf a1cd edae ee5e ea5d e982 ea93 ebb4 ec67 ec4a ed14 ee42 efbf f0e0 f108 f08e f160 f198 eef0 ec61 ea1b ea16 e8c0 e979 eb01 ecbd efee ed77 9ce3 6ec1 71f9 7424 736a 6c38 6547 6f3d 9da5 d6d8 ede1 f1ad f14a f1ad eec1 d8dc 9f5f 6ce1 6581 6509 65d8 6979 6cdd 6a65 67af 675a 7f1a d2bd f08d eda8 ee6d f068 c927 72b3 6831 686a 68dc 69ea 6c1b 6db5 6b99 653a 6588 86fd dd63 f024 ed8f eb55 ebda ebec ec88 ec51 ed29 ef96 e8d7 cb17 a673 b55e e372 ee32 edb1 eb56 eaa2 ea50 e89a e8bf e978 ea4f ec04 ef9f cb2d 7625 68d9 64c7 5e07 5f06 606a
39c3 42b1 4fb9 590d 6008 82f9 ba52 dd24 e8e4 ecdf eb14 e77d e384 e3c6 e493 e2dd e1c8 e17d e199 e14f e235 e312 e32e e32f e377 e407 e3e8 e43e e5b2 e870 dfce 8da7 6196 6351 6424 65ee 6690 676e 656f 6368 63b5 63b0 6244 65eb 67ce 674b 6845 687a 677e 6506 655d 6491 638a 65c8 6a4c 6d2d 9971 ebac eee1 eb7e ec01 eca5 ec86 ebbf eb07 eb06 eafb ec43 ee06 ef67 ef7b ef6a ef33 eda0 eb93 e909 e8ff e7b4 e7db e9ae eb56 ee9a e397 837e 6a86 6d0a 6ded 6e56 6aae 656b 650e 6ac8 806f a05d b913 c16c ba8f a1ef 7f75 6a24 6423 63f7 62e8 611b 63bc 65b4 6813 672a 6cf0 b3a1 ef19 ed56 e815 e9e2 ee80 ec27 ac4b 701d 67dd 69db 6aa1 680a 68b6 66d3 64f3 7a80 c73b ee2a ed62 e9d8 e922 ea79 ec44 ed7e ef36 f15f e0a3 a320 710d 64b3 9789 ecef f002 e9dd e7c9 e876 e868 e776 e812 e899 ea68 edbb ea5b 9bc9 671d 64fd 61b1 5fee 6103 5f33
3d37 462f 51dc 5984 5d7f 6449 720c 8682 a49e ce9b e8c5 e903 e5e4 e3f5 e33b e18d e0ce e148 e23a e1f5 e279 e29a e27c e358 e335 e326 e2f8 e536 e7da eae0 ecc8 d2f4 8578 66ce 64bd 649d 65f7 667a 6701 6675 65b7 64e4 63a0 6608 652d 64ec 6563 664c 64e7 647f 652a 647e 64e6 6622 6868 6b3b 84bf dc1a f0db ee32 ef79 ef24 ecd8 ec2e ead7 ea3d ea0c eae8 ec5c ed41 edee edf7 ee45 ed29 ec56 ead2 e918 e7db e81d e970 ebed ee8d e024 7dd8 6b17 6ca9 7031 6d04 6918 6762 65e4 657b 670f 6aea 7092 73f5 7028 6df4 68ee 65f1 64e3 63db 64a9 61fb 6213 6219 6334 657d 7eef db4f f0b9 ebdf ea00 e974 ecc3 f243 e9ad b2bc 7bae 6e4d 6b1b 6888 67f0 6bf2 8963 c7a9 ed09 ecdb ea67 e928 e8c3 e9f3 eb1f ed42 f157 e2e6 981c 68d7 6269 6219 7cbc d98c ef63 e9a8 e7ee e899 e8ab e851 e936 e978 ecec f0d5 d039 73a8 623a 60f0 5f0c 5ef4 5c10 5914
4039 4630 5346 5c18 5f4d 61fe 6658 6a01 6d0d 7e59 b6f8 e6ff e7d7 e448 e1e3 e056 e077 e093 e23d e1f4 e1ec e238 e298 e288 e2d0 e3f4 e491 e67a e8ac eab6 ebc3 ec89 d6b5 9e8e 717f 6172 613c 6227 63bf 651e 64a0 647f 6244 635a 64e7 66dd 66c8 6745 6680 66e5 68f7 6514 6584 660b 66b1 6a15 73d4 b663 f0b5 f3a2 f156 f02c ece5 ebc0 ebb3 eb10 ea79 eaae eb99 eccb ee28 ed97 edb3 ec9b eb45 ea30 e991 e927 e8ec e95c ebd4 ee4a e334 82b5 68cc 6b83 7094 6cf8 67c0 67b2 6831 6542 6367 6336 62f5 6584 6738 6a9f 6aa5 6960 6669 65bb 6582 6266 617c 6178 61d6 675c 941d eaed ee66 eaea ea7a e9a1 eae6 ee0e f265 efd0 d763 b1e0 976f 9187 9d55 be44 e24c ef42 edc7 ea48 e88f e915 e8a6 e970 ea81 edd1 ec08 a7e3 69c3 653d 6576 62ad 6902 a915 e90c ed0c ea43 e98f ea6c eb6c eb3d ec84 f043 e241 9292 6292 6392 620d 5e02 5b43 57b6 542f
42da 480a 54e5 5bc9 5cf7 5fed 642c 654c 6400 6621 7738 bafd e736 e541 e088 e04e e0c9 e0d0 e159 e15b e187 e21a e299 e2ab e3d7 e512 e5af e74d e95c e98f e8d2 ea3f ebc6 e69f d18b ae65 7f1e 5fad 5e25 6153 61ca 64e1 6445 639b 669a 69af 68af 6a0b 68e5 696e 6839 6387 6633 6631 66dc 697d 6da3 8814 d04c f493 f405 efd5 ee8a ed0e eca3 ec6c ec28 ec7e ed48 eea8 eed2 edd5 ee27 ebd7 e9dd e92e e980 e9f7 e9f7 e9c2 eaec ed4a eb14 9a1d 669c 6a5e 6f43 6b6d 6672 68d8 6881 666f 64ca 64d6 61a6 6391 675b 69f4 68be 67db 66ba 681b 6674 64f0 6333 61ae 6280 68f8 9d2a ed52 ed0f e9f3 e9a2 ea1c eb16 ec51 eed5 f21a f356 f180 ed02 ebe7 ef56 f2dc f285 ef0f ec8b ea63 e856 e89c e866 e9b1 ec00 eea7 d48d 7776 63a4 6540 6292 5f61 5fef 71bd b4fa e79e eed7 ed74 eddf ef67 f12c efba dbf9 9a45 647a 6024 624f 61e9 5d97 597d 55e1 5213
44e5 4ac7 55a6 5b4a 5d4a 615f 66a3 660d 64e9 664d 681b 8271 d480 e5a2 e1d7 e188 e206 e1e4 e16f e1cc e262 e265 e3bc e419 e523 e57a e61d e72d e7ea e74b e557 e5e8 e70e e80c e9c3 e987 d87b 9bed 62b0 5e45 6113 6311 647e 6457 67c6 6cb8 6de9 7013 6d16 6bf9 6b18 685c 6961 68d0 68d6 6886 69cf 70cb 8cdd c875 ec84 f256 f28a f05f ef0e eedf ee86 ee0d ee5b f035 f006 ef3b eeb7 ec0e eb61 eaaa ea30 eb77 ec1f ec14 ed28 ee85 f068 c672 7110 6819 6ea8 6db5 674f 6918 690a 66b0 6697 683a 638f 6477 6801 694f 674b 6720 668f 67e4 6721 6840 6672 6402 62d7 6846 9a89 ebae eca5 e9f7 e950 e8c5 e917 ea1f eb11 ed08 eefe f0f9 f1e3 f28a f28e f189 f092 eeb0 ecc0 eb52 e998 e950 e8e9 e87e ebe7 ee47 b70d 68a2 63ef 65fe 6472 5faf 5bb6 5c35 6f9e 9cb0 cbf6 e22c e840 e77d db68 b90c 852c 6652 6105 5e03 5f4a 5e83 5d67 5a8b 5507 524c
4601 4d58 567f 5b9d 5e24 62db 68b6 66f8 67b3 67ba 644e 684e b0d5 e7ec e69e e40e e3ea e409 e31b e2b8 e343 e4b7 e65a e736 e7c7 e658 e71b e7db e762 e63d e504 e429 e609 e6a6 e6c6 e897 ea82 e197 9adf 5ecd 5f6f 64b3 67a5 680c 69b9 6eff 71e3 706d 6dd4 6b7f 6b33 69be 68cb 6a7b 6d7e 6a7e 69e7 6ba8 70ae 7fe9 a056 c50a e472 f38d f3a0 f1cc f0ba efda eec4 f046 f166 f161 eff1 edd4 ed29 ec8f ed1a ede4 ed7c ecc3 edcf eeaf f00c e992 a3c8 6b09 681f 69a6 6617 6641 65e4 64cc 66a9 6b07 66c0 6620 68c9 6818 6673 6667 66db 66c1 6567 65bb 6666 6482 63a8 6789 8b71 e53f ef01 eb76 e970 e91c e99a e9f0 e997 ea37 ecef eebc efcb f0c8 f07c ef1a ef09 ee99 ed0d ecb8 eb6b ea69 e9be e950 eca9 eda5 a828 67a8 65ec 6739 65c6 6299 5d0b 588e 5da0 6648 7526 8559 8cf8 8b36 7e7c 6d93 6468 62eb 639e 6178 613f 5e42 5f09 5a5e 599a 5b31
4184 4bc0 566f 59a4 5b35 639b 67d0 6587 67b4 688a 6510 637f 9599 e610 e8ea e639 e5b4 e50f e40e e482 e5b9 e711 e99b eb3c eae3 e91f e9b5 e97d e891 e748 e6cb e55e e603 e781 e7ad e878 e965 ec5f d875 7ad7 5f99 61f0 64cd 6764 675f 6a07 6ad2 6a0f 68be 693e 68a7 68d4 6766 6759 6ad3 6c1b 6da1 6f11 7071 7168 7295 7b91 93f3 c640 ef51 f496 f288 f19c f045 f0c0 f1ef f13b f0d4 f00e ef79 ef72 efe8 eed0 eebb ef7b ef13 ef1f effe f202 e329 a1eb 6eda 64a4 630d 62d1 6130 616d 624d 665b 6381 658b 6973 6904 66e1 6412 64c3 6592 6310 6113 61f0 608b 6002 625e 74bd cc2d f143 ec77 e926 e87a e996 e90c e8bc ea07 eb8d ec38 ecf4 ee9b efe0 edc4 ecbe ebf5 eba9 ebfb eba2 eba0 ea82 e9be ed0b ed4f a63a 6381 63ee 63eb 618a 6032 5dc9 5940 5a11 5f27 63bd 676a 6699 645b 66b9 65a1 6359 6443 63b4 5ec4 5fae 5deb 5cd8 586f 59d2 6f33
429b 4b15 5469 5722 5b0b 62c7 64d6 6494 6766 699c 6688 64c8 8c40 e467 ea1e e816 e80f e68d e5bb e61c e82e e966 ebc0 ecf1 ec7d eb42 ec3a eb1d e9a3 e93b e90c e8c6 e855 e996 e7e1 e895 ea9b ec81 ec2f a974 63b3 5f5d 61ce 653b 6449 6614 67da 6757 6748 6785 6692 65ad 65bc 65f1 6965 6cb0 6ecf 6ec7 6f0d 6f6f 6ede 6e54 726c 81db bdfa f0b3 f32c f11f ef38 ef1b ef20 ede9 edb9 ee55 edf8 ee7d ee94 ed18 ede7 ef69 ef82 ef4d efb9 efd0 f115 e8d1 c478 976d 7396 61af 5fbf 5f34 610b 60be 5c1a 6092 6741 6810 66ad 6546 64f2 6368 6292 61b5 5fd6 5ef5 5f0c 5f57 6562 989b e47d ef30 ead1 ea3a ea51 e9e9 e925 e9de eaab ea9a ead7 ec45 ed43 ed38 ec17 ea98 e968 e9d0 e9a4 eacf e9ff e9bc ebfa ec70 b474 60d3 5cc3 5e97 5d45 5cc6 5dcd 5bfa 5c88 5d59 6196 63d9 61f9 5dcf 61dd 65d3 6458 63a2 61f3 5d6d 5dfe 5e01 5ad0 56be 5b4b 8a44
9c6e 8a0f 6e16 58ba 5822 6188 6439 6530 66c0 6803 65bb 6425 903c e552 e98a e763 e6ec e600 e5d8 e6ab e922 ea90 eb2e ec59 ece9 ec8c eceb ed40 ebbf ea04 e9f7 eaf2 ea55 e961 e795 e86c eaea ebea ee80 c60d 6c5a 66a6 64a1 660d 6632 6624 6825 66e2 6678 679c 65ea 6558 6490 664f 6970 6d17 6e34 6d7d 6e6f 6fcf 6e92 6cd8 700e 72e5 8660 d2df f24e f114 ed80 ece4 ec83 ebcf eba9 eba1 ebf1 eca8 ec76 eca0 edcf eed2 efcd ef68 ee36 ee0a ee7d ef99 ef6c e9f8 d37a 9b87 652a 5c21 5fb7 5ea9 5833 5c1c 624c 64a2 65d1 6748 6597 62c7 60bb 6195 61fa 61c7 6239 5fe2 5fea 7056 abcf e574 f132 efd7 ed3a eb86 ea8d e9d5 e91a e953 e953 e9fe eaac eaf3 ea12 e9d2 e8bb e858 e788 e854 e8e5 e96b eb05 ec66 d13b 6d41 592f 5ba6 5cec 5b58 59f5 59e5 5af9 5ce0 5e3c 6017 5dbd 5c1b 5e63 62cb 60c5 5dac 602f 5f00 5c2d 5d37 597a 53e9 5a9d 954f
dbaa dca1 cf67 9e53 652b 5d4b 60d2 623c 64bd 6637 63ff 631e a487 e6fb e6b3 e587 e586 e549 e555 e60f e816 e9a5 ea17 ec77 ee47 ee81 eea7 f05c f016 ef8f ee4e ecc3 eacf e8c1 e889 e889 e903 ea5d edd0 cdef 6efb 670a 6518 6586 64b2 649f 675e 6681 634f 6263 60ec 61bf 63f6 6778 6acb 6aca 6b6e 6c38 6d42 6d8f 6d4f 6cc3 6d25 6d7b 7397 a81a ede4 f145 ed2f ec05 eb97 ea6f e9ca e9db eaf7 ec3b ed35 edc5 ee57 ee8c ef7e ee3a ebde ec88 ec93 ec8d ed43 ecf1 ee4c e5c4 a6bf 5fd7 5a8d 5cbf 5887 591a 5cce 5f28 6211 64d1 63fe 620b 5d5e 5cc3 5e31 6006 6242 5ee5 5ba0 616d 7253 9bd1 cb55 e590 efb3 ef5c ec85 eb2b e99c e7e6 e794 e7dc e902 e954 e947 e98a e911 e75b e618 e6c9 e809 e854 e8de eb42 e7a7 9ba8 584f 56f0 5979 5710 53a5 53f9 562b 5a92 5b1d 5be5 5aa8 5aa1 5a53 5a4e 5aeb 58f1 5d6a 5d8b 57fa 5978 5412 4e4c 5629 8b2c
d8eb dbe1 e0f6 e040 b19f 6713 5b89 5c5e 615d 63cd 6018 6e8e c81a e834 e5dd e492 e3d0 e312 e331 e478 e6eb e9d4 eb2d ebaa e30c d361 ca88 cd7d da16 e9ec f07f ede0 ebca e91c e88b e777 e7c9 e957 ecba cab4 6c67 6480 6389 6481 63cb 6217 6311 63a3 61ff 62b0 6114 60a0 61ed 6499 652b 6360 6224 61a1 6456 67a4 69a1 6b5e 6aa6 6b07 6f25 8c5a e37f efad ed05 ebcc ea91 ea2c ea23 eb8e ec1b ecb2 ed60 ee5f eea2 edc7 edc6 ed15 eb94 ebed eb22 ead6 eae6 ea04 eb92 ed5e e2f9 8ee5 5b11 5c09 5af9 594c 5e54 6286 6593 6707 656d 6482 6386 6132 5fb9 6327 6431 618d 5eba 60f8 6492 6ac1 792e 91bd bbc1 e6cb f200 ee72 eb3f ea17 ea15 e8b1 e992 e99b ea12 e9ee e988 e812 e66c e610 e756 e746 e802 e9be ebdd d7fa 858a 598a 547b 5364 5049 51bd 5509 58e6 5921 59f3 5916 5a87 5b96 5aa3 5b46 5b6f 5cda 5baf 56dd 578a 5094 4c32 4f96 6d38
d64d d878 db3a df5e e047 a1e5 5dd3 5e36 61d6 61bf 6611 9e69 e3e0 e7e4 e593 e4d2 e4a9 e50a e5bf e6ab e878 ecee e289 b699 8d06 7993 762f 791a 8275 9deb ccbd ec3f ee37 ea7f e84b e70d e766 e967 ed60 b8d5 693e 6583 68eb 679b 65eb 6349 6312 642d 6644 66bb 64da 6423 6320 654a 6512 62d6 61e8 5f60 630e 69b9 6bdd 6c6b 6b1e 6b70 6e46 826b dcb0 f0d1 ee5b ecd5 eb87 eaca ebaa ede2 edc6 ed07 ee20 eeef ef9f ee7c ecdb ebe4 eb96 eb8e eb0a ea92 eb2d ea6f eb86 ecce ee45 c4ad 690f 5edc 5ce2 596a 5f21 660d 69c5 6a70 693b 68dc 6abe 69c5 6660 6850 68fb 66ac 683d 6ba9 6b24 681a 67d6 6bfb 7863 a3af e48a f2f9 eff8 ef8c ef21 ed1e ec79 eb11 eb14 ea4c e980 e8ce e7f7 e762 e843 e8bc e806 e899 eaa1 ebd8 da27 a26c 6d31 56d1 5086 50cb 53a0 555c 5608 5760 5a3b 5c09 5e02 5e87 5ffd 6091 5d01 5b0f 5874 56e9 51c9 4bdf 4b40 569d
d70a d7fb da61 ddc1 e359 d429 75f9 5e73 5ecd 658d 93b9 d98b e823 e616 e544 e520 e5ba e779 e83b e916 ec4b df05 9c90 7227 6b97 6b39 6d27 6f0e 71e2 70a2 81e0 bd01 eb78 ed43 e7f2 e70a e833 ec93 e795 9402 6803 68e5 6c8d 6b96 682a 6720 6702 66f4 6756 66da 6ef6 8186 9124 95cb 8d05 7abc 684b 631c 6609 6a1e 6f64 7028 6e84 6f2b 70b5 8329 de58 f23d f056 ee9e ecaa ece8 ede0 ee40 ee8e ee6b efb0 f10e f215 f17c eff4 ef1a ee6e ed2f ecd5 edea edab ec6f ed31 ed88 f028 e1e5 7e9c 63fc 5e42 5bf0 6086 66ac 69b4 68d5 6862 6819 692b 6c6b 69a6 677f 66bf 66e2 68a4 6a98 6bd0 6b0b 6c9f 6d53 6f84 7901 ae85 ef7b f527 f30d f133 f04d ee91 ed1d eccf ecf6 ed6d ec11 eb3c eb3a eae5 eb56 e9c4 e9f2 eb07 ec8d ed63 e8c8 d656 b126 754c 5159 5042 537b 55c4 56ce 5a62 5ca3 5e5f 6097 61d5 6277 5d33 5a4f 58c0 5834 53e8 4c29 48ef 4fd6
da4f dbb6 decb e089 e537 e7f2 9993 6252 7266 a5a0 db86 e8e6 e6d2 e663 e5df e5a1 e63c e89b ea99 ecb4 e54b 9d0a 6c5d 69ec 67b4 685a 69c3 6b4e 6b99 6920 6e44 7e44 c77f ec44 e7ea e87b ec88 ef46 c319 71c6 6917 6c24 6f14 6d2f 6aa2 6974 67f6 668d 673b 8a45 c0a8 e0a7 e9d6 ea01 e6c7 d9de b161 78f3 63f3 67a3 6bee 6ee1 6e67 6e9a 6f2e 8c11 e595 f104 eed8 ed1f ec44 ed3f edc1 edf7 f0f8 f27b f35d f38c f42b f420 f396 f35f f1af f086 ef5c ee32 ecee ecf6 ee0a eea0 f1e2 eb50 8b8b 66f8 5f45 5cff 626f 65cf 666c 65db 6474 6365 6402 690f 6603 6313 63e0 667b 67ff 677b 6a6e 6a9b 6d22 6f3a 6d92 6f5a 8560 d664 f6ae f4f6 f208 f043 ee34 eeaf ee28 eef7 ef89 ef39 ef92 ef2e edf6 ed6c ebe7 ead1 eadb ec88 ebbb eb54 ea8c e927 d4b6 8b81 54b8 5495 5456 57e0 5b7f 5bdf 5d8e 6270 64a7 63f4 6137 5e17 5a9a 596c 5524 4dde 48c4 49c2
e024 e126 e333 e5f7 e1c4 d2ca b943 b903 d2d1 e361 e723 e665 e54f e52d e4f8 e53b e5fa e808 eb21 ed57 bd5c 7030 675e 6688 643a 649c 66b6 6906 696e 6a41 6aba 6b39 91af e2cc eb24 ec32 ee91 d005 7fc8 65c2 6a89 6f30 6c99 6b09 69ae 6930 6766 6842 9897 dc57 ebb0 ea59 ea19 e90e ea1e ed91 ecfe ced5 8256 674a 697e 6fa5 7073 6d27 7031 ac56 ee64 f014 ed25 eb3e eb47 ec1b ed72 ef68 f2ce f576 f4e1 eff1 e840 e5a0 e880 efce f39e f36b f1ae ee42 ec0c ebb6 ec41 ed37 f1f6 e9ab 8894 6872 628d 6355 66ed 694b 686b 6647 65da 6472 65bf 675c 6476 624f 62aa 67c7 6b1c 6b4d 6c63 6d8e 6d07 7163 6f39 6cd0 76c5 b57c f47a f5a5 f25f f0be ef04 ef38 ee95 f017 f135 f0ff f194 f18e f0fc ef83 edb3 ebd1 eb74 ec4a ecb9 ea97 e942 e94a ec08 d818 7c77 568a 53ff 5835 5ce6 5d90 5f51 64e8 680a 6620 63eb 5f94 5bf2 5ad8 58d0 5242 4da4 4a71
e400 e66d e3f8 c316 90c2 7668 a4b6 e8b0 e83b e452 e3df e3e8 e39e e4af e52a e49f e568 e6d0 ebca e603 9093 67ca 6707 6914 665d 66b6 66e5 6834 6a3b 6b9e 6962 67d3 73a0 cd4f ee65 e737 c3a7 81ed 64f4 6719 6b91 6eb4 6aef 679c 66b6 67b6 6666 8e7a dddc ec9e e90b e594 e4ab e4b3 e678 ea3d ee83 ef49 cadf 76c7 6bc3 711f 6f91 6cb2 86b8 d94f f2e8 f08f ee0a ec04 ebfc ece1 ef46 f1f5 f38d ee54 ce9a a7b1 9114 8c9f 930a a8f1 cd7c ed62 f465 f172 ef24 ecd0 ebc1 eccb f23f ded2 7dcc 684b 6253 6600 685e 6aa0 68f2 68b1 6842 65b4 6586 6629 65c7 6271 62a3 67cc 694d 6ac0 6d91 6f18 6f42 70b3 713a 6ffc 7342 a1b5 f0d1 f4a4 f10c ef02 ede7 ee04 ee57 f00c f1b2 f1fc f25d f284 f21b f0a6 eead ec27 ec21 eb32 eb8f ea91 e862 e6c2 e9f1 ec2b b7c4 5c00 53c6 579d 5b4f 5b7d 5fb7 6750 6719 638b 6126 5fe3 5d6f 5ca6 59b5 5434 4efc 4c5a
e749 e2f7 a9e4 7168 627e 61e5 873d df63 e95c e43b e331 e408 e347 e306 e442 e42c e526 e790 ed72 cc66 738c 6558 67ca 6b35 67c8 66f2 654d 645c 6506 641c 6519 7016 8a7c b92c b8e9 980b 75b3 67ca 66e8 6748 6cd0 6f89 6c69 6a99 67a0 65bb 72a4 c7a8 efce ec3e e90e e73e e644 e773 e8f0 ea31 ed38 f064 ecd6 a023 68f0 6ad7 6b68 7f3f c669 f0c7 f322 f0c3 ef1d eed6 eec2 ef6d f276 f4c1 e7f7 ab9f 7ea9 73cc 73c8 75da 76d7 7b37 8458 ac1e e662 f41a f158 ee80 ecf9 ef44 f1e8 bfc2 6f92 673d 6609 6937 69c3 67af 67e9 64e2 6487 63e0 64db 6b8f 74d8 75af 6fad 6503 640f 6756 6b34 6d6c 6dfa 6fdb 70dc 7209 72b4 9e45 efe5 f46f f097 ee65 ed89 ecd6 ecc4 eeb4 f196 f27b f2c2 f27e f296 f156 f034 eee0 ed60 eb86 ea83 e9eb e8a1 e749 e8c7 ecf9 d8c5 6d62 53ec 54bf 59a6 5d1c 61bf 67dc 6734 603e 5dc1 5e0b 5cfb 5a20 5779 541e 5084 4ca6
ea60 b2c6 6be5 6249 61ae 5ec3 6d19 b95c e954 e6f1 e3de e4a5 e505 e4e8 e5b1 e682 e700 eb2c e31c 973d 6638 6524 6867 6a93 6730 6315 6241 5ff4 60c0 6d3b 9a43 cd4e e48a c186 7415 6cb3 6cb7 6b70 6acc 6b60 6f20 70e6 6e51 6dc8 6a5d 69a9 92c4 e835 f076 ed29 ec28 eadc ebb1 ed80 ed88 ed05 eef3 f130 f373 c6e1 6c9b 6df4 903a cb6e eead f244 f275 f158 f0d1 f0a5 f17e f371 f606 ecd0 a99f 743d 6f09 7026 7343 76f1 7589 76bc 763d 78a3 ad8d ee60 f359 ef79 eeb9 f29f e363 8dca 6782 691a 690a 6b2a 6bb2 6a0e 6a8c 67c1 67e0 7695 a2ba c99b da21 dc50 d513 b7fc 8788 6715 65f4 68df 6a3b 6eca 71cb 70db 7547 aa6b f0b4 f377 eff2 eef5 ee05 ec98 ebfc edc2 f19d f388 f4cb f3ed f39a f37f f2a0 f0b2 eee9 ed9f ebab e9f9 e8b1 e8d1 e9ad ec0b e40b 7c8c 54c6 55c4 5acd 5fe9 62fe 6597 689f 6236 5d0e 5b65 5acd 589c 5605 5470 51df 4f75
d451 7af3 649f 652d 6488 5ed9 601c 7f39 ca62 ea47 ea57 e7de e73e e846 e8ce eb0c edb6 e5ee a928 6dfc 65fa 6678 687a 69f6 652c 6041 60a4 63ba 755b b94d e5cb ed2e ee3c d909 7d5b 6aed 6d0e 6ce3 6db5 6ffa 707e 6fe2 6f95 6ed6 6e33 757a bc09 f12c efc8 ecc2 ebdd eb68 ecfa ef23 efa2 f101 f39c f34f ea49 ce4f aa0d c432 e5d0 f1c4 f279 f1a6 f200 f176 f1e8 f1a3 f330 f612 f661 c652 7b56 72d9 7025 7107 749e 74c9 76e8 79bc 7856 7024 7eb9 cef6 f442 f233 f371 ea15 a905 6e51 6a2a 6d2c 6c86 6ddf 6d40 6a69 6adf 6bac 89c8 cb51 ed09 f0b7 eef8 ee4d eed3 edef e0cb a7b8 6b21 66c1 69ce 6f0a 70e8 701f 7bc1 c8da f427 f27e eff6 ef16 ee6e ecd3 ebb8 ed60 f151 f49b f618 f3a9 f10d f1e7 f455 f477 f2f7 f061 ebfb e95c e934 e954 eb18 ecc1 e57b 807d 5728 58f9 5e0e 6287 646c 648a 6520 5f99 5b2d 5987 58a1 593f 577d 54fc 5171 5020
a83a 68ea 6690 6714 64a9 5f30 5def 65c6 833f be74 e358 ec00 eb67 ebe8 ec30 ea64 d791 9ee0 6c27 65c4 6700 6732 67d0 6786 62d7 5bfa 5e3a 6aa3 b0fb e8cc e971 e7ba e8d9 e990 a875 6ae6 6909 6dae 730c 739c 71f3 6fed 6b84 6a5a 6d57 9011 e0e2 ef82 ecc0 eb2c ebd7 ed48 ee3f f0c7 f2fb f590 eb47 c28a 982a 9654 e080 f471 f2ea f0a8 f0bd f0df f03a f0a6 f22d f240 f343 f711 ed72 9837 735d 729b 70dc 73b9 7718 75fb 7511 7647 75cf 71bc 720d a90e f0c6 f3a4 e2f6 a887 71c2 6a71 6d29 6e02 6e95 6fd8 6d92 6c1a 6d0c 8687 d44b f1e3 ef3c ecd8 eb25 ea75 eb34 ecea eeb1 e7c8 a4a3 67fc 6842 6e6d 6e38 7168 97f5 e886 f424 f060 ef08 eed4 eed2 eece edbe ef7a f2ae ead7 cd40 b12a a4d3 a8d0 bd6b dc7d f23a f431 ee19 ea69 e9c5 e91a ea9b ee1c dced 7498 5968 5b86 619d 6384 63c8 659a 631f 5c97 581a 5a38 5a95 573c 5537 53b7 504d 4efb
8497 648c 6496 6337 61fc 5deb 5cee 61b6 6755 75d2 92f2 b2b5 c38e c688 bbb5 a147 7f41 6770 6191 6619 67f8 65a1 6527 6426 5ee6 5993 60d6 8a69 df3e e8cb e31d e272 e3d4 e968 dae8 8ecc 6bb9 6da9 6fe1 7196 70cb 6c15 68e5 6b85 8435 ce6b f0c5 eeda ebbb eb81 ed5d ef66 f110 f348 f557 e620 a698 7a1f 7128 7d3f d226 f514 f1b0 ef3b eeb3 eeed eeb8 ef71 f1af f272 f33d f6ab d3a4 7cd0 71ab 7126 7130 7403 7597 7518 7537 7385 7275 70d7 7af5 a262 d1d6 ba52 8d3d 7018 69c4 6c03 704d 6f98 7053 727b 700f 6d71 775d c09e f091 ef99 ebcc ec13 eb8d eb83 eccc ed28 ee63 f29d dc71 79eb 622a 6773 6b88 8629 d1e0 f4b9 f2aa f03f eed8 ee99 efbc f107 f1a0 f25b d712 9bda 770e 7132 737b 7571 7721 89d0 bba2 ec58 f11a ec79 e999 e94e ebdb f018 c10f 64d3 5b40 5c86 61dc 6626 63d3 62d6 6090 5a06 5855 5d08 5d96 5d89 5c3e 5463 4f31 4c34
782f 6200 61ac 615d 5e6c 59ab 5aba 639e 66ab 6867 6997 6e81 72b3 7211 6e6c 691e 6496 6125 61e7 64eb 64c4 64ee 6489 61bb 5cd8 5d48 65a1 b152 e911 e48c e030 dfec e2d2 e841 ec97 db3d a285 7752 6ead 6f96 6f6a 6cfb 7506 9875 d210 f11a f224 efa9 ee1d ee38 ef71 f20b f37a f610 eb48 a616 767f 73e7 7423 739d a9a1 ee75 f336 efe0 ef10 ef96 f06a f1a0 f2d6 f2ff f5f5 edc8 a249 7030 6efb 6f8f 7014 72fb 71aa 7289 7300 6fdd 7e29 a8fc d2d2 db7c 9342 7301 6cd7 6ae1 6dbc 71f5 755d 73cf 737c 7540 72f5 720f 93c9 e720 f35d eed7 eb33 eb75 ebe4 ec88 ed87 ee72 eefc f1c4 ef02 9ea1 630e 6c87 8b89 cd88 f30f f3d9 f17b f01b ee8a eeca f185 f385 f414 d5d7 88fd 6cd2 6a00 6ce9 6e39 6f79 6e2c 6ec5 7b49 b64e ed75 eddf ea4a eab3 ee59 e576 8e2f 5fa5 5fab 6131 6496 666e 6413 623b 60bf 5d59 6bc0 9355 b61f c74e c64e b341 88bc 59ff
7d4b 6067 628d 60b0 5d26 5927 5c73 6274 665c 6964 6717 6864 689a 676d 65fc 6499 641d 631c 635d 65c8 65ae 6844 661b 6090 5e76 5f42 6c79 c675 e690 e1ae dfc3 e1e1 e3d8 e77e ecbc ef68 eb2f ce04 aaf1 97a5 9634 a8c5 ca6a e9c4 f339 f248 f114 f0e3 f074 f103 f1e3 f3bd f4ae f601 c950 7c58 760f 78a2 74cb 6ff6 81ca cdcf f45f f288 efcf f049 f1ed f29a f391 f5f1 f6e4 c57c 7638 6de8 6f79 6f77 6f7f 7198 6e67 6d2c 6f36 7ed6 c639 f1dc f809 ef86 98ea 6e7c 6e55 701b 72d0 75d4 7421 73ff 7222 72da 71be 739c b2ab f391 f451 eff5 ec67 ecd3 ed2e ecc7 ee9b f0da f275 f499 f4bc bf37 86b4 ad9a de9c f353 f2fa f17b f074 f045 ee88 ee71 f211 f5a9 ebd3 9972 6c20 6b9e 6ba0 6af5 6c05 6c2e 6a5f 686b 6871 7e31 d6f9 f02a ecfb eef2 f0b6 bb86 67ed 5f97 608d 6386 64ee 61b9 6070 5ef7 6013 7b26 c2a6 ea93 eef2 ee3c efae ef42 e4c9 ba99
py393/.~lock.boson_commands.ods# 0 → 100644
View file @ 043d4849
,eyesis,eyesis-SH87R,26.12.2020 00:01,file:///home/eyesis/.config/libreoffice/4;
\ No newline at end of file
py393/cargs_test 0 → 100644
View file @ 043d4849
-d TARGET_MODE=1
-f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh ../includes/x393_simulation_parameters.vh
-l ../includes/x393_cur_params_target_gen.vh
-p PICKLE="../includes/x393_mcntrl.pickle"
-i
py393/generate_flir_boson_cs.py 0 → 100755
View file @ 043d4849
#!/usr/bin/env python3
# encoding: utf-8
'''
# Copyright (C) 2020, Elphel.inc.
# test for import_verilog_parameters.py
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2020 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
CRC16_XMODEM_TABLE =[
0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0]
def create_with_parity (init_data, # numeric data (may be less than full array
num_bits, # number of bits in item, valid: 1,2,4,8,9,16,18,32,36,64,72
# start_bit, # bit number to start filling from
full_bram): # true if ramb36, false - ramb18
d = num_bits
num_bits8 = 1;
while d > 1:
d >>= 1
num_bits8 <<= 1
bsize = (0x4000,0x8000)[full_bram]
bdata = [0 for i in range(bsize)]
sb = 0
for item in init_data:
for bt in range (num_bits8):
bdata[sb+bt] = (item >> bt) & 1;
sb += num_bits8
data = []
for i in range (len(bdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + bdata[256*i+b]
data.append(d)
data_p = []
num_bits_p = num_bits8 >> 3
sb = 0
print ("num_bits=",num_bits)
print ("num_bits8=",num_bits8)
print ("num_bits_p=",num_bits_p)
if num_bits_p:
pbsize = bsize >> 3
pbdata = [0 for i in range(pbsize)]
for item in init_data:
# print ("item = 0x%x, p = 0x%x"%(item,item >> num_bits8))
for bt in range (num_bits_p):
pbdata[sb+bt] = (item >> (bt+num_bits8)) & 1;
# print ("pbdata[%d] = 0x%x"%(sb+bt, pbdata[sb+bt]))
sb += num_bits_p
for i in range (len(pbdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + pbdata[256*i+b]
data_p.append(d)
# print(bdata)
# print(data)
# print(pbdata)
# print(data_p)
return {'data':data,'data_p':data_p}
def print_params(data,out_file_name):
with open(out_file_name,"w") as out_file:
for i, v in enumerate(data['data']):
if v:
print (", .INIT_%02X (256'h%064X)"%(i,v), file=out_file)
for i, v in enumerate(data['data_p']):
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)
def print_params(data):
print("Paste following to memory parameters in Verilog source file:")
for i, v in enumerate(data['data']):
if v:
print (", .INIT_%02X (256'h%064X)"%(i,v))
for i, v in enumerate(data['data_p']):
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v))
rslt = create_with_parity (CRC16_XMODEM_TABLE, # init_data, # numeric data (may be less than full array
16, # num_bits, # number of bits in item, valid: 1,2,4,8,9,16,18,32,36,64,72
False) #full_bram): # true if ramb36, false - ramb18
print_params(rslt)#,"test.vh")
# from FLIR docs:
def crc16(data, crc=0x1d0f): #Note the new initial condition is 0x1d0f instead of 0.
# in C:return(USHORT)((crcin << 8) ^ ccitt_16Table[((crcin >> 8)^(data))&255]);
for byte in data:
crc = ((crc << 8) & 0xff00) ^ CRC16_XMODEM_TABLE[((crc >> 8) & 0xff) ^ byte]
return crc & 0xffff
py393/import_verilog_parameters.py
View file @ 043d4849
......@@ -517,7 +517,7 @@ class ImportVerilogParameters(object):
self.conditions.append(not self.conditions.pop())
continue
elif tokens[0] == "elsif":
self.conditions.pop
self.conditions.pop()
self.conditions.append((tokens[1] in self.defines) and ( not False in self.conditions))
continue
else: # enabled, process all directives
......@@ -528,7 +528,7 @@ class ImportVerilogParameters(object):
self.conditions.append(not (tokens[1] in self.defines))
continue
elif tokens[0] == "elsif":
self.conditions.pop
self.conditions.pop()
self.conditions.append(tokens[1] in self.defines)
continue
elif tokens[0] == "else":
......@@ -748,4 +748,4 @@ class ImportVerilogParameters(object):
return self.parameters
def getDefines(self):
return self.defines
\ No newline at end of file
py393/test.vh 0 → 100644
View file @ 043d4849
, .INIT_00 (256'hF1EFE1CED1ADC18CB16BA14A9129810870E760C650A540843063204210210000)
, .INIT_01 (256'hE3DEF3FFC39CD3BDA35AB37B8318933962D672F7429452B52252327302101231)
, .INIT_02 (256'hD58DC5ACF5CFE5EE95098528B54BA56A548544A474C764E61401042034432462)
, .INIT_03 (256'hC7BCD79DE7FEF7DF87389719A77AB75B46B4569566F676D70630161126723653)
, .INIT_04 (256'hB92BA90A99698948F9AFE98ED9EDC9CC382328021861084078A7688658E548C4)
, .INIT_05 (256'hAB1ABB3B8B589B79EB9EFBBFCBDCDBFD2A123A330A501A716A967AB74AD45AF5)
, .INIT_06 (256'h9D498D68BD0BAD2ADDCDCDECFD8FEDAE1C410C603C032C225CC54CE47C876CA6)
, .INIT_07 (256'h8F789F59AF3ABF1BCFFCDFDDEFBEFF9F0E701E512E323E134EF45ED56EB67E97)
, .INIT_08 (256'h606770464025500420E330C200A11080E16FF14EC12DD10CA1EBB1CA81A99188)
, .INIT_09 (256'h725662775214423532D222F3129002B1F35EE37FD31CC33DB3DAA3FB939883B9)
, .INIT_0A (256'h4405542464477466048114A024C334E2C50DD52CE54FF56E858995A8A5CBB5EA)
, .INIT_0B (256'h563446157676665716B0069136F226D3D73CC71DF77EE75F97B88799B7FAA7DB)
, .INIT_0C (256'h28A3388208E118C06827780648655844A9ABB98A89E999C8E92FF90EC96DD94C)
, .INIT_0D (256'h3A922AB31AD00AF17A166A375A544A75BB9AABBB9BD88BF9FB1EEB3FDB5CCB7D)
, .INIT_0E (256'h0CC11CE02C833CA24C455C646C077C268DC99DE8AD8BBDAACD4DDD6CED0FFD2E)
, .INIT_0F (256'h1EF00ED13EB22E935E744E557E366E179FF88FD9BFBAAF9BDF7CCF5DFF3EEF1F)
py393/test_mcntrl.py
View file @ 043d4849
......@@ -580,7 +580,8 @@ USAGE
print(" 'defines' command accepts regular expression as a second parameter to filter the list")
elif (lineList[0] == 'pydev_predefines'):
predefines=""
for k,v in ivp.parsToDict(parameters).items():
# for k,v in ivp.parsToDict(parameters).items():
for k,v in list(sorted(ivp.parsToDict(parameters).items(), key=lambda item:item[0])):
typ=str(type(v))
typ=typ[typ.find("'")+1:typ.rfind("'")]
if "None" in typ:
......@@ -664,4 +665,4 @@ if __name__ == "__main__":
stats.print_stats()
statsfile.close()
sys.exit(0)
sys.exit(main())
\ No newline at end of file
sys.exit(main())
py393/vrlg.py
View file @ 043d4849
This source diff could not be displayed because it is too large. You can view the blob instead.
py393/vrlg_mod.py 0 → 100644
View file @ 043d4849
from __future__ import print_function
from __future__ import division
'''
# Copyright (C) 2015, Elphel.inc.
# Module to keep globals (Verilog parameters) accessible for all modules
# that import (not import from) this one
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
DEFAULTS={}
dqs_dqm_patt=None
def init_vars(d):
global DEFAULTS
if d:
globals().update(d)
for k,v in d.items():
DEFAULTS[k]=v
def set_name_field(vname,
fieldIndex,
value):
"""
Set specified byte in the parameter
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
<value> value to set the specified byte to
"""
v=globals()[vname]
mask = 0xff << (8*fieldIndex)
val = value << (8*fieldIndex)
v = ((v ^ val) & mask) ^ v
globals()[vname]=v
def get_name_field(vname,
fieldIndex):
"""
Get specified byte in the parameter
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
Return specified byte
"""
# print ("value for %s is %s"%(vname,str(globals()[vname])))
# print ("dflt for %s is %s"%(vname,str(DEFAULTS[vname])))
# print ("value[%d] for %s is 0x%x"%(fieldIndex,vname,globals()[vname]))
# print ("dflt[%d] for %s is 0x%x"%(fieldIndex,vname,DEFAULTS[vname]))
return ( globals()[vname] >> (8*fieldIndex)) & 0xff
def get_default_field(vname,
fieldIndex):
"""
Get specified byte in the parameter default value (read at program
start from Verilog parameters)
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
Return specified byte
"""
global DEFAULTS
# print ("value for %s is %s"%(vname,str(globals()[vname])))
# print ("dflt for %s is %s"%(vname,str(DEFAULTS[vname])))
# print ("value[%d] for %s is 0x%x"%(fieldIndex,vname,globals()[vname]))
# print ("dflt[%d] for %s is 0x%x"%(fieldIndex,vname,DEFAULTS[vname]))
return (DEFAULTS[vname] >> (8*fieldIndex)) & 0xff
def get_default(vname):
"""
Get parameter default value (read at program start from Verilog parameters)
<vname> Verilog parameter name string (as listen in 'parameters')
Return specified parameter default
"""
global DEFAULTS
return DEFAULTS[vname]
def save_default(vname=None):
"""
Save parameter default value (replace read at program start from Verilog
parameters) using current parameter value
<vname> Verilog parameter name string (as listen in 'parameters')
"""
global DEFAULTS
if vname and vname in DEFAULTS:
DEFAULTS[vname] = globals()[vname]
else:
for vname in DEFAULTS:
DEFAULTS[vname] = globals()[vname]
def restore_default(vname=None):
"""
Restore parameter value from default
<vname> Verilog parameter name string (as listen in 'parameters')
"""
global DEFAULTS
if vname:
globals()[vname] = DEFAULTS[vname]
else:
for vname in DEFAULTS:
globals()[vname] = DEFAULTS[vname]
#### PyDev predefines
PICKLE = str
PICKLE__TYPE = str
PICKLE__RAW = str
VERBOSE = int
VERBOSE__TYPE = str
VERBOSE__RAW = str
MCONTR_WR_MASK = int
MCONTR_WR_MASK__TYPE = str
MCONTR_WR_MASK__RAW = str
MCONTR_RD_MASK = int
MCONTR_RD_MASK__TYPE = str
MCONTR_RD_MASK__RAW = str
CONTROL_ADDR = int
CONTROL_ADDR__TYPE = str
CONTROL_ADDR__RAW = str
CONTROL_ADDR_MASK = int
CONTROL_ADDR_MASK__TYPE = str
CONTROL_ADDR_MASK__RAW = str
CONTROL_RBACK_ADDR = int
CONTROL_RBACK_ADDR__TYPE = str
CONTROL_RBACK_ADDR__RAW = str
CONTROL_RBACK_ADDR_MASK = int
CONTROL_RBACK_ADDR_MASK__TYPE = str
CONTROL_RBACK_ADDR_MASK__RAW = str
CONTROL_RBACK_DEPTH = int
CONTROL_RBACK_DEPTH__TYPE = str
CONTROL_RBACK_DEPTH__RAW = str
STATUS_ADDR = int
STATUS_ADDR__TYPE = str
STATUS_ADDR__RAW = str
STATUS_ADDR_MASK = int
STATUS_ADDR_MASK__TYPE = str
STATUS_ADDR_MASK__RAW = str
MCONTR_CMD_WR_ADDR = int
MCONTR_CMD_WR_ADDR__TYPE = str
MCONTR_CMD_WR_ADDR__RAW = str
MCONTR_BUF0_RD_ADDR = int
MCONTR_BUF0_RD_ADDR__TYPE = str
MCONTR_BUF0_RD_ADDR__RAW = str
MCONTR_BUF0_WR_ADDR = int
MCONTR_BUF0_WR_ADDR__TYPE = str
MCONTR_BUF0_WR_ADDR__RAW = str
MCONTR_BUF2_RD_ADDR = int
MCONTR_BUF2_RD_ADDR__TYPE = str
MCONTR_BUF2_RD_ADDR__RAW = str
MCONTR_BUF2_WR_ADDR = int
MCONTR_BUF2_WR_ADDR__TYPE = str
MCONTR_BUF2_WR_ADDR__RAW = str
MCONTR_BUF3_RD_ADDR = int
MCONTR_BUF3_RD_ADDR__TYPE = str
MCONTR_BUF3_RD_ADDR__RAW = str
MCONTR_BUF3_WR_ADDR = int
MCONTR_BUF3_WR_ADDR__TYPE = str
MCONTR_BUF3_WR_ADDR__RAW = str
MCONTR_BUF4_RD_ADDR = int
MCONTR_BUF4_RD_ADDR__TYPE = str
MCONTR_BUF4_RD_ADDR__RAW = str
MCONTR_BUF4_WR_ADDR = int
MCONTR_BUF4_WR_ADDR__TYPE = str
MCONTR_BUF4_WR_ADDR__RAW = str
AXI_WR_ADDR_BITS = int
AXI_WR_ADDR_BITS__TYPE = str
AXI_WR_ADDR_BITS__RAW = str
AXI_RD_ADDR_BITS = int
AXI_RD_ADDR_BITS__TYPE = str
AXI_RD_ADDR_BITS__RAW = str
STATUS_DEPTH = int
STATUS_DEPTH__TYPE = str
STATUS_DEPTH__RAW = str
DLY_LD = int
DLY_LD__TYPE = str
DLY_LD__RAW = str
DLY_LD_MASK = int
DLY_LD_MASK__TYPE = str
DLY_LD_MASK__RAW = str
MCONTR_PHY_0BIT_ADDR = int
MCONTR_PHY_0BIT_ADDR__TYPE = str
MCONTR_PHY_0BIT_ADDR__RAW = str
MCONTR_PHY_0BIT_ADDR_MASK = int
MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
MCONTR_PHY_0BIT_ADDR_MASK__RAW = str
MCONTR_PHY_0BIT_DLY_SET = int
MCONTR_PHY_0BIT_DLY_SET__TYPE = str
MCONTR_PHY_0BIT_DLY_SET__RAW = str
MCONTR_PHY_0BIT_CMDA_EN = int
MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
MCONTR_PHY_0BIT_CMDA_EN__RAW = str
MCONTR_PHY_0BIT_SDRST_ACT = int
MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
MCONTR_PHY_0BIT_SDRST_ACT__RAW = str
MCONTR_PHY_0BIT_CKE_EN = int
MCONTR_PHY_0BIT_CKE_EN__TYPE = str
MCONTR_PHY_0BIT_CKE_EN__RAW = str
MCONTR_PHY_0BIT_DCI_RST = int
MCONTR_PHY_0BIT_DCI_RST__TYPE = str
MCONTR_PHY_0BIT_DCI_RST__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
MCONTR_PHY_0BIT_DLY_RST__TYPE = str
MCONTR_PHY_0BIT_DLY_RST__RAW = str
MCONTR_TOP_0BIT_ADDR = int
MCONTR_TOP_0BIT_ADDR__TYPE = str
MCONTR_TOP_0BIT_ADDR__RAW = str
MCONTR_TOP_0BIT_ADDR_MASK = int
MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
MCONTR_TOP_0BIT_MCONTR_EN = int
MCONTR_TOP_0BIT_MCONTR_EN__TYPE = str
MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
MCONTR_TOP_0BIT_REFRESH_EN = int
MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
MCONTR_TOP_0BIT_REFRESH_EN__RAW = str
MCONTR_PHY_16BIT_ADDR = int
MCONTR_PHY_16BIT_ADDR__TYPE = str
MCONTR_PHY_16BIT_ADDR__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK = int
MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
MCONTR_PHY_16BIT_PATTERNS = int
MCONTR_PHY_16BIT_PATTERNS__TYPE = str
MCONTR_PHY_16BIT_PATTERNS__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI = int
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
MCONTR_PHY_16BIT_WBUF_DELAY = int
MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
MCONTR_PHY_16BIT_EXTRA = int
MCONTR_PHY_16BIT_EXTRA__TYPE = str
MCONTR_PHY_16BIT_EXTRA__RAW = str
MCONTR_PHY_STATUS_CNTRL = int
MCONTR_PHY_STATUS_CNTRL__TYPE = str
MCONTR_PHY_STATUS_CNTRL__RAW = str
MCONTR_ARBIT_ADDR = int
MCONTR_ARBIT_ADDR__TYPE = str
MCONTR_ARBIT_ADDR__RAW = str
MCONTR_ARBIT_ADDR_MASK = int
MCONTR_ARBIT_ADDR_MASK__TYPE = str
MCONTR_ARBIT_ADDR_MASK__RAW = str
MCONTR_TOP_16BIT_ADDR = int
MCONTR_TOP_16BIT_ADDR__TYPE = str
MCONTR_TOP_16BIT_ADDR__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK = int
MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
MCONTR_TOP_16BIT_CHN_EN = int
MCONTR_TOP_16BIT_CHN_EN__TYPE = str
MCONTR_TOP_16BIT_CHN_EN__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int
MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
MCONTR_TOP_16BIT_REFRESH_PERIOD__RAW = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__RAW = str
MCONTR_TOP_16BIT_STATUS_CNTRL = int
MCONTR_TOP_16BIT_STATUS_CNTRL__TYPE = str
MCONTR_TOP_16BIT_STATUS_CNTRL__RAW = str
MCONTR_PHY_STATUS_REG_ADDR = int
MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__RAW = str
MCONTR_TOP_STATUS_REG_ADDR = int
MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
MCONTR_TOP_STATUS_REG_ADDR__RAW = str
CHNBUF_READ_LATENCY = int
CHNBUF_READ_LATENCY__TYPE = str
CHNBUF_READ_LATENCY__RAW = str
DFLT_DQS_PATTERN = int
DFLT_DQS_PATTERN__TYPE = str
DFLT_DQS_PATTERN__RAW = str
DFLT_DQM_PATTERN = int
DFLT_DQM_PATTERN__TYPE = str
DFLT_DQM_PATTERN__RAW = str
DFLT_DQ_TRI_ON_PATTERN = int
DFLT_DQ_TRI_ON_PATTERN__TYPE = str
DFLT_DQ_TRI_ON_PATTERN__RAW = str
DFLT_DQ_TRI_OFF_PATTERN = int
DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
DFLT_DQ_TRI_OFF_PATTERN__RAW = str
DFLT_DQS_TRI_ON_PATTERN = int
DFLT_DQS_TRI_ON_PATTERN__TYPE = str
DFLT_DQS_TRI_ON_PATTERN__RAW = str
DFLT_DQS_TRI_OFF_PATTERN = int
DFLT_DQS_TRI_OFF_PATTERN__TYPE = str
DFLT_DQS_TRI_OFF_PATTERN__RAW = str
DFLT_WBUF_DELAY = int
DFLT_WBUF_DELAY__TYPE = str
DFLT_WBUF_DELAY__RAW = str
DFLT_INV_CLK_DIV = int
DFLT_INV_CLK_DIV__TYPE = str
DFLT_INV_CLK_DIV__RAW = str
DFLT_CHN_EN = int
DFLT_CHN_EN__TYPE = str
DFLT_CHN_EN__RAW = str
DFLT_REFRESH_ADDR = int
DFLT_REFRESH_ADDR__TYPE = str
DFLT_REFRESH_ADDR__RAW = str
DFLT_REFRESH_PERIOD = int
DFLT_REFRESH_PERIOD__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
ADDRESS_NUMBER = int
ADDRESS_NUMBER__TYPE = str
ADDRESS_NUMBER__RAW = str
COLADDR_NUMBER = int
COLADDR_NUMBER__TYPE = str
COLADDR_NUMBER__RAW = str
PHASE_WIDTH = int
PHASE_WIDTH__TYPE = str
PHASE_WIDTH__RAW = str
SLEW_DQ = str
SLEW_DQ__TYPE = str
SLEW_DQ__RAW = str
SLEW_DQS = str
SLEW_DQS__TYPE = str
SLEW_DQS__RAW = str
SLEW_CMDA = str
SLEW_CMDA__TYPE = str
SLEW_CMDA__RAW = str
SLEW_CLK = str
SLEW_CLK__TYPE = str
SLEW_CLK__RAW = str
IBUF_LOW_PWR = str
IBUF_LOW_PWR__TYPE = str
IBUF_LOW_PWR__RAW = str
REFCLK_FREQUENCY = float
REFCLK_FREQUENCY__TYPE = str
REFCLK_FREQUENCY__RAW = str
HIGH_PERFORMANCE_MODE = str
HIGH_PERFORMANCE_MODE__TYPE = str
HIGH_PERFORMANCE_MODE__RAW = str
CLKIN_PERIOD = int
CLKIN_PERIOD__TYPE = str
CLKIN_PERIOD__RAW = str
CLKFBOUT_MULT = int
CLKFBOUT_MULT__TYPE = str
CLKFBOUT_MULT__RAW = str
DIVCLK_DIVIDE = int
DIVCLK_DIVIDE__TYPE = str
DIVCLK_DIVIDE__RAW = str
CLKFBOUT_USE_FINE_PS = int
CLKFBOUT_USE_FINE_PS__TYPE = str
CLKFBOUT_USE_FINE_PS__RAW = str
CLKFBOUT_PHASE = float
CLKFBOUT_PHASE__TYPE = str
CLKFBOUT_PHASE__RAW = str
SDCLK_PHASE = float
SDCLK_PHASE__TYPE = str
SDCLK_PHASE__RAW = str
CLK_PHASE = float
CLK_PHASE__TYPE = str
CLK_PHASE__RAW = str
CLK_DIV_PHASE = float
CLK_DIV_PHASE__TYPE = str
CLK_DIV_PHASE__RAW = str
MCLK_PHASE = float
MCLK_PHASE__TYPE = str
MCLK_PHASE__RAW = str
REF_JITTER1 = float
REF_JITTER1__TYPE = str
REF_JITTER1__RAW = str
SS_EN = str
SS_EN__TYPE = str
SS_EN__RAW = str
SS_MODE = str
SS_MODE__TYPE = str
SS_MODE__RAW = str
SS_MOD_PERIOD = int
SS_MOD_PERIOD__TYPE = str
SS_MOD_PERIOD__RAW = str
CMD_PAUSE_BITS = int
CMD_PAUSE_BITS__TYPE = str
CMD_PAUSE_BITS__RAW = str
CMD_DONE_BIT = int
CMD_DONE_BIT__TYPE = str
CMD_DONE_BIT__RAW = str
NUM_CYCLES_LOW_BIT = int
NUM_CYCLES_LOW_BIT__TYPE = str
NUM_CYCLES_LOW_BIT__RAW = str
NUM_CYCLES_00 = int
NUM_CYCLES_00__TYPE = str
NUM_CYCLES_00__RAW = str
NUM_CYCLES_01 = int
NUM_CYCLES_01__TYPE = str
NUM_CYCLES_01__RAW = str
NUM_CYCLES_02 = int
NUM_CYCLES_02__TYPE = str
NUM_CYCLES_02__RAW = str
NUM_CYCLES_03 = int
NUM_CYCLES_03__TYPE = str
NUM_CYCLES_03__RAW = str
NUM_CYCLES_04 = int
NUM_CYCLES_04__TYPE = str
NUM_CYCLES_04__RAW = str
NUM_CYCLES_05 = int
NUM_CYCLES_05__TYPE = str
NUM_CYCLES_05__RAW = str
NUM_CYCLES_06 = int
NUM_CYCLES_06__TYPE = str
NUM_CYCLES_06__RAW = str
NUM_CYCLES_07 = int
NUM_CYCLES_07__TYPE = str
NUM_CYCLES_07__RAW = str
NUM_CYCLES_08 = int
NUM_CYCLES_08__TYPE = str
NUM_CYCLES_08__RAW = str
NUM_CYCLES_09 = int
NUM_CYCLES_09__TYPE = str
NUM_CYCLES_09__RAW = str
NUM_CYCLES_10 = int
NUM_CYCLES_10__TYPE = str
NUM_CYCLES_10__RAW = str
NUM_CYCLES_11 = int
NUM_CYCLES_11__TYPE = str
NUM_CYCLES_11__RAW = str
NUM_CYCLES_12 = int
NUM_CYCLES_12__TYPE = str
NUM_CYCLES_12__RAW = str
NUM_CYCLES_13 = int
NUM_CYCLES_13__TYPE = str
NUM_CYCLES_13__RAW = str
NUM_CYCLES_14 = int
NUM_CYCLES_14__TYPE = str
NUM_CYCLES_14__RAW = str
NUM_CYCLES_15 = int
NUM_CYCLES_15__TYPE = str
NUM_CYCLES_15__RAW = str
NUM_CYCLES_16 = int
NUM_CYCLES_16__TYPE = str
NUM_CYCLES_16__RAW = str
NUM_CYCLES_17 = int
NUM_CYCLES_17__TYPE = str
NUM_CYCLES_17__RAW = str
NUM_CYCLES_18 = int
NUM_CYCLES_18__TYPE = str
NUM_CYCLES_18__RAW = str
NUM_CYCLES_19 = int
NUM_CYCLES_19__TYPE = str
NUM_CYCLES_19__RAW = str
NUM_CYCLES_20 = int
NUM_CYCLES_20__TYPE = str
NUM_CYCLES_20__RAW = str
NUM_CYCLES_21 = int
NUM_CYCLES_21__TYPE = str
NUM_CYCLES_21__RAW = str
NUM_CYCLES_22 = int
NUM_CYCLES_22__TYPE = str
NUM_CYCLES_22__RAW = str
NUM_CYCLES_23 = int
NUM_CYCLES_23__TYPE = str
NUM_CYCLES_23__RAW = str
NUM_CYCLES_24 = int
NUM_CYCLES_24__TYPE = str
NUM_CYCLES_24__RAW = str
NUM_CYCLES_25 = int
NUM_CYCLES_25__TYPE = str
NUM_CYCLES_25__RAW = str
NUM_CYCLES_26 = int
NUM_CYCLES_26__TYPE = str
NUM_CYCLES_26__RAW = str
NUM_CYCLES_27 = int
NUM_CYCLES_27__TYPE = str
NUM_CYCLES_27__RAW = str
NUM_CYCLES_28 = int
NUM_CYCLES_28__TYPE = str
NUM_CYCLES_28__RAW = str
NUM_CYCLES_29 = int
NUM_CYCLES_29__TYPE = str
NUM_CYCLES_29__RAW = str
NUM_CYCLES_30 = int
NUM_CYCLES_30__TYPE = str
NUM_CYCLES_30__RAW = str
NUM_CYCLES_31 = int
NUM_CYCLES_31__TYPE = str
NUM_CYCLES_31__RAW = str
MCNTRL_PS_ADDR = int
MCNTRL_PS_ADDR__TYPE = str
MCNTRL_PS_ADDR__RAW = str
MCNTRL_PS_MASK = int
MCNTRL_PS_MASK__TYPE = str
MCNTRL_PS_MASK__RAW = str
MCNTRL_PS_STATUS_REG_ADDR = int
MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
MCNTRL_PS_STATUS_REG_ADDR__RAW = str
MCNTRL_PS_EN_RST = int
MCNTRL_PS_EN_RST__TYPE = str
MCNTRL_PS_EN_RST__RAW = str
MCNTRL_PS_CMD = int
MCNTRL_PS_CMD__TYPE = str
MCNTRL_PS_CMD__RAW = str
MCNTRL_PS_STATUS_CNTRL = int
MCNTRL_PS_STATUS_CNTRL__TYPE = str
MCNTRL_PS_STATUS_CNTRL__RAW = str
NUM_XFER_BITS = int
NUM_XFER_BITS__TYPE = str
NUM_XFER_BITS__RAW = str
FRAME_WIDTH_BITS = int
FRAME_WIDTH_BITS__TYPE = str
FRAME_WIDTH_BITS__RAW = str
FRAME_HEIGHT_BITS = int
FRAME_HEIGHT_BITS__TYPE = str
FRAME_HEIGHT_BITS__RAW = str
LAST_FRAME_BITS = int
LAST_FRAME_BITS__TYPE = str
LAST_FRAME_BITS__RAW = str
MCNTRL_SCANLINE_CHN1_ADDR = int
MCNTRL_SCANLINE_CHN1_ADDR__TYPE = str
MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
MCNTRL_SCANLINE_CHN3_ADDR = int
MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR__RAW = str
MCNTRL_SCANLINE_MASK = int
MCNTRL_SCANLINE_MASK__TYPE = str
MCNTRL_SCANLINE_MASK__RAW = str
MCNTRL_SCANLINE_MODE = int
MCNTRL_SCANLINE_MODE__TYPE = str
MCNTRL_SCANLINE_MODE__RAW = str
MCNTRL_SCANLINE_STATUS_CNTRL = int
MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
MCNTRL_SCANLINE_STARTADDR = int
MCNTRL_SCANLINE_STARTADDR__TYPE = str
MCNTRL_SCANLINE_STARTADDR__RAW = str
MCNTRL_SCANLINE_FRAME_SIZE = int
MCNTRL_SCANLINE_FRAME_SIZE__TYPE = str
MCNTRL_SCANLINE_FRAME_SIZE__RAW = str
MCNTRL_SCANLINE_FRAME_LAST = int
MCNTRL_SCANLINE_FRAME_LAST__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST__RAW = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__TYPE = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
MCNTRL_SCANLINE_WINDOW_WH = int
MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
MCNTRL_SCANLINE_WINDOW_WH__RAW = str
MCNTRL_SCANLINE_WINDOW_X0Y0 = int
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
MCNTRL_SCANLINE_WINDOW_X0Y0__RAW = str
MCNTRL_SCANLINE_WINDOW_STARTXY = int
MCNTRL_SCANLINE_WINDOW_STARTXY__TYPE = str
MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
MAX_TILE_WIDTH = int
MAX_TILE_WIDTH__TYPE = str
MAX_TILE_WIDTH__RAW = str
MAX_TILE_HEIGHT = int
MAX_TILE_HEIGHT__TYPE = str
MAX_TILE_HEIGHT__RAW = str
MCNTRL_TILED_CHN2_ADDR = int
MCNTRL_TILED_CHN2_ADDR__TYPE = str
MCNTRL_TILED_CHN2_ADDR__RAW = str
MCNTRL_TILED_CHN4_ADDR = int
MCNTRL_TILED_CHN4_ADDR__TYPE = str
MCNTRL_TILED_CHN4_ADDR__RAW = str
MCNTRL_TILED_MASK = int
MCNTRL_TILED_MASK__TYPE = str
MCNTRL_TILED_MASK__RAW = str
MCNTRL_TILED_MODE = int
MCNTRL_TILED_MODE__TYPE = str
MCNTRL_TILED_MODE__RAW = str
MCNTRL_TILED_STATUS_CNTRL = int
MCNTRL_TILED_STATUS_CNTRL__TYPE = str
MCNTRL_TILED_STATUS_CNTRL__RAW = str
MCNTRL_TILED_STARTADDR = int
MCNTRL_TILED_STARTADDR__TYPE = str
MCNTRL_TILED_STARTADDR__RAW = str
MCNTRL_TILED_FRAME_SIZE = int
MCNTRL_TILED_FRAME_SIZE__TYPE = str
MCNTRL_TILED_FRAME_SIZE__RAW = str
MCNTRL_TILED_FRAME_LAST = int
MCNTRL_TILED_FRAME_LAST__TYPE = str
MCNTRL_TILED_FRAME_LAST__RAW = str
MCNTRL_TILED_FRAME_FULL_WIDTH = int
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
MCNTRL_TILED_WINDOW_WH = int
MCNTRL_TILED_WINDOW_WH__TYPE = str
MCNTRL_TILED_WINDOW_WH__RAW = str
MCNTRL_TILED_WINDOW_X0Y0 = int
MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str
MCNTRL_TILED_WINDOW_STARTXY = int
MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
MCNTRL_TILED_WINDOW_STARTXY__RAW = str
MCNTRL_TILED_TILE_WHS = int
MCNTRL_TILED_TILE_WHS__TYPE = str
MCNTRL_TILED_TILE_WHS__RAW = str
MCNTRL_SCANLINE_START_DELAY = int
MCNTRL_SCANLINE_START_DELAY__TYPE = str
MCNTRL_SCANLINE_START_DELAY__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
MCNTRL_TILED_PENDING_CNTR_BITS = int
MCNTRL_TILED_PENDING_CNTR_BITS__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
MCNTRL_TILED_FRAME_PAGE_RESET = int
MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str
MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str
BUFFER_DEPTH32 = int
BUFFER_DEPTH32__TYPE = str
BUFFER_DEPTH32__RAW = str
MCONTR_LINTILE_NRESET = int
MCONTR_LINTILE_NRESET__TYPE = str
MCONTR_LINTILE_NRESET__RAW = str
MCONTR_LINTILE_EN = int
MCONTR_LINTILE_EN__TYPE = str
MCONTR_LINTILE_EN__RAW = str
MCONTR_LINTILE_WRITE = int
MCONTR_LINTILE_WRITE__TYPE = str
MCONTR_LINTILE_WRITE__RAW = str
MCONTR_LINTILE_EXTRAPG = int
MCONTR_LINTILE_EXTRAPG__TYPE = str
MCONTR_LINTILE_EXTRAPG__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS = int
MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
MCONTR_LINTILE_KEEP_OPEN = int
MCONTR_LINTILE_KEEP_OPEN__TYPE = str
MCONTR_LINTILE_KEEP_OPEN__RAW = str
MCONTR_LINTILE_BYTE32 = int
MCONTR_LINTILE_BYTE32__TYPE = str
MCONTR_LINTILE_BYTE32__RAW = str
MCONTR_LINTILE_LINEAR = int
MCONTR_LINTILE_LINEAR__TYPE = str
MCONTR_LINTILE_LINEAR__RAW = str
MCONTR_LINTILE_RST_FRAME = int
MCONTR_LINTILE_RST_FRAME__TYPE = str
MCONTR_LINTILE_RST_FRAME__RAW = str
MCONTR_LINTILE_SINGLE = int
MCONTR_LINTILE_SINGLE__TYPE = str
MCONTR_LINTILE_SINGLE__RAW = str
MCONTR_LINTILE_REPEAT = int
MCONTR_LINTILE_REPEAT__TYPE = str
MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_LINTILE_DIS_NEED = int
MCONTR_LINTILE_DIS_NEED__TYPE = str
MCONTR_LINTILE_DIS_NEED__RAW = str
MCONTR_LINTILE_SKIP_LATE = int
MCONTR_LINTILE_SKIP_LATE__TYPE = str
MCONTR_LINTILE_SKIP_LATE__RAW = str
MCONTR_LINTILE_COPY_FRAME = int
MCONTR_LINTILE_COPY_FRAME__TYPE = str
MCONTR_LINTILE_COPY_FRAME__RAW = str
MCONTR_LINTILE_ABORT_LATE = int
MCONTR_LINTILE_ABORT_LATE__TYPE = str
MCONTR_LINTILE_ABORT_LATE__RAW = str
MCNTRL_SCANLINE_DLY_WIDTH = int
MCNTRL_SCANLINE_DLY_WIDTH__TYPE = str
MCNTRL_SCANLINE_DLY_WIDTH__RAW = str
MCNTRL_SCANLINE_DLY_DEFAULT = int
MCNTRL_SCANLINE_DLY_DEFAULT__TYPE = str
MCNTRL_SCANLINE_DLY_DEFAULT__RAW = str
MCNTRL_TEST01_ADDR = int
MCNTRL_TEST01_ADDR__TYPE = str
MCNTRL_TEST01_ADDR__RAW = str
MCNTRL_TEST01_MASK = int
MCNTRL_TEST01_MASK__TYPE = str
MCNTRL_TEST01_MASK__RAW = str
MCNTRL_TEST01_CHN1_MODE = int
MCNTRL_TEST01_CHN1_MODE__TYPE = str
MCNTRL_TEST01_CHN1_MODE__RAW = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
MCNTRL_TEST01_CHN1_STATUS_CNTRL__TYPE = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
MCNTRL_TEST01_CHN2_MODE = int
MCNTRL_TEST01_CHN2_MODE__TYPE = str
MCNTRL_TEST01_CHN2_MODE__RAW = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
MCNTRL_TEST01_CHN2_STATUS_CNTRL__TYPE = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
MCNTRL_TEST01_CHN3_MODE = int
MCNTRL_TEST01_CHN3_MODE__TYPE = str
MCNTRL_TEST01_CHN3_MODE__RAW = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
MCNTRL_TEST01_CHN4_MODE = int
MCNTRL_TEST01_CHN4_MODE__TYPE = str
MCNTRL_TEST01_CHN4_MODE__RAW = str
MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str
MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR = int
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR = int
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR = int
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
MCONTR_SENS_BASE = int
MCONTR_SENS_BASE__TYPE = str
MCONTR_SENS_BASE__RAW = str
MCONTR_SENS_INC = int
MCONTR_SENS_INC__TYPE = str
MCONTR_SENS_INC__RAW = str
MCONTR_CMPRS_BASE = int
MCONTR_CMPRS_BASE__TYPE = str
MCONTR_CMPRS_BASE__RAW = str
MCONTR_CMPRS_INC = int
MCONTR_CMPRS_INC__TYPE = str
MCONTR_CMPRS_INC__RAW = str
MCONTR_SENS_STATUS_BASE = int
MCONTR_SENS_STATUS_BASE__TYPE = str
MCONTR_SENS_STATUS_BASE__RAW = str
MCONTR_SENS_STATUS_INC = int
MCONTR_SENS_STATUS_INC__TYPE = str
MCONTR_SENS_STATUS_INC__RAW = str
MCONTR_CMPRS_STATUS_BASE = int
MCONTR_CMPRS_STATUS_BASE__TYPE = str
MCONTR_CMPRS_STATUS_BASE__RAW = str
MCONTR_CMPRS_STATUS_INC = int
MCONTR_CMPRS_STATUS_INC__TYPE = str
MCONTR_CMPRS_STATUS_INC__RAW = str
MEMBRIDGE_ADDR = int
MEMBRIDGE_ADDR__TYPE = str
MEMBRIDGE_ADDR__RAW = str
MEMBRIDGE_MASK = int
MEMBRIDGE_MASK__TYPE = str
MEMBRIDGE_MASK__RAW = str
MEMBRIDGE_CTRL = int
MEMBRIDGE_CTRL__TYPE = str
MEMBRIDGE_CTRL__RAW = str
MEMBRIDGE_STATUS_CNTRL = int
MEMBRIDGE_STATUS_CNTRL__TYPE = str
MEMBRIDGE_STATUS_CNTRL__RAW = str
MEMBRIDGE_LO_ADDR64 = int
MEMBRIDGE_LO_ADDR64__TYPE = str
MEMBRIDGE_LO_ADDR64__RAW = str
MEMBRIDGE_SIZE64 = int
MEMBRIDGE_SIZE64__TYPE = str
MEMBRIDGE_SIZE64__RAW = str
MEMBRIDGE_START64 = int
MEMBRIDGE_START64__TYPE = str
MEMBRIDGE_START64__RAW = str
MEMBRIDGE_LEN64 = int
MEMBRIDGE_LEN64__TYPE = str
MEMBRIDGE_LEN64__RAW = str
MEMBRIDGE_WIDTH64 = int
MEMBRIDGE_WIDTH64__TYPE = str
MEMBRIDGE_WIDTH64__RAW = str
MEMBRIDGE_CTRL_IRQ = int
MEMBRIDGE_CTRL_IRQ__TYPE = str
MEMBRIDGE_CTRL_IRQ__RAW = str
MEMBRIDGE_STATUS_REG = int
MEMBRIDGE_STATUS_REG__TYPE = str
MEMBRIDGE_STATUS_REG__RAW = str
RSEL = int
RSEL__TYPE = str
RSEL__RAW = str
WSEL = int
WSEL__TYPE = str
WSEL__RAW = str
SENSOR_GROUP_ADDR = int
SENSOR_GROUP_ADDR__TYPE = str
SENSOR_GROUP_ADDR__RAW = str
SENSOR_BASE_INC = int
SENSOR_BASE_INC__TYPE = str
SENSOR_BASE_INC__RAW = str
HIST_SAXI_ADDR_REL = int
HIST_SAXI_ADDR_REL__TYPE = str
HIST_SAXI_ADDR_REL__RAW = str
HIST_SAXI_MODE_ADDR_REL = int
HIST_SAXI_MODE_ADDR_REL__TYPE = str
HIST_SAXI_MODE_ADDR_REL__RAW = str
SENSI2C_STATUS_REG_BASE = int
SENSI2C_STATUS_REG_BASE__TYPE = str
SENSI2C_STATUS_REG_BASE__RAW = str
SENSI2C_STATUS_REG_INC = int
SENSI2C_STATUS_REG_INC__TYPE = str
SENSI2C_STATUS_REG_INC__RAW = str
SENSI2C_STATUS_REG_REL = int
SENSI2C_STATUS_REG_REL__TYPE = str
SENSI2C_STATUS_REG_REL__RAW = str
SENSIO_STATUS_REG_REL = int
SENSIO_STATUS_REG_REL__TYPE = str
SENSIO_STATUS_REG_REL__RAW = str
SENSOR_TIMING_STATUS_REG_BASE = int
SENSOR_TIMING_STATUS_REG_BASE__TYPE = str
SENSOR_TIMING_STATUS_REG_BASE__RAW = str
SENSOR_TIMING_STATUS_REG_INC = int
SENSOR_TIMING_STATUS_REG_INC__TYPE = str
SENSOR_TIMING_STATUS_REG_INC__RAW = str
SENSOR_TIMING_BITS = int
SENSOR_TIMING_BITS__TYPE = str
SENSOR_TIMING_BITS__RAW = str
SENSOR_TIMING_START = int
SENSOR_TIMING_START__TYPE = str
SENSOR_TIMING_START__RAW = str
SENSOR_TIMING_LANE = int
SENSOR_TIMING_LANE__TYPE = str
SENSOR_TIMING_LANE__RAW = str
SENSOR_TIMING_FROM = int
SENSOR_TIMING_FROM__TYPE = str
SENSOR_TIMING_FROM__RAW = str
SENSOR_TIMING_TO = int
SENSOR_TIMING_TO__TYPE = str
SENSOR_TIMING_TO__RAW = str
SENSOR_NUM_HISTOGRAM = int
SENSOR_NUM_HISTOGRAM__TYPE = str
SENSOR_NUM_HISTOGRAM__RAW = str
HISTOGRAM_RAM_MODE = str
HISTOGRAM_RAM_MODE__TYPE = str
HISTOGRAM_RAM_MODE__RAW = str
SENS_NUM_SUBCHN = int
SENS_NUM_SUBCHN__TYPE = str
SENS_NUM_SUBCHN__RAW = str
SENS_GAMMA_BUFFER = int
SENS_GAMMA_BUFFER__TYPE = str
SENS_GAMMA_BUFFER__RAW = str
SENSOR_CTRL_RADDR = int
SENSOR_CTRL_RADDR__TYPE = str
SENSOR_CTRL_RADDR__RAW = str
SENSOR_CTRL_ADDR_MASK = int
SENSOR_CTRL_ADDR_MASK__TYPE = str
SENSOR_CTRL_ADDR_MASK__RAW = str
SENSOR_HIST_EN_BITS = int
SENSOR_HIST_EN_BITS__TYPE = str
SENSOR_HIST_EN_BITS__RAW = str
SENSOR_HIST_NRST_BITS = int
SENSOR_HIST_NRST_BITS__TYPE = str
SENSOR_HIST_NRST_BITS__RAW = str
SENSOR_HIST_BITS_SET = int
SENSOR_HIST_BITS_SET__TYPE = str
SENSOR_HIST_BITS_SET__RAW = str
SENSOR_CHN_EN_BIT = int
SENSOR_CHN_EN_BIT__TYPE = str
SENSOR_CHN_EN_BIT__RAW = str
SENSOR_CHN_EN_BIT_SET = int
SENSOR_CHN_EN_BIT_SET__TYPE = str
SENSOR_CHN_EN_BIT_SET__RAW = str
SENSOR_16BIT_BIT = int
SENSOR_16BIT_BIT__TYPE = str
SENSOR_16BIT_BIT__RAW = str
SENSOR_16BIT_BIT_SET = int
SENSOR_16BIT_BIT_SET__TYPE = str
SENSOR_16BIT_BIT_SET__RAW = str
SENSI2C_CTRL_RADDR = int
SENSI2C_CTRL_RADDR__TYPE = str
SENSI2C_CTRL_RADDR__RAW = str
SENSI2C_CTRL_MASK = int
SENSI2C_CTRL_MASK__TYPE = str
SENSI2C_CTRL_MASK__RAW = str
SENSI2C_CTRL = int
SENSI2C_CTRL__TYPE = str
SENSI2C_CTRL__RAW = str
SENSI2C_CMD_TABLE = int
SENSI2C_CMD_TABLE__TYPE = str
SENSI2C_CMD_TABLE__RAW = str
SENSI2C_CMD_TAND = int
SENSI2C_CMD_TAND__TYPE = str
SENSI2C_CMD_TAND__RAW = str
SENSI2C_CMD_RESET = int
SENSI2C_CMD_RESET__TYPE = str
SENSI2C_CMD_RESET__RAW = str
SENSI2C_CMD_RUN = int
SENSI2C_CMD_RUN__TYPE = str
SENSI2C_CMD_RUN__RAW = str
SENSI2C_CMD_RUN_PBITS = int
SENSI2C_CMD_RUN_PBITS__TYPE = str
SENSI2C_CMD_RUN_PBITS__RAW = str
SENSI2C_CMD_USE_EOF = int
SENSI2C_CMD_USE_EOF__TYPE = str
SENSI2C_CMD_USE_EOF__RAW = str
SENSI2C_CMD_SOFT_SDA = int
SENSI2C_CMD_SOFT_SDA__TYPE = str
SENSI2C_CMD_SOFT_SDA__RAW = str
SENSI2C_CMD_SOFT_SCL = int
SENSI2C_CMD_SOFT_SCL__TYPE = str
SENSI2C_CMD_SOFT_SCL__RAW = str
SENSI2C_CMD_FIFO_RD = int
SENSI2C_CMD_FIFO_RD__TYPE = str
SENSI2C_CMD_FIFO_RD__RAW = str
SENSI2C_CMD_ACIVE = int
SENSI2C_CMD_ACIVE__TYPE = str
SENSI2C_CMD_ACIVE__RAW = str
SENSI2C_CMD_ACIVE_EARLY0 = int
SENSI2C_CMD_ACIVE_EARLY0__TYPE = str
SENSI2C_CMD_ACIVE_EARLY0__RAW = str
SENSI2C_CMD_ACIVE_SDA = int
SENSI2C_CMD_ACIVE_SDA__TYPE = str
SENSI2C_CMD_ACIVE_SDA__RAW = str
SENSI2C_TBL_RAH = int
SENSI2C_TBL_RAH__TYPE = str
SENSI2C_TBL_RAH__RAW = str
SENSI2C_TBL_RAH_BITS = int
SENSI2C_TBL_RAH_BITS__TYPE = str
SENSI2C_TBL_RAH_BITS__RAW = str
SENSI2C_TBL_RNWREG = int
SENSI2C_TBL_RNWREG__TYPE = str
SENSI2C_TBL_RNWREG__RAW = str
SENSI2C_TBL_SA = int
SENSI2C_TBL_SA__TYPE = str
SENSI2C_TBL_SA__RAW = str
SENSI2C_TBL_SA_BITS = int
SENSI2C_TBL_SA_BITS__TYPE = str
SENSI2C_TBL_SA_BITS__RAW = str
SENSI2C_TBL_NBWR = int
SENSI2C_TBL_NBWR__TYPE = str
SENSI2C_TBL_NBWR__RAW = str
SENSI2C_TBL_NBWR_BITS = int
SENSI2C_TBL_NBWR_BITS__TYPE = str
SENSI2C_TBL_NBWR_BITS__RAW = str
SENSI2C_TBL_NBRD = int
SENSI2C_TBL_NBRD__TYPE = str
SENSI2C_TBL_NBRD__RAW = str
SENSI2C_TBL_NBRD_BITS = int
SENSI2C_TBL_NBRD_BITS__TYPE = str
SENSI2C_TBL_NBRD_BITS__RAW = str
SENSI2C_TBL_NABRD = int
SENSI2C_TBL_NABRD__TYPE = str
SENSI2C_TBL_NABRD__RAW = str
SENSI2C_TBL_DLY = int
SENSI2C_TBL_DLY__TYPE = str
SENSI2C_TBL_DLY__RAW = str
SENSI2C_TBL_DLY_BITS = int
SENSI2C_TBL_DLY_BITS__TYPE = str
SENSI2C_TBL_DLY_BITS__RAW = str
SENSI2C_STATUS = int
SENSI2C_STATUS__TYPE = str
SENSI2C_STATUS__RAW = str
SENS_SYNC_RADDR = int
SENS_SYNC_RADDR__TYPE = str
SENS_SYNC_RADDR__RAW = str
SENS_SYNC_MASK = int
SENS_SYNC_MASK__TYPE = str
SENS_SYNC_MASK__RAW = str
SENS_SYNC_MULT = int
SENS_SYNC_MULT__TYPE = str
SENS_SYNC_MULT__RAW = str
SENS_SYNC_LATE = int
SENS_SYNC_LATE__TYPE = str
SENS_SYNC_LATE__RAW = str
SENS_GAMMA_RADDR = int
SENS_GAMMA_RADDR__TYPE = str
SENS_GAMMA_RADDR__RAW = str
SENS_GAMMA_ADDR_MASK = int
SENS_GAMMA_ADDR_MASK__TYPE = str
SENS_GAMMA_ADDR_MASK__RAW = str
SENS_GAMMA_CTRL = int
SENS_GAMMA_CTRL__TYPE = str
SENS_GAMMA_CTRL__RAW = str
SENS_GAMMA_ADDR_DATA = int
SENS_GAMMA_ADDR_DATA__TYPE = str
SENS_GAMMA_ADDR_DATA__RAW = str
SENS_GAMMA_HEIGHT01 = int
SENS_GAMMA_HEIGHT01__TYPE = str
SENS_GAMMA_HEIGHT01__RAW = str
SENS_GAMMA_HEIGHT2 = int
SENS_GAMMA_HEIGHT2__TYPE = str
SENS_GAMMA_HEIGHT2__RAW = str
SENS_GAMMA_MODE_BAYER = int
SENS_GAMMA_MODE_BAYER__TYPE = str
SENS_GAMMA_MODE_BAYER__RAW = str
SENS_GAMMA_MODE_BAYER_SET = int
SENS_GAMMA_MODE_BAYER_SET__TYPE = str
SENS_GAMMA_MODE_BAYER_SET__RAW = str
SENS_GAMMA_MODE_PAGE = int
SENS_GAMMA_MODE_PAGE__TYPE = str
SENS_GAMMA_MODE_PAGE__RAW = str
SENS_GAMMA_MODE_PAGE_SET = int
SENS_GAMMA_MODE_PAGE_SET__TYPE = str
SENS_GAMMA_MODE_PAGE_SET__RAW = str
SENS_GAMMA_MODE_EN = int
SENS_GAMMA_MODE_EN__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENS_GAMMA_MODE_EN_SET = int
SENS_GAMMA_MODE_EN_SET__TYPE = str
SENS_GAMMA_MODE_EN_SET__RAW = str
SENS_GAMMA_MODE_REPET = int
SENS_GAMMA_MODE_REPET__TYPE = str
SENS_GAMMA_MODE_REPET__RAW = str
SENS_GAMMA_MODE_REPET_SET = int
SENS_GAMMA_MODE_REPET_SET__TYPE = str
SENS_GAMMA_MODE_REPET_SET__RAW = str
SENS_GAMMA_MODE_TRIG = int
SENS_GAMMA_MODE_TRIG__TYPE = str
SENS_GAMMA_MODE_TRIG__RAW = str
SENS_LENS_RADDR = int
SENS_LENS_RADDR__TYPE = str
SENS_LENS_RADDR__RAW = str
SENS_LENS_ADDR_MASK = int
SENS_LENS_ADDR_MASK__TYPE = str
SENS_LENS_ADDR_MASK__RAW = str
SENS_LENS_COEFF = int
SENS_LENS_COEFF__TYPE = str
SENS_LENS_COEFF__RAW = str
SENS_LENS_AX = int
SENS_LENS_AX__TYPE = str
SENS_LENS_AX__RAW = str
SENS_LENS_AX_MASK = int
SENS_LENS_AX_MASK__TYPE = str
SENS_LENS_AX_MASK__RAW = str
SENS_LENS_AY = int
SENS_LENS_AY__TYPE = str
SENS_LENS_AY__RAW = str
SENS_LENS_AY_MASK = int
SENS_LENS_AY_MASK__TYPE = str
SENS_LENS_AY_MASK__RAW = str
SENS_LENS_C = int
SENS_LENS_C__TYPE = str
SENS_LENS_C__RAW = str
SENS_LENS_C_MASK = int
SENS_LENS_C_MASK__TYPE = str
SENS_LENS_C_MASK__RAW = str
SENS_LENS_BX = int
SENS_LENS_BX__TYPE = str
SENS_LENS_BX__RAW = str
SENS_LENS_BX_MASK = int
SENS_LENS_BX_MASK__TYPE = str
SENS_LENS_BX_MASK__RAW = str
SENS_LENS_BY = int
SENS_LENS_BY__TYPE = str
SENS_LENS_BY__RAW = str
SENS_LENS_BY_MASK = int
SENS_LENS_BY_MASK__TYPE = str
SENS_LENS_BY_MASK__RAW = str
SENS_LENS_SCALES = int
SENS_LENS_SCALES__TYPE = str
SENS_LENS_SCALES__RAW = str
SENS_LENS_SCALES_MASK = int
SENS_LENS_SCALES_MASK__TYPE = str
SENS_LENS_SCALES_MASK__RAW = str
SENS_LENS_FAT0_IN = int
SENS_LENS_FAT0_IN__TYPE = str
SENS_LENS_FAT0_IN__RAW = str
SENS_LENS_FAT0_IN_MASK = int
SENS_LENS_FAT0_IN_MASK__TYPE = str
SENS_LENS_FAT0_IN_MASK__RAW = str
SENS_LENS_FAT0_OUT = int
SENS_LENS_FAT0_OUT__TYPE = str
SENS_LENS_FAT0_OUT__RAW = str
SENS_LENS_FAT0_OUT_MASK = int
SENS_LENS_FAT0_OUT_MASK__TYPE = str
SENS_LENS_FAT0_OUT_MASK__RAW = str
SENS_LENS_POST_SCALE = int
SENS_LENS_POST_SCALE__TYPE = str
SENS_LENS_POST_SCALE__RAW = str
SENS_LENS_POST_SCALE_MASK = int
SENS_LENS_POST_SCALE_MASK__TYPE = str
SENS_LENS_POST_SCALE_MASK__RAW = str
SENSIO_RADDR = int
SENSIO_RADDR__TYPE = str
SENSIO_RADDR__RAW = str
SENSIO_ADDR_MASK = int
SENSIO_ADDR_MASK__TYPE = str
SENSIO_ADDR_MASK__RAW = str
SENSIO_CTRL = int
SENSIO_CTRL__TYPE = str
SENSIO_CTRL__RAW = str
SENS_CTRL_MRST = int
SENS_CTRL_MRST__TYPE = str
SENS_CTRL_MRST__RAW = str
SENS_CTRL_ARST = int
SENS_CTRL_ARST__TYPE = str
SENS_CTRL_ARST__RAW = str
SENS_CTRL_ARO = int
SENS_CTRL_ARO__TYPE = str
SENS_CTRL_ARO__RAW = str
SENS_CTRL_RST_MMCM = int
SENS_CTRL_RST_MMCM__TYPE = str
SENS_CTRL_RST_MMCM__RAW = str
SENS_CTRL_IGNORE_EMBED = int
SENS_CTRL_IGNORE_EMBED__TYPE = str
SENS_CTRL_IGNORE_EMBED__RAW = str
SENS_CTRL_EXT_CLK = int
SENS_CTRL_EXT_CLK__TYPE = str
SENS_CTRL_EXT_CLK__RAW = str
SENS_CTRL_LD_DLY = int
SENS_CTRL_LD_DLY__TYPE = str
SENS_CTRL_LD_DLY__RAW = str
SENS_CTRL_GP0 = int
SENS_CTRL_GP0__TYPE = str
SENS_CTRL_GP0__RAW = str
SENS_CTRL_GP1 = int
SENS_CTRL_GP1__TYPE = str
SENS_CTRL_GP1__RAW = str
SENS_CTRL_GP2 = int
SENS_CTRL_GP2__TYPE = str
SENS_CTRL_GP2__RAW = str
SENS_CTRL_GP3 = int
SENS_CTRL_GP3__TYPE = str
SENS_CTRL_GP3__RAW = str
SENS_UART_EXTIF_EN = int
SENS_UART_EXTIF_EN__TYPE = str
SENS_UART_EXTIF_EN__RAW = str
SENS_UART_XMIT_RST = int
SENS_UART_XMIT_RST__TYPE = str
SENS_UART_XMIT_RST__RAW = str
SENS_UART_RECV_RST = int
SENS_UART_RECV_RST__TYPE = str
SENS_UART_RECV_RST__RAW = str
SENS_UART_XMIT_START = int
SENS_UART_XMIT_START__TYPE = str
SENS_UART_XMIT_START__RAW = str
SENS_UART_RECV_NEXT = int
SENS_UART_RECV_NEXT__TYPE = str
SENS_UART_RECV_NEXT__RAW = str
SENS_CTRL_QUADRANTS = int
SENS_CTRL_QUADRANTS__TYPE = str
SENS_CTRL_QUADRANTS__RAW = str
SENS_CTRL_QUADRANTS_WIDTH = int
SENS_CTRL_QUADRANTS_WIDTH__TYPE = str
SENS_CTRL_QUADRANTS_WIDTH__RAW = str
SENS_CTRL_ODD = int
SENS_CTRL_ODD__TYPE = str
SENS_CTRL_ODD__RAW = str
SENS_CTRL_QUADRANTS_EN = int
SENS_CTRL_QUADRANTS_EN__TYPE = str
SENS_CTRL_QUADRANTS_EN__RAW = str
SENSIO_STATUS = int
SENSIO_STATUS__TYPE = str
SENSIO_STATUS__RAW = str
SENSIO_JTAG = int
SENSIO_JTAG__TYPE = str
SENSIO_JTAG__RAW = str
SENS_JTAG_PGMEN = int
SENS_JTAG_PGMEN__TYPE = str
SENS_JTAG_PGMEN__RAW = str
SENS_JTAG_PROG = int
SENS_JTAG_PROG__TYPE = str
SENS_JTAG_PROG__RAW = str
SENS_JTAG_TCK = int
SENS_JTAG_TCK__TYPE = str
SENS_JTAG_TCK__RAW = str
SENS_JTAG_TMS = int
SENS_JTAG_TMS__TYPE = str
SENS_JTAG_TMS__RAW = str
SENS_JTAG_TDI = int
SENS_JTAG_TDI__TYPE = str
SENS_JTAG_TDI__RAW = str
SENSIO_WIDTH = int
SENSIO_WIDTH__TYPE = str
SENSIO_WIDTH__RAW = str
SENSIO_DELAYS = int
SENSIO_DELAYS__TYPE = str
SENSIO_DELAYS__RAW = str
SENSI2C_ABS_RADDR = int
SENSI2C_ABS_RADDR__TYPE = str
SENSI2C_ABS_RADDR__RAW = str
SENSI2C_REL_RADDR = int
SENSI2C_REL_RADDR__TYPE = str
SENSI2C_REL_RADDR__RAW = str
SENSI2C_ADDR_MASK = int
SENSI2C_ADDR_MASK__TYPE = str
SENSI2C_ADDR_MASK__RAW = str
HISTOGRAM_RADDR_INC = int
HISTOGRAM_RADDR_INC__TYPE = str
HISTOGRAM_RADDR_INC__RAW = str
HISTOGRAM_RADDR0 = int
HISTOGRAM_RADDR0__TYPE = str
HISTOGRAM_RADDR0__RAW = str
HISTOGRAM_RADDR1 = int
HISTOGRAM_RADDR1__TYPE = str
HISTOGRAM_RADDR1__RAW = str
HISTOGRAM_RADDR2 = int
HISTOGRAM_RADDR2__TYPE = str
HISTOGRAM_RADDR2__RAW = str
HISTOGRAM_RADDR3 = int
HISTOGRAM_RADDR3__TYPE = str
HISTOGRAM_RADDR3__RAW = str
HISTOGRAM_ADDR_MASK = int
HISTOGRAM_ADDR_MASK__TYPE = str
HISTOGRAM_ADDR_MASK__RAW = str
HISTOGRAM_LEFT_TOP = int
HISTOGRAM_LEFT_TOP__TYPE = str
HISTOGRAM_LEFT_TOP__RAW = str
HISTOGRAM_WIDTH_HEIGHT = int
HISTOGRAM_WIDTH_HEIGHT__TYPE = str
HISTOGRAM_WIDTH_HEIGHT__RAW = str
XOR_HIST_BAYER = int
XOR_HIST_BAYER__TYPE = str
XOR_HIST_BAYER__RAW = str
SENSI2C_DRIVE = int
SENSI2C_DRIVE__TYPE = str
SENSI2C_DRIVE__RAW = str
SENSI2C_IBUF_LOW_PWR = str
SENSI2C_IBUF_LOW_PWR__TYPE = str
SENSI2C_IBUF_LOW_PWR__RAW = str
SENSI2C_SLEW = str
SENSI2C_SLEW__TYPE = str
SENSI2C_SLEW__RAW = str
VOSPI_MRST = int
VOSPI_MRST__TYPE = str
VOSPI_MRST__RAW = str
VOSPI_MRST_BITS = int
VOSPI_MRST_BITS__TYPE = str
VOSPI_MRST_BITS__RAW = str
VOSPI_RST_SEQ = int
VOSPI_RST_SEQ__TYPE = str
VOSPI_RST_SEQ__RAW = str
VOSPI_SPI_SEQ = int
VOSPI_SPI_SEQ__TYPE = str
VOSPI_SPI_SEQ__RAW = str
VOSPI_MCLK = int
VOSPI_MCLK__TYPE = str
VOSPI_MCLK__RAW = str
VOSPI_MCLK_BITS = int
VOSPI_MCLK_BITS__TYPE = str
VOSPI_MCLK_BITS__RAW = str
VOSPI_EN = int
VOSPI_EN__TYPE = str
VOSPI_EN__RAW = str
VOSPI_EN_BITS = int
VOSPI_EN_BITS__TYPE = str
VOSPI_EN_BITS__RAW = str
VOSPI_OUT_EN = int
VOSPI_OUT_EN__TYPE = str
VOSPI_OUT_EN__RAW = str
VOSPI_OUT_EN_BITS = int
VOSPI_OUT_EN_BITS__TYPE = str
VOSPI_OUT_EN_BITS__RAW = str
VOSPI_OUT_EN_SINGL = int
VOSPI_OUT_EN_SINGL__TYPE = str
VOSPI_OUT_EN_SINGL__RAW = str
VOSPI_RESET_ERR = int
VOSPI_RESET_ERR__TYPE = str
VOSPI_RESET_ERR__RAW = str
VOSPI_SPI_CLK = int
VOSPI_SPI_CLK__TYPE = str
VOSPI_SPI_CLK__RAW = str
VOSPI_SPI_CLK_BITS = int
VOSPI_SPI_CLK_BITS__TYPE = str
VOSPI_SPI_CLK_BITS__RAW = str
VOSPI_SEGM0_OK = int
VOSPI_SEGM0_OK__TYPE = str
VOSPI_SEGM0_OK__RAW = str
VOSPI_SEGM0_OK_BITS = int
VOSPI_SEGM0_OK_BITS__TYPE = str
VOSPI_SEGM0_OK_BITS__RAW = str
VOSPI_VSYNC = int
VOSPI_VSYNC__TYPE = str
VOSPI_VSYNC__RAW = str
VOSPI_VSYNC_BITS = int
VOSPI_VSYNC_BITS__TYPE = str
VOSPI_VSYNC_BITS__RAW = str
VOSPI_NORESYNC = int
VOSPI_NORESYNC__TYPE = str
VOSPI_NORESYNC__RAW = str
VOSPI_NORESYNC_BITS = int
VOSPI_NORESYNC_BITS__TYPE = str
VOSPI_NORESYNC_BITS__RAW = str
VOSPI_TELEMETRY = int
VOSPI_TELEMETRY__TYPE = str
VOSPI_TELEMETRY__RAW = str
VOSPI_TELEMETRY_BITS = int
VOSPI_TELEMETRY_BITS__TYPE = str
VOSPI_TELEMETRY_BITS__RAW = str
VOSPI_GPIO = int
VOSPI_GPIO__TYPE = str
VOSPI_GPIO__RAW = str
VOSPI_GPIO_BITS = int
VOSPI_GPIO_BITS__TYPE = str
VOSPI_GPIO_BITS__RAW = str
VOSPI_DBG_SRC = int
VOSPI_DBG_SRC__TYPE = str
VOSPI_DBG_SRC__RAW = str
VOSPI_DBG_SRC_BITS = int
VOSPI_DBG_SRC_BITS__TYPE = str
VOSPI_DBG_SRC_BITS__RAW = str
VOSPI_PACKET_WORDS = int
VOSPI_PACKET_WORDS__TYPE = str
VOSPI_PACKET_WORDS__RAW = str
VOSPI_NO_INVALID = int
VOSPI_NO_INVALID__TYPE = str
VOSPI_NO_INVALID__RAW = str
VOSPI_PACKETS_PER_LINE = int
VOSPI_PACKETS_PER_LINE__TYPE = str
VOSPI_PACKETS_PER_LINE__RAW = str
VOSPI_SEGMENT_FIRST = int
VOSPI_SEGMENT_FIRST__TYPE = str
VOSPI_SEGMENT_FIRST__RAW = str
VOSPI_SEGMENT_LAST = int
VOSPI_SEGMENT_LAST__TYPE = str
VOSPI_SEGMENT_LAST__RAW = str
VOSPI_PACKET_FIRST = int
VOSPI_PACKET_FIRST__TYPE = str
VOSPI_PACKET_FIRST__RAW = str
VOSPI_PACKET_LAST = int
VOSPI_PACKET_LAST__TYPE = str
VOSPI_PACKET_LAST__RAW = str
VOSPI_PACKET_TTT = int
VOSPI_PACKET_TTT__TYPE = str
VOSPI_PACKET_TTT__RAW = str
VOSPI_SOF_TO_HACT = int
VOSPI_SOF_TO_HACT__TYPE = str
VOSPI_SOF_TO_HACT__RAW = str
VOSPI_HACT_TO_HACT_EOF = int
VOSPI_HACT_TO_HACT_EOF__TYPE = str
VOSPI_HACT_TO_HACT_EOF__RAW = str
VOSPI_MCLK_HALFDIV = int
VOSPI_MCLK_HALFDIV__TYPE = str
VOSPI_MCLK_HALFDIV__RAW = str
VOSPI_MRST_MS = int
VOSPI_MRST_MS__TYPE = str
VOSPI_MRST_MS__RAW = str
VOSPI_MRST_AFTER_MS = int
VOSPI_MRST_AFTER_MS__TYPE = str
VOSPI_MRST_AFTER_MS__RAW = str
VOSPI_SPI_TIMEOUT_MS = int
VOSPI_SPI_TIMEOUT_MS__TYPE = str
VOSPI_SPI_TIMEOUT_MS__RAW = str
SENSOR_DATA_WIDTH = int
SENSOR_DATA_WIDTH__TYPE = str
SENSOR_DATA_WIDTH__RAW = str
SENSOR_FIFO_2DEPTH = int
SENSOR_FIFO_2DEPTH__TYPE = str
SENSOR_FIFO_2DEPTH__RAW = str
SENSOR_FIFO_DELAY = int
SENSOR_FIFO_DELAY__TYPE = str
SENSOR_FIFO_DELAY__RAW = str
HIST_SAXI_ADDR_MASK = int
HIST_SAXI_ADDR_MASK__TYPE = str
HIST_SAXI_ADDR_MASK__RAW = str
HIST_SAXI_MODE_WIDTH = int
HIST_SAXI_MODE_WIDTH__TYPE = str
HIST_SAXI_MODE_WIDTH__RAW = str
HIST_SAXI_EN = int
HIST_SAXI_EN__TYPE = str
HIST_SAXI_EN__RAW = str
HIST_SAXI_NRESET = int
HIST_SAXI_NRESET__TYPE = str
HIST_SAXI_NRESET__RAW = str
HIST_CONFIRM_WRITE = int
HIST_CONFIRM_WRITE__TYPE = str
HIST_CONFIRM_WRITE__RAW = str
HIST_SAXI_AWCACHE = int
HIST_SAXI_AWCACHE__TYPE = str
HIST_SAXI_AWCACHE__RAW = str
HIST_SAXI_MODE_ADDR_MASK = int
HIST_SAXI_MODE_ADDR_MASK__TYPE = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str
NUM_FRAME_BITS = int
NUM_FRAME_BITS__TYPE = str
NUM_FRAME_BITS__RAW = str
SENS_SYNC_FBITS = int
SENS_SYNC_FBITS__TYPE = str
SENS_SYNC_FBITS__RAW = str
SENS_SYNC_LBITS = int
SENS_SYNC_LBITS__TYPE = str
SENS_SYNC_LBITS__RAW = str
SENS_SYNC_LATE_DFLT = int
SENS_SYNC_LATE_DFLT__TYPE = str
SENS_SYNC_LATE_DFLT__RAW = str
SENS_SYNC_MINBITS = int
SENS_SYNC_MINBITS__TYPE = str
SENS_SYNC_MINBITS__RAW = str
SENS_SYNC_MINPER = int
SENS_SYNC_MINPER__TYPE = str
SENS_SYNC_MINPER__RAW = str
IDELAY_VALUE = int
IDELAY_VALUE__TYPE = str
IDELAY_VALUE__RAW = str
PXD_DRIVE = int
PXD_DRIVE__TYPE = str
PXD_DRIVE__RAW = str
PXD_IBUF_LOW_PWR = str
PXD_IBUF_LOW_PWR__TYPE = str
PXD_IBUF_LOW_PWR__RAW = str
PXD_SLEW = str
PXD_SLEW__TYPE = str
PXD_SLEW__RAW = str
VOSPI_DRIVE = int
VOSPI_DRIVE__TYPE = str
VOSPI_DRIVE__RAW = str
VOSPI_IBUF_LOW_PWR = str
VOSPI_IBUF_LOW_PWR__TYPE = str
VOSPI_IBUF_LOW_PWR__RAW = str
VOSPI_IOSTANDARD = str
VOSPI_IOSTANDARD__TYPE = str
VOSPI_IOSTANDARD__RAW = str
VOSPI_SLEW = str
VOSPI_SLEW__TYPE = str
VOSPI_SLEW__RAW = str
SENS_REFCLK_FREQUENCY = float
SENS_REFCLK_FREQUENCY__TYPE = str
SENS_REFCLK_FREQUENCY__RAW = str
SENS_HIGH_PERFORMANCE_MODE = str
SENS_HIGH_PERFORMANCE_MODE__TYPE = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
PXD_CAPACITANCE = str
PXD_CAPACITANCE__TYPE = str
PXD_CAPACITANCE__RAW = str
PXD_CLK_DIV = int
PXD_CLK_DIV__TYPE = str
PXD_CLK_DIV__RAW = str
PXD_CLK_DIV_BITS = int
PXD_CLK_DIV_BITS__TYPE = str
PXD_CLK_DIV_BITS__RAW = str
SENS_PHASE_WIDTH = int
SENS_PHASE_WIDTH__TYPE = str
SENS_PHASE_WIDTH__RAW = str
SENS_BANDWIDTH = str
SENS_BANDWIDTH__TYPE = str
SENS_BANDWIDTH__RAW = str
CLKIN_PERIOD_SENSOR = float
CLKIN_PERIOD_SENSOR__TYPE = str
CLKIN_PERIOD_SENSOR__RAW = str
CLKFBOUT_MULT_SENSOR = int
CLKFBOUT_MULT_SENSOR__TYPE = str
CLKFBOUT_MULT_SENSOR__RAW = str
CLKFBOUT_PHASE_SENSOR = float
CLKFBOUT_PHASE_SENSOR__TYPE = str
CLKFBOUT_PHASE_SENSOR__RAW = str
IPCLK_PHASE = float
IPCLK_PHASE__TYPE = str
IPCLK_PHASE__RAW = str
IPCLK2X_PHASE = float
IPCLK2X_PHASE__TYPE = str
IPCLK2X_PHASE__RAW = str
PXD_IOSTANDARD = str
PXD_IOSTANDARD__TYPE = str
PXD_IOSTANDARD__RAW = str
SENSI2C_IOSTANDARD = str
SENSI2C_IOSTANDARD__TYPE = str
SENSI2C_IOSTANDARD__RAW = str
HISPI_UNTUNED_SPLIT = str
HISPI_UNTUNED_SPLIT__TYPE = str
HISPI_UNTUNED_SPLIT__RAW = str
HISPI_DIFF_TERM = str
HISPI_DIFF_TERM__TYPE = str
HISPI_DIFF_TERM__RAW = str
HISPI_IOSTANDARD = str
HISPI_IOSTANDARD__TYPE = str
HISPI_IOSTANDARD__RAW = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS0__TYPE = str
BUF_IPCLK_SENS0__RAW = str
BUF_IPCLK2X_SENS0 = str
BUF_IPCLK2X_SENS0__TYPE = str
BUF_IPCLK2X_SENS0__RAW = str
BUF_IPCLK_SENS1 = str
BUF_IPCLK_SENS1__TYPE = str
BUF_IPCLK_SENS1__RAW = str
BUF_IPCLK2X_SENS1 = str
BUF_IPCLK2X_SENS1__TYPE = str
BUF_IPCLK2X_SENS1__RAW = str
BUF_IPCLK_SENS2 = str
BUF_IPCLK_SENS2__TYPE = str
BUF_IPCLK_SENS2__RAW = str
BUF_IPCLK2X_SENS2 = str
BUF_IPCLK2X_SENS2__TYPE = str
BUF_IPCLK2X_SENS2__RAW = str
BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS3__TYPE = str
BUF_IPCLK_SENS3__RAW = str
BUF_IPCLK2X_SENS3 = str
BUF_IPCLK2X_SENS3__TYPE = str
BUF_IPCLK2X_SENS3__RAW = str
SENS_DIVCLK_DIVIDE = int
SENS_DIVCLK_DIVIDE__TYPE = str
SENS_DIVCLK_DIVIDE__RAW = str
SENS_REF_JITTER1 = float
SENS_REF_JITTER1__TYPE = str
SENS_REF_JITTER1__RAW = str
SENS_REF_JITTER2 = float
SENS_REF_JITTER2__TYPE = str
SENS_REF_JITTER2__RAW = str
SENS_SS_EN = str
SENS_SS_EN__TYPE = str
SENS_SS_EN__RAW = str
SENS_SS_MODE = str
SENS_SS_MODE__TYPE = str
SENS_SS_MODE__RAW = str
SENS_SS_MOD_PERIOD = int
SENS_SS_MOD_PERIOD__TYPE = str
SENS_SS_MOD_PERIOD__RAW = str
HISPI_MSB_FIRST = int
HISPI_MSB_FIRST__TYPE = str
HISPI_MSB_FIRST__RAW = str
HISPI_NUMLANES = int
HISPI_NUMLANES__TYPE = str
HISPI_NUMLANES__RAW = str
HISPI_DELAY_CLK0 = str
HISPI_DELAY_CLK0__TYPE = str
HISPI_DELAY_CLK0__RAW = str
HISPI_DELAY_CLK1 = str
HISPI_DELAY_CLK1__TYPE = str
HISPI_DELAY_CLK1__RAW = str
HISPI_DELAY_CLK2 = str
HISPI_DELAY_CLK2__TYPE = str
HISPI_DELAY_CLK2__RAW = str
HISPI_DELAY_CLK3 = str
HISPI_DELAY_CLK3__TYPE = str
HISPI_DELAY_CLK3__RAW = str
HISPI_MMCM0 = str
HISPI_MMCM0__TYPE = str
HISPI_MMCM0__RAW = str
HISPI_MMCM1 = str
HISPI_MMCM1__TYPE = str
HISPI_MMCM1__RAW = str
HISPI_MMCM2 = str
HISPI_MMCM2__TYPE = str
HISPI_MMCM2__RAW = str
HISPI_MMCM3 = str
HISPI_MMCM3__TYPE = str
HISPI_MMCM3__RAW = str
HISPI_KEEP_IRST = int
HISPI_KEEP_IRST__TYPE = str
HISPI_KEEP_IRST__RAW = str
HISPI_WAIT_ALL_LANES = int
HISPI_WAIT_ALL_LANES__TYPE = str
HISPI_WAIT_ALL_LANES__RAW = str
HISPI_FIFO_DEPTH = int
HISPI_FIFO_DEPTH__TYPE = str
HISPI_FIFO_DEPTH__RAW = str
HISPI_FIFO_START = int
HISPI_FIFO_START__TYPE = str
HISPI_FIFO_START__RAW = str
HISPI_CAPACITANCE = str
HISPI_CAPACITANCE__TYPE = str
HISPI_CAPACITANCE__RAW = str
HISPI_DQS_BIAS = str
HISPI_DQS_BIAS__TYPE = str
HISPI_DQS_BIAS__RAW = str
HISPI_IBUF_DELAY_VALUE = str
HISPI_IBUF_DELAY_VALUE__TYPE = str
HISPI_IBUF_DELAY_VALUE__RAW = str
HISPI_IBUF_LOW_PWR = str
HISPI_IBUF_LOW_PWR__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str
HISPI_IFD_DELAY_VALUE = str
HISPI_IFD_DELAY_VALUE__TYPE = str
HISPI_IFD_DELAY_VALUE__RAW = str
CMPRS_NUM_AFI_CHN = int
CMPRS_NUM_AFI_CHN__TYPE = str
CMPRS_NUM_AFI_CHN__RAW = str
CMPRS_GROUP_ADDR = int
CMPRS_GROUP_ADDR__TYPE = str
CMPRS_GROUP_ADDR__RAW = str
CMPRS_BASE_INC = int
CMPRS_BASE_INC__TYPE = str
CMPRS_BASE_INC__RAW = str
CMPRS_AFIMUX_RADDR0 = int
CMPRS_AFIMUX_RADDR0__TYPE = str
CMPRS_AFIMUX_RADDR0__RAW = str
CMPRS_AFIMUX_RADDR1 = int
CMPRS_AFIMUX_RADDR1__TYPE = str
CMPRS_AFIMUX_RADDR1__RAW = str
CMPRS_AFIMUX_MASK = int
CMPRS_AFIMUX_MASK__TYPE = str
CMPRS_AFIMUX_MASK__RAW = str
CMPRS_STATUS_REG_BASE = int
CMPRS_STATUS_REG_BASE__TYPE = str
CMPRS_STATUS_REG_BASE__RAW = str
CMPRS_HIFREQ_REG_BASE = int
CMPRS_HIFREQ_REG_BASE__TYPE = str
CMPRS_HIFREQ_REG_BASE__RAW = str
CMPRS_AFIMUX_REG_ADDR0 = int
CMPRS_AFIMUX_REG_ADDR0__TYPE = str
CMPRS_AFIMUX_REG_ADDR0__RAW = str
CMPRS_AFIMUX_REG_ADDR1 = int
CMPRS_AFIMUX_REG_ADDR1__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str
CMPRS_STATUS_REG_INC = int
CMPRS_STATUS_REG_INC__TYPE = str
CMPRS_STATUS_REG_INC__RAW = str
CMPRS_HIFREQ_REG_INC = int
CMPRS_HIFREQ_REG_INC__TYPE = str
CMPRS_HIFREQ_REG_INC__RAW = str
CMPRS_MASK = int
CMPRS_MASK__TYPE = str
CMPRS_MASK__RAW = str
CMPRS_CONTROL_REG = int
CMPRS_CONTROL_REG__TYPE = str
CMPRS_CONTROL_REG__RAW = str
CMPRS_STATUS_CNTRL = int
CMPRS_STATUS_CNTRL__TYPE = str
CMPRS_STATUS_CNTRL__RAW = str
CMPRS_FORMAT = int
CMPRS_FORMAT__TYPE = str
CMPRS_FORMAT__RAW = str
CMPRS_COLOR_SATURATION = int
CMPRS_COLOR_SATURATION__TYPE = str
CMPRS_COLOR_SATURATION__RAW = str
CMPRS_CORING_MODE = int
CMPRS_CORING_MODE__TYPE = str
CMPRS_CORING_MODE__RAW = str
CMPRS_INTERRUPTS = int
CMPRS_INTERRUPTS__TYPE = str
CMPRS_INTERRUPTS__RAW = str
CMPRS_TABLES = int
CMPRS_TABLES__TYPE = str
CMPRS_TABLES__RAW = str
TABLE_QUANTIZATION_INDEX = int
TABLE_QUANTIZATION_INDEX__TYPE = str
TABLE_QUANTIZATION_INDEX__RAW = str
TABLE_CORING_INDEX = int
TABLE_CORING_INDEX__TYPE = str
TABLE_CORING_INDEX__RAW = str
TABLE_FOCUS_INDEX = int
TABLE_FOCUS_INDEX__TYPE = str
TABLE_FOCUS_INDEX__RAW = str
TABLE_HUFFMAN_INDEX = int
TABLE_HUFFMAN_INDEX__TYPE = str
TABLE_HUFFMAN_INDEX__RAW = str
CMPRS_CBIT_RUN = int
CMPRS_CBIT_RUN__TYPE = str
CMPRS_CBIT_RUN__RAW = str
CMPRS_CBIT_RUN_BITS = int
CMPRS_CBIT_RUN_BITS__TYPE = str
CMPRS_CBIT_RUN_BITS__RAW = str
CMPRS_CBIT_QBANK = int
CMPRS_CBIT_QBANK__TYPE = str
CMPRS_CBIT_QBANK__RAW = str
CMPRS_CBIT_QBANK_BITS = int
CMPRS_CBIT_QBANK_BITS__TYPE = str
CMPRS_CBIT_QBANK_BITS__RAW = str
CMPRS_CBIT_DCSUB = int
CMPRS_CBIT_DCSUB__TYPE = str
CMPRS_CBIT_DCSUB__RAW = str
CMPRS_CBIT_DCSUB_BITS = int
CMPRS_CBIT_DCSUB_BITS__TYPE = str
CMPRS_CBIT_DCSUB_BITS__RAW = str
CMPRS_CBIT_CMODE = int
CMPRS_CBIT_CMODE__TYPE = str
CMPRS_CBIT_CMODE__RAW = str
CMPRS_CBIT_CMODE_BITS = int
CMPRS_CBIT_CMODE_BITS__TYPE = str
CMPRS_CBIT_CMODE_BITS__RAW = str
CMPRS_CBIT_FRAMES = int
CMPRS_CBIT_FRAMES__TYPE = str
CMPRS_CBIT_FRAMES__RAW = str
CMPRS_CBIT_FRAMES_BITS = int
CMPRS_CBIT_FRAMES_BITS__TYPE = str
CMPRS_CBIT_FRAMES_BITS__RAW = str
CMPRS_CBIT_BE16 = int
CMPRS_CBIT_BE16__TYPE = str
CMPRS_CBIT_BE16__RAW = str
CMPRS_CBIT_BE16_BITS = int
CMPRS_CBIT_BE16_BITS__TYPE = str
CMPRS_CBIT_BE16_BITS__RAW = str
CMPRS_CBIT_BAYER = int
CMPRS_CBIT_BAYER__TYPE = str
CMPRS_CBIT_BAYER__RAW = str
CMPRS_CBIT_BAYER_BITS = int
CMPRS_CBIT_BAYER_BITS__TYPE = str
CMPRS_CBIT_BAYER_BITS__RAW = str
CMPRS_CBIT_FOCUS = int
CMPRS_CBIT_FOCUS__TYPE = str
CMPRS_CBIT_FOCUS__RAW = str
CMPRS_CBIT_FOCUS_BITS = int
CMPRS_CBIT_FOCUS_BITS__TYPE = str
CMPRS_CBIT_FOCUS_BITS__RAW = str
CMPRS_CBIT_ROWS_LSB = int
CMPRS_CBIT_ROWS_LSB__TYPE = str
CMPRS_CBIT_ROWS_LSB__RAW = str
CMPRS_CBIT_ROWS_LSB_BITS = int
CMPRS_CBIT_ROWS_LSB_BITS__TYPE = str
CMPRS_CBIT_ROWS_LSB_BITS__RAW = str
CMPRS_CBIT_RUN_RST = int
CMPRS_CBIT_RUN_RST__TYPE = str
CMPRS_CBIT_RUN_RST__RAW = str
CMPRS_CBIT_RUN_STANDALONE = int
CMPRS_CBIT_RUN_STANDALONE__TYPE = str
CMPRS_CBIT_RUN_STANDALONE__RAW = str
CMPRS_CBIT_RUN_ENABLE = int
CMPRS_CBIT_RUN_ENABLE__TYPE = str
CMPRS_CBIT_RUN_ENABLE__RAW = str
CMPRS_CBIT_CMODE_JPEG18 = int
CMPRS_CBIT_CMODE_JPEG18__TYPE = str
CMPRS_CBIT_CMODE_JPEG18__RAW = str
CMPRS_CBIT_CMODE_MONO6 = int
CMPRS_CBIT_CMODE_MONO6__TYPE = str
CMPRS_CBIT_CMODE_MONO6__RAW = str
CMPRS_CBIT_CMODE_JP46 = int
CMPRS_CBIT_CMODE_JP46__TYPE = str
CMPRS_CBIT_CMODE_JP46__RAW = str
CMPRS_CBIT_CMODE_JP46DC = int
CMPRS_CBIT_CMODE_JP46DC__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__RAW = str
CMPRS_CBIT_CMODE_JPEG20 = int
CMPRS_CBIT_CMODE_JPEG20__TYPE = str
CMPRS_CBIT_CMODE_JPEG20__RAW = str
CMPRS_CBIT_CMODE_JP4 = int
CMPRS_CBIT_CMODE_JP4__TYPE = str
CMPRS_CBIT_CMODE_JP4__RAW = str
CMPRS_CBIT_CMODE_JP4DC = int
CMPRS_CBIT_CMODE_JP4DC__TYPE = str
CMPRS_CBIT_CMODE_JP4DC__RAW = str
CMPRS_CBIT_CMODE_JP4DIFF = int
CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFF__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2 = int
CMPRS_CBIT_CMODE_JP4DIFFDIV2__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = int
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__RAW = str
CMPRS_CBIT_CMODE_MONO1 = int
CMPRS_CBIT_CMODE_MONO1__TYPE = str
CMPRS_CBIT_CMODE_MONO1__RAW = str
CMPRS_CBIT_CMODE_MONO4 = int
CMPRS_CBIT_CMODE_MONO4__TYPE = str
CMPRS_CBIT_CMODE_MONO4__RAW = str
CMPRS_CBIT_CMODE_RAW = int
CMPRS_CBIT_CMODE_RAW__TYPE = str
CMPRS_CBIT_CMODE_RAW__RAW = str
CMPRS_CBIT_FRAMES_SINGLE = int
CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
CMPRS_CBIT_FRAMES_SINGLE__RAW = str
CMPRS_COLOR18 = int
CMPRS_COLOR18__TYPE = str
CMPRS_COLOR18__RAW = str
CMPRS_COLOR20 = int
CMPRS_COLOR20__TYPE = str
CMPRS_COLOR20__RAW = str
CMPRS_MONO16 = int
CMPRS_MONO16__TYPE = str
CMPRS_MONO16__RAW = str
CMPRS_JP4 = int
CMPRS_JP4__TYPE = str
CMPRS_JP4__RAW = str
CMPRS_JP4DIFF = int
CMPRS_JP4DIFF__TYPE = str
CMPRS_JP4DIFF__RAW = str
CMPRS_RAW = int
CMPRS_RAW__TYPE = str
CMPRS_RAW__RAW = str
CMPRS_MONO8 = int
CMPRS_MONO8__TYPE = str
CMPRS_MONO8__RAW = str
CMPRS_FRMT_MBCM1 = int
CMPRS_FRMT_MBCM1__TYPE = str
CMPRS_FRMT_MBCM1__RAW = str
CMPRS_FRMT_MBCM1_BITS = int
CMPRS_FRMT_MBCM1_BITS__TYPE = str
CMPRS_FRMT_MBCM1_BITS__RAW = str
CMPRS_FRMT_MBRM1 = int
CMPRS_FRMT_MBRM1__TYPE = str
CMPRS_FRMT_MBRM1__RAW = str
CMPRS_FRMT_MBRM1_BITS = int
CMPRS_FRMT_MBRM1_BITS__TYPE = str
CMPRS_FRMT_MBRM1_BITS__RAW = str
CMPRS_FRMT_LMARG = int
CMPRS_FRMT_LMARG__TYPE = str
CMPRS_FRMT_LMARG__RAW = str
CMPRS_FRMT_LMARG_BITS = int
CMPRS_FRMT_LMARG_BITS__TYPE = str
CMPRS_FRMT_LMARG_BITS__RAW = str
CMPRS_CSAT_CB = int
CMPRS_CSAT_CB__TYPE = str
CMPRS_CSAT_CB__RAW = str
CMPRS_CSAT_CB_BITS = int
CMPRS_CSAT_CB_BITS__TYPE = str
CMPRS_CSAT_CB_BITS__RAW = str
CMPRS_CSAT_CR = int
CMPRS_CSAT_CR__TYPE = str
CMPRS_CSAT_CR__RAW = str
CMPRS_CSAT_CR_BITS = int
CMPRS_CSAT_CR_BITS__TYPE = str
CMPRS_CSAT_CR_BITS__RAW = str
CMPRS_CORING_BITS = int
CMPRS_CORING_BITS__TYPE = str
CMPRS_CORING_BITS__RAW = str
CMPRS_TIMEOUT_BITS = int
CMPRS_TIMEOUT_BITS__TYPE = str
CMPRS_TIMEOUT_BITS__RAW = str
CMPRS_TIMEOUT = int
CMPRS_TIMEOUT__TYPE = str
CMPRS_TIMEOUT__RAW = str
CMPRS_AFIMUX_EN = int
CMPRS_AFIMUX_EN__TYPE = str
CMPRS_AFIMUX_EN__RAW = str
CMPRS_AFIMUX_RST = int
CMPRS_AFIMUX_RST__TYPE = str
CMPRS_AFIMUX_RST__RAW = str
CMPRS_AFIMUX_MODE = int
CMPRS_AFIMUX_MODE__TYPE = str
CMPRS_AFIMUX_MODE__RAW = str
CMPRS_AFIMUX_STATUS_CNTRL = int
CMPRS_AFIMUX_STATUS_CNTRL__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
CMPRS_AFIMUX_SA_LEN = int
CMPRS_AFIMUX_SA_LEN__TYPE = str
CMPRS_AFIMUX_SA_LEN__RAW = str
CMPRS_AFIMUX_WIDTH = int
CMPRS_AFIMUX_WIDTH__TYPE = str
CMPRS_AFIMUX_WIDTH__RAW = str
CMPRS_AFIMUX_CYCBITS = int
CMPRS_AFIMUX_CYCBITS__TYPE = str
CMPRS_AFIMUX_CYCBITS__RAW = str
AFI_MUX_BUF_LATENCY = int
AFI_MUX_BUF_LATENCY__TYPE = str
AFI_MUX_BUF_LATENCY__RAW = str
GPIO_DRIVE = int
GPIO_DRIVE__TYPE = str
GPIO_DRIVE__RAW = str
GPIO_ADDR = int
GPIO_ADDR__TYPE = str
GPIO_ADDR__RAW = str
GPIO_MASK = int
GPIO_MASK__TYPE = str
GPIO_MASK__RAW = str
GPIO_STATUS_REG_ADDR = int
GPIO_STATUS_REG_ADDR__TYPE = str
GPIO_STATUS_REG_ADDR__RAW = str
GPIO_IBUF_LOW_PWR = str
GPIO_IBUF_LOW_PWR__TYPE = str
GPIO_IBUF_LOW_PWR__RAW = str
GPIO_IOSTANDARD = str
GPIO_IOSTANDARD__TYPE = str
GPIO_IOSTANDARD__RAW = str
GPIO_SLEW = str
GPIO_SLEW__TYPE = str
GPIO_SLEW__RAW = str
GPIO_SET_PINS = int
GPIO_SET_PINS__TYPE = str
GPIO_SET_PINS__RAW = str
GPIO_SET_STATUS = int
GPIO_SET_STATUS__TYPE = str
GPIO_SET_STATUS__RAW = str
GPIO_N = int
GPIO_N__TYPE = str
GPIO_N__RAW = str
GPIO_PORTEN = int
GPIO_PORTEN__TYPE = str
GPIO_PORTEN__RAW = str
RTC_ADDR = int
RTC_ADDR__TYPE = str
RTC_ADDR__RAW = str
CAMSYNC_ADDR = int
CAMSYNC_ADDR__TYPE = str
CAMSYNC_ADDR__RAW = str
RTC_STATUS_REG_ADDR = int
RTC_STATUS_REG_ADDR__TYPE = str
RTC_STATUS_REG_ADDR__RAW = str
RTC_SEC_USEC_ADDR = int
RTC_SEC_USEC_ADDR__TYPE = str
RTC_SEC_USEC_ADDR__RAW = str
RTC_MASK = int
RTC_MASK__TYPE = str
RTC_MASK__RAW = str
CAMSYNC_MASK = int
CAMSYNC_MASK__TYPE = str
CAMSYNC_MASK__RAW = str
CAMSYNC_MODE = int
CAMSYNC_MODE__TYPE = str
CAMSYNC_MODE__RAW = str
CAMSYNC_TRIG_SRC = int
CAMSYNC_TRIG_SRC__TYPE = str
CAMSYNC_TRIG_SRC__RAW = str
CAMSYNC_TRIG_DST = int
CAMSYNC_TRIG_DST__TYPE = str
CAMSYNC_TRIG_DST__RAW = str
CAMSYNC_TRIG_PERIOD = int
CAMSYNC_TRIG_PERIOD__TYPE = str
CAMSYNC_TRIG_PERIOD__RAW = str
CAMSYNC_TRIG_DELAY0 = int
CAMSYNC_TRIG_DELAY0__TYPE = str
CAMSYNC_TRIG_DELAY0__RAW = str
CAMSYNC_TRIG_DELAY1 = int
CAMSYNC_TRIG_DELAY1__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str
CAMSYNC_TRIG_DELAY2 = int
CAMSYNC_TRIG_DELAY2__TYPE = str
CAMSYNC_TRIG_DELAY2__RAW = str
CAMSYNC_TRIG_DELAY3 = int
CAMSYNC_TRIG_DELAY3__TYPE = str
CAMSYNC_TRIG_DELAY3__RAW = str
CAMSYNC_EN_BIT = int
CAMSYNC_EN_BIT__TYPE = str
CAMSYNC_EN_BIT__RAW = str
CAMSYNC_SNDEN_BIT = int
CAMSYNC_SNDEN_BIT__TYPE = str
CAMSYNC_SNDEN_BIT__RAW = str
CAMSYNC_EXTERNAL_BIT = int
CAMSYNC_EXTERNAL_BIT__TYPE = str
CAMSYNC_EXTERNAL_BIT__RAW = str
CAMSYNC_TRIGGERED_BIT = int
CAMSYNC_TRIGGERED_BIT__TYPE = str
CAMSYNC_TRIGGERED_BIT__RAW = str
CAMSYNC_MASTER_BIT = int
CAMSYNC_MASTER_BIT__TYPE = str
CAMSYNC_MASTER_BIT__RAW = str
CAMSYNC_CHN_EN_BIT = int
CAMSYNC_CHN_EN_BIT__TYPE = str
CAMSYNC_CHN_EN_BIT__RAW = str
CAMSYNC_PRE_MAGIC = int
CAMSYNC_PRE_MAGIC__TYPE = str
CAMSYNC_PRE_MAGIC__RAW = str
CAMSYNC_POST_MAGIC = int
CAMSYNC_POST_MAGIC__TYPE = str
CAMSYNC_POST_MAGIC__RAW = str
CAMSYNC_GPIO_EXT_IN = int
CAMSYNC_GPIO_EXT_IN__TYPE = str
CAMSYNC_GPIO_EXT_IN__RAW = str
CAMSYNC_GPIO_INT_IN = int
CAMSYNC_GPIO_INT_IN__TYPE = str
CAMSYNC_GPIO_INT_IN__RAW = str
CAMSYNC_GPIO_EXT_OUT = int
CAMSYNC_GPIO_EXT_OUT__TYPE = str
CAMSYNC_GPIO_EXT_OUT__RAW = str
CAMSYNC_GPIO_INT_OUT = int
CAMSYNC_GPIO_INT_OUT__TYPE = str
CAMSYNC_GPIO_INT_OUT__RAW = str
RTC_MHZ = int
RTC_MHZ__TYPE = str
RTC_MHZ__RAW = str
RTC_BITC_PREDIV = int
RTC_BITC_PREDIV__TYPE = str
RTC_BITC_PREDIV__RAW = str
RTC_SET_USEC = int
RTC_SET_USEC__TYPE = str
RTC_SET_USEC__RAW = str
RTC_SET_SEC = int
RTC_SET_SEC__TYPE = str
RTC_SET_SEC__RAW = str
RTC_SET_CORR = int
RTC_SET_CORR__TYPE = str
RTC_SET_CORR__RAW = str
RTC_SET_STATUS = int
RTC_SET_STATUS__TYPE = str
RTC_SET_STATUS__RAW = str
CMDFRAMESEQ_ADDR_BASE = int
CMDFRAMESEQ_ADDR_BASE__TYPE = str
CMDFRAMESEQ_ADDR_BASE__RAW = str
CMDFRAMESEQ_ADDR_INC = int
CMDFRAMESEQ_ADDR_INC__TYPE = str
CMDFRAMESEQ_ADDR_INC__RAW = str
CMDFRAMESEQ_MASK = int
CMDFRAMESEQ_MASK__TYPE = str
CMDFRAMESEQ_MASK__RAW = str
CMDFRAMESEQ_DEPTH = int
CMDFRAMESEQ_DEPTH__TYPE = str
CMDFRAMESEQ_DEPTH__RAW = str
CMDFRAMESEQ_ABS = int
CMDFRAMESEQ_ABS__TYPE = str
CMDFRAMESEQ_ABS__RAW = str
CMDFRAMESEQ_REL = int
CMDFRAMESEQ_REL__TYPE = str
CMDFRAMESEQ_REL__RAW = str
CMDFRAMESEQ_CTRL = int
CMDFRAMESEQ_CTRL__TYPE = str
CMDFRAMESEQ_CTRL__RAW = str
CMDFRAMESEQ_RST_BIT = int
CMDFRAMESEQ_RST_BIT__TYPE = str
CMDFRAMESEQ_RST_BIT__RAW = str
CMDFRAMESEQ_RUN_BIT = int
CMDFRAMESEQ_RUN_BIT__TYPE = str
CMDFRAMESEQ_RUN_BIT__RAW = str
CMDFRAMESEQ_IRQ_BIT = int
CMDFRAMESEQ_IRQ_BIT__TYPE = str
CMDFRAMESEQ_IRQ_BIT__RAW = str
CMDSEQMUX_ADDR = int
CMDSEQMUX_ADDR__TYPE = str
CMDSEQMUX_ADDR__RAW = str
CMDSEQMUX_MASK = int
CMDSEQMUX_MASK__TYPE = str
CMDSEQMUX_MASK__RAW = str
CMDSEQMUX_STATUS = int
CMDSEQMUX_STATUS__TYPE = str
CMDSEQMUX_STATUS__RAW = str
LOGGER_ADDR = int
LOGGER_ADDR__TYPE = str
LOGGER_ADDR__RAW = str
LOGGER_STATUS = int
LOGGER_STATUS__TYPE = str
LOGGER_STATUS__RAW = str
LOGGER_STATUS_REG_ADDR = int
LOGGER_STATUS_REG_ADDR__TYPE = str
LOGGER_STATUS_REG_ADDR__RAW = str
LOGGER_MASK = int
LOGGER_MASK__TYPE = str
LOGGER_MASK__RAW = str
LOGGER_STATUS_MASK = int
LOGGER_STATUS_MASK__TYPE = str
LOGGER_STATUS_MASK__RAW = str
LOGGER_PAGE_IMU = int
LOGGER_PAGE_IMU__TYPE = str
LOGGER_PAGE_IMU__RAW = str
LOGGER_PAGE_GPS = int
LOGGER_PAGE_GPS__TYPE = str
LOGGER_PAGE_GPS__RAW = str
LOGGER_PAGE_MSG = int
LOGGER_PAGE_MSG__TYPE = str
LOGGER_PAGE_MSG__RAW = str
LOGGER_PERIOD = int
LOGGER_PERIOD__TYPE = str
LOGGER_PERIOD__RAW = str
LOGGER_BIT_DURATION = int
LOGGER_BIT_DURATION__TYPE = str
LOGGER_BIT_DURATION__RAW = str
LOGGER_BIT_HALF_PERIOD = int
LOGGER_BIT_HALF_PERIOD__TYPE = str
LOGGER_BIT_HALF_PERIOD__RAW = str
LOGGER_CONFIG = int
LOGGER_CONFIG__TYPE = str
LOGGER_CONFIG__RAW = str
LOGGER_CONF_IMU = int
LOGGER_CONF_IMU__TYPE = str
LOGGER_CONF_IMU__RAW = str
LOGGER_CONF_IMU_BITS = int
LOGGER_CONF_IMU_BITS__TYPE = str
LOGGER_CONF_IMU_BITS__RAW = str
LOGGER_CONF_GPS = int
LOGGER_CONF_GPS__TYPE = str
LOGGER_CONF_GPS__RAW = str
LOGGER_CONF_GPS_BITS = int
LOGGER_CONF_GPS_BITS__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str
LOGGER_CONF_MSG = int
LOGGER_CONF_MSG__TYPE = str
LOGGER_CONF_MSG__RAW = str
LOGGER_CONF_MSG_BITS = int
LOGGER_CONF_MSG_BITS__TYPE = str
LOGGER_CONF_MSG_BITS__RAW = str
LOGGER_CONF_SYN = int
LOGGER_CONF_SYN__TYPE = str
LOGGER_CONF_SYN__RAW = str
LOGGER_CONF_SYN_BITS = int
LOGGER_CONF_SYN_BITS__TYPE = str
LOGGER_CONF_SYN_BITS__RAW = str
LOGGER_CONF_EN = int
LOGGER_CONF_EN__TYPE = str
LOGGER_CONF_EN__RAW = str
LOGGER_CONF_EN_BITS = int
LOGGER_CONF_EN_BITS__TYPE = str
LOGGER_CONF_EN_BITS__RAW = str
LOGGER_CONF_DBG = int
LOGGER_CONF_DBG__TYPE = str
LOGGER_CONF_DBG__RAW = str
LOGGER_CONF_DBG_BITS = int
LOGGER_CONF_DBG_BITS__TYPE = str
LOGGER_CONF_DBG_BITS__RAW = str
MULT_SAXI_HALF_BRAM_IN = int
MULT_SAXI_HALF_BRAM_IN__TYPE = str
MULT_SAXI_HALF_BRAM_IN__RAW = str
MULT_SAXI_WLOG = int
MULT_SAXI_WLOG__TYPE = str
MULT_SAXI_WLOG__RAW = str
MULT_SAXI_ADDR = int
MULT_SAXI_ADDR__TYPE = str
MULT_SAXI_ADDR__RAW = str
MULT_SAXI_IRQLEN_ADDR = int
MULT_SAXI_IRQLEN_ADDR__TYPE = str
MULT_SAXI_IRQLEN_ADDR__RAW = str
MULT_SAXI_CNTRL_ADDR = int
MULT_SAXI_CNTRL_ADDR__TYPE = str
MULT_SAXI_CNTRL_ADDR__RAW = str
MULT_SAXI_CNTRL_MODE = int
MULT_SAXI_CNTRL_MODE__TYPE = str
MULT_SAXI_CNTRL_MODE__RAW = str
MULT_SAXI_CNTRL_STATUS = int
MULT_SAXI_CNTRL_STATUS__TYPE = str
MULT_SAXI_CNTRL_STATUS__RAW = str
MULT_SAXI_CNTRL_IRQ = int
MULT_SAXI_CNTRL_IRQ__TYPE = str
MULT_SAXI_CNTRL_IRQ__RAW = str
MULT_SAXI_POINTERS_REG = int
MULT_SAXI_POINTERS_REG__TYPE = str
MULT_SAXI_POINTERS_REG__RAW = str
MULT_SAXI_STATUS_REG = int
MULT_SAXI_STATUS_REG__TYPE = str
MULT_SAXI_STATUS_REG__RAW = str
MULT_SAXI_HALF_BRAM = int
MULT_SAXI_HALF_BRAM__TYPE = str
MULT_SAXI_HALF_BRAM__RAW = str
MULT_SAXI_BSLOG0 = int
MULT_SAXI_BSLOG0__TYPE = str
MULT_SAXI_BSLOG0__RAW = str
MULT_SAXI_BSLOG1 = int
MULT_SAXI_BSLOG1__TYPE = str
MULT_SAXI_BSLOG1__RAW = str
MULT_SAXI_BSLOG2 = int
MULT_SAXI_BSLOG2__TYPE = str
MULT_SAXI_BSLOG2__RAW = str
MULT_SAXI_BSLOG3 = int
MULT_SAXI_BSLOG3__TYPE = str
MULT_SAXI_BSLOG3__RAW = str
MULT_SAXI_MASK = int
MULT_SAXI_MASK__TYPE = str
MULT_SAXI_MASK__RAW = str
MULT_SAXI_IRQLEN_MASK = int
MULT_SAXI_IRQLEN_MASK__TYPE = str
MULT_SAXI_IRQLEN_MASK__RAW = str
MULT_SAXI_CNTRL_MASK = int
MULT_SAXI_CNTRL_MASK__TYPE = str
MULT_SAXI_CNTRL_MASK__RAW = str
MULT_SAXI_AWCACHE = int
MULT_SAXI_AWCACHE__TYPE = str
MULT_SAXI_AWCACHE__RAW = str
MULT_SAXI_ADV_WR = int
MULT_SAXI_ADV_WR__TYPE = str
MULT_SAXI_ADV_WR__RAW = str
MULT_SAXI_ADV_RD = int
MULT_SAXI_ADV_RD__TYPE = str
MULT_SAXI_ADV_RD__RAW = str
CLK_ADDR = int
CLK_ADDR__TYPE = str
CLK_ADDR__RAW = str
CLK_MASK = int
CLK_MASK__TYPE = str
CLK_MASK__RAW = str
CLK_STATUS_REG_ADDR = int
CLK_STATUS_REG_ADDR__TYPE = str
CLK_STATUS_REG_ADDR__RAW = str
CLK_CNTRL = int
CLK_CNTRL__TYPE = str
CLK_CNTRL__RAW = str
CLK_STATUS = int
CLK_STATUS__TYPE = str
CLK_STATUS__RAW = str
DEBUG_ADDR = int
DEBUG_ADDR__TYPE = str
DEBUG_ADDR__RAW = str
DEBUG_MASK = int
DEBUG_MASK__TYPE = str
DEBUG_MASK__RAW = str
DEBUG_STATUS_REG_ADDR = int
DEBUG_STATUS_REG_ADDR__TYPE = str
DEBUG_STATUS_REG_ADDR__RAW = str
DEBUG_READ_REG_ADDR = int
DEBUG_READ_REG_ADDR__TYPE = str
DEBUG_READ_REG_ADDR__RAW = str
DEBUG_SHIFT_DATA = int
DEBUG_SHIFT_DATA__TYPE = str
DEBUG_SHIFT_DATA__RAW = str
DEBUG_LOAD = int
DEBUG_LOAD__TYPE = str
DEBUG_LOAD__RAW = str
DEBUG_SET_STATUS = int
DEBUG_SET_STATUS__TYPE = str
DEBUG_SET_STATUS__RAW = str
DEBUG_CMD_LATENCY = int
DEBUG_CMD_LATENCY__TYPE = str
DEBUG_CMD_LATENCY__RAW = str
MULTICLK_IN_PERIOD = int
MULTICLK_IN_PERIOD__TYPE = str
MULTICLK_IN_PERIOD__RAW = str
MULTICLK_DIVCLK = int
MULTICLK_DIVCLK__TYPE = str
MULTICLK_DIVCLK__RAW = str
MULTICLK_MULT = int
MULTICLK_MULT__TYPE = str
MULTICLK_MULT__RAW = str
MULTICLK_DIV_DLYREF = int
MULTICLK_DIV_DLYREF__TYPE = str
MULTICLK_DIV_DLYREF__RAW = str
MULTICLK_DIV_AXIHP = int
MULTICLK_DIV_AXIHP__TYPE = str
MULTICLK_DIV_AXIHP__RAW = str
MULTICLK_DIV_XCLK = int
MULTICLK_DIV_XCLK__TYPE = str
MULTICLK_DIV_XCLK__RAW = str
MULTICLK_DIV_XCLK2X = int
MULTICLK_DIV_XCLK2X__TYPE = str
MULTICLK_DIV_XCLK2X__RAW = str
MULTICLK_DIV_SYNC = int
MULTICLK_DIV_SYNC__TYPE = str
MULTICLK_DIV_SYNC__RAW = str
MULTICLK_PHASE_FB = float
MULTICLK_PHASE_FB__TYPE = str
MULTICLK_PHASE_FB__RAW = str
MULTICLK_PHASE_DLYREF = float
MULTICLK_PHASE_DLYREF__TYPE = str
MULTICLK_PHASE_DLYREF__RAW = str
MULTICLK_BUF_DLYREF = str
MULTICLK_BUF_DLYREF__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
MULTICLK_PHASE_AXIHP = float
MULTICLK_PHASE_AXIHP__TYPE = str
MULTICLK_PHASE_AXIHP__RAW = str
MULTICLK_BUF_AXIHP = str
MULTICLK_BUF_AXIHP__TYPE = str
MULTICLK_BUF_AXIHP__RAW = str
MULTICLK_PHASE_XCLK = float
MULTICLK_PHASE_XCLK__TYPE = str
MULTICLK_PHASE_XCLK__RAW = str
MULTICLK_BUF_XCLK = str
MULTICLK_BUF_XCLK__TYPE = str
MULTICLK_BUF_XCLK__RAW = str
MULTICLK_PHASE_SYNC = float
MULTICLK_PHASE_SYNC__TYPE = str
MULTICLK_PHASE_SYNC__RAW = str
MULTICLK_BUF_SYNC = str
MULTICLK_BUF_SYNC__TYPE = str
MULTICLK_BUF_SYNC__RAW = str
CLKIN_PERIOD_PCLK = int
CLKIN_PERIOD_PCLK__TYPE = str
CLKIN_PERIOD_PCLK__RAW = str
DIVCLK_DIVIDE_PCLK = int
DIVCLK_DIVIDE_PCLK__TYPE = str
DIVCLK_DIVIDE_PCLK__RAW = str
CLKFBOUT_MULT_PCLK = int
CLKFBOUT_MULT_PCLK__TYPE = str
CLKFBOUT_MULT_PCLK__RAW = str
CLKOUT_DIV_PCLK = int
CLKOUT_DIV_PCLK__TYPE = str
CLKOUT_DIV_PCLK__RAW = str
CLKOUT_DIV_PCLK2X = int
CLKOUT_DIV_PCLK2X__TYPE = str
CLKOUT_DIV_PCLK2X__RAW = str
PHASE_CLK2X_PCLK = float
PHASE_CLK2X_PCLK__TYPE = str
PHASE_CLK2X_PCLK__RAW = str
BUF_CLK1X_PCLK = str
BUF_CLK1X_PCLK__TYPE = str
BUF_CLK1X_PCLK__RAW = str
BUF_CLK1X_PCLK2X = str
BUF_CLK1X_PCLK2X__TYPE = str
BUF_CLK1X_PCLK2X__RAW = str
MEMCLK_CAPACITANCE = str
MEMCLK_CAPACITANCE__TYPE = str
MEMCLK_CAPACITANCE__RAW = str
MEMCLK_IBUF_LOW_PWR = str
MEMCLK_IBUF_LOW_PWR__TYPE = str
MEMCLK_IBUF_LOW_PWR__RAW = str
MEMCLK_IOSTANDARD = str
MEMCLK_IOSTANDARD__TYPE = str
MEMCLK_IOSTANDARD__RAW = str
FFCLK0_CAPACITANCE = str
FFCLK0_CAPACITANCE__TYPE = str
FFCLK0_CAPACITANCE__RAW = str
FFCLK0_DIFF_TERM = str
FFCLK0_DIFF_TERM__TYPE = str
FFCLK0_DIFF_TERM__RAW = str
FFCLK0_IBUF_LOW_PWR = str
FFCLK0_IBUF_LOW_PWR__TYPE = str
FFCLK0_IBUF_LOW_PWR__RAW = str
FFCLK0_IOSTANDARD = str
FFCLK0_IOSTANDARD__TYPE = str
FFCLK0_IOSTANDARD__RAW = str
FFCLK1_CAPACITANCE = str
FFCLK1_CAPACITANCE__TYPE = str
FFCLK1_CAPACITANCE__RAW = str
FFCLK1_DIFF_TERM = str
FFCLK1_DIFF_TERM__TYPE = str
FFCLK1_DIFF_TERM__RAW = str
FFCLK1_IBUF_LOW_PWR = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
FFCLK1_IBUF_LOW_PWR__RAW = str
FFCLK1_IOSTANDARD = str
FFCLK1_IOSTANDARD__TYPE = str
FFCLK1_IOSTANDARD__RAW = str
DLY_LANE0_ODELAY = int
DLY_LANE0_ODELAY__TYPE = str
DLY_LANE0_ODELAY__RAW = str
DLY_LANE0_IDELAY = int
DLY_LANE0_IDELAY__TYPE = str
DLY_LANE0_IDELAY__RAW = str
DLY_LANE1_ODELAY = int
DLY_LANE1_ODELAY__TYPE = str
DLY_LANE1_ODELAY__RAW = str
DLY_LANE1_IDELAY = int
DLY_LANE1_IDELAY__TYPE = str
DLY_LANE1_IDELAY__RAW = str
DLY_CMDA = int
DLY_CMDA__TYPE = str
DLY_CMDA__RAW = str
DLY_PHASE = int
DLY_PHASE__TYPE = str
DLY_PHASE__RAW = str
DEFAULT_STATUS_MODE = int
DEFAULT_STATUS_MODE__TYPE = str
DEFAULT_STATUS_MODE__RAW = str
LD_DLY_LANE0_ODELAY = int
LD_DLY_LANE0_ODELAY__TYPE = str
LD_DLY_LANE0_ODELAY__RAW = str
LD_DLY_LANE0_IDELAY = int
LD_DLY_LANE0_IDELAY__TYPE = str
LD_DLY_LANE0_IDELAY__RAW = str
LD_DLY_LANE1_ODELAY = int
LD_DLY_LANE1_ODELAY__TYPE = str
LD_DLY_LANE1_ODELAY__RAW = str
LD_DLY_LANE1_IDELAY = int
LD_DLY_LANE1_IDELAY__TYPE = str
LD_DLY_LANE1_IDELAY__RAW = str
LD_DLY_CMDA = int
LD_DLY_CMDA__TYPE = str
LD_DLY_CMDA__RAW = str
LD_DLY_PHASE = int
LD_DLY_PHASE__TYPE = str
LD_DLY_PHASE__RAW = str
DLY_SET = int
DLY_SET__TYPE = str
DLY_SET__RAW = str
T_RFC = int
T_RFC__TYPE = str
T_RFC__RAW = str
T_REFI = int
T_REFI__TYPE = str
T_REFI__RAW = str
DLY_DQ_IDELAY = int
DLY_DQ_IDELAY__TYPE = str
DLY_DQ_IDELAY__RAW = str
DLY_DQ_ODELAY = int
DLY_DQ_ODELAY__TYPE = str
DLY_DQ_ODELAY__RAW = str
DLY_DQS_IDELAY = int
DLY_DQS_IDELAY__TYPE = str
DLY_DQS_IDELAY__RAW = str
DLY_DQS_ODELAY = int
DLY_DQS_ODELAY__TYPE = str
DLY_DQS_ODELAY__RAW = str
DLY_DM_ODELAY = int
DLY_DM_ODELAY__TYPE = str
DLY_DM_ODELAY__RAW = str
DLY_CMDA_ODELAY = int
DLY_CMDA_ODELAY__TYPE = str
DLY_CMDA_ODELAY__RAW = str
DLY_LANE0_DQS_WLV_IDELAY = int
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY__RAW = str
DLY_LANE1_DQS_WLV_IDELAY = int
DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
DLY_LANE1_DQS_WLV_IDELAY__RAW = str
DQSTRI_FIRST = int
DQSTRI_FIRST__TYPE = str
DQSTRI_FIRST__RAW = str
DQSTRI_LAST = int
DQSTRI_LAST__TYPE = str
DQSTRI_LAST__RAW = str
DQTRI_FIRST = int
DQTRI_FIRST__TYPE = str
DQTRI_FIRST__RAW = str
DQTRI_LAST = int
DQTRI_LAST__TYPE = str
DQTRI_LAST__RAW = str
WBUF_DLY_DFLT = int
WBUF_DLY_DFLT__TYPE = str
WBUF_DLY_DFLT__RAW = str
WBUF_DLY_WLV = int
WBUF_DLY_WLV__TYPE = str
WBUF_DLY_WLV__RAW = str
INITIALIZE_OFFSET = int
INITIALIZE_OFFSET__TYPE = str
INITIALIZE_OFFSET__RAW = str
REFRESH_OFFSET = int
REFRESH_OFFSET__TYPE = str
REFRESH_OFFSET__RAW = str
WRITELEV_OFFSET = int
WRITELEV_OFFSET__TYPE = str
WRITELEV_OFFSET__RAW = str
READ_PATTERN_OFFSET = int
READ_PATTERN_OFFSET__TYPE = str
READ_PATTERN_OFFSET__RAW = str
WRITE_BLOCK_OFFSET = int
WRITE_BLOCK_OFFSET__TYPE = str
WRITE_BLOCK_OFFSET__RAW = str
READ_BLOCK_OFFSET = int
READ_BLOCK_OFFSET__TYPE = str
READ_BLOCK_OFFSET__RAW = str
STATUS_SEQ_SHFT = int
STATUS_SEQ_SHFT__TYPE = str
STATUS_SEQ_SHFT__RAW = str
STATUS_2LSB_SHFT = int
STATUS_2LSB_SHFT__TYPE = str
STATUS_2LSB_SHFT__RAW = str
STATUS_MSB_RSHFT = int
STATUS_MSB_RSHFT__TYPE = str
STATUS_MSB_RSHFT__RAW = str
STATUS_PSHIFTER_RDY_MASK = int
STATUS_PSHIFTER_RDY_MASK__TYPE = str
STATUS_PSHIFTER_RDY_MASK__RAW = str
FRAME_START_ADDRESS = int
FRAME_START_ADDRESS__TYPE = str
FRAME_START_ADDRESS__RAW = str
FRAME_START_ADDRESS_INC = int
FRAME_START_ADDRESS_INC__TYPE = str
FRAME_START_ADDRESS_INC__RAW = str
LAST_BUF_FRAME = int
LAST_BUF_FRAME__TYPE = str
LAST_BUF_FRAME__RAW = str
CAMSYNC_DELAY = int
CAMSYNC_DELAY__TYPE = str
CAMSYNC_DELAY__RAW = str
FRAME_FULL_WIDTH = int
FRAME_FULL_WIDTH__TYPE = str
FRAME_FULL_WIDTH__RAW = str
AFI_LO_ADDR64 = int
AFI_LO_ADDR64__TYPE = str
AFI_LO_ADDR64__RAW = str
AFI_SIZE64 = int
AFI_SIZE64__TYPE = str
AFI_SIZE64__RAW = str
WINDOW_WIDTH = int
WINDOW_WIDTH__TYPE = str
WINDOW_WIDTH__RAW = str
WINDOW_HEIGHT = int
WINDOW_HEIGHT__TYPE = str
WINDOW_HEIGHT__RAW = str
WINDOW_X0 = int
WINDOW_X0__TYPE = str
WINDOW_X0__RAW = str
WINDOW_Y0 = int
WINDOW_Y0__TYPE = str
WINDOW_Y0__RAW = str
SCANLINE_STARTX = int
SCANLINE_STARTX__TYPE = str
SCANLINE_STARTX__RAW = str
SCANLINE_STARTY = int
SCANLINE_STARTY__TYPE = str
SCANLINE_STARTY__RAW = str
SCANLINE_EXTRA_PAGES = int
SCANLINE_EXTRA_PAGES__TYPE = str
SCANLINE_EXTRA_PAGES__RAW = str
TILED_STARTX = int
TILED_STARTX__TYPE = str
TILED_STARTX__RAW = str
TILED_STARTY = int
TILED_STARTY__TYPE = str
TILED_STARTY__RAW = str
TILED_EXTRA_PAGES = int
TILED_EXTRA_PAGES__TYPE = str
TILED_EXTRA_PAGES__RAW = str
TILED_KEEP_OPEN = int
TILED_KEEP_OPEN__TYPE = str
TILED_KEEP_OPEN__RAW = str
TILE_WIDTH = int
TILE_WIDTH__TYPE = str
TILE_WIDTH__RAW = str
TILE_HEIGHT = int
TILE_HEIGHT__TYPE = str
TILE_HEIGHT__RAW = str
TILE_VSTEP = int
TILE_VSTEP__TYPE = str
TILE_VSTEP__RAW = str
TEST01_START_FRAME = int
TEST01_START_FRAME__TYPE = str
TEST01_START_FRAME__RAW = str
TEST01_NEXT_PAGE = int
TEST01_NEXT_PAGE__TYPE = str
TEST01_NEXT_PAGE__RAW = str
TEST01_SUSPEND = int
TEST01_SUSPEND__TYPE = str
TEST01_SUSPEND__RAW = str
TEST_INITIAL_BURST = int
TEST_INITIAL_BURST__TYPE = str
TEST_INITIAL_BURST__RAW = str
NUM_INTERRUPTS = int
NUM_INTERRUPTS__TYPE = str
NUM_INTERRUPTS__RAW = str
AXI_RDADDR_LATENCY = int
AXI_RDADDR_LATENCY__TYPE = str
AXI_RDADDR_LATENCY__RAW = str
AXI_WRADDR_LATENCY = int
AXI_WRADDR_LATENCY__TYPE = str
AXI_WRADDR_LATENCY__RAW = str
AXI_WRDATA_LATENCY = int
AXI_WRDATA_LATENCY__TYPE = str
AXI_WRDATA_LATENCY__RAW = str
AXI_TASK_HOLD = float
AXI_TASK_HOLD__TYPE = str
AXI_TASK_HOLD__RAW = str
SIMUL_AXI_READ_WIDTH = int
SIMUL_AXI_READ_WIDTH__TYPE = str
SIMUL_AXI_READ_WIDTH__RAW = str
MEMCLK_PERIOD = float
MEMCLK_PERIOD__TYPE = str
MEMCLK_PERIOD__RAW = str
FCLK0_PERIOD = float
FCLK0_PERIOD__TYPE = str
FCLK0_PERIOD__RAW = str
FCLK1_PERIOD = float
FCLK1_PERIOD__TYPE = str
FCLK1_PERIOD__RAW = str
LWIR_DATA_FILE1 = str
LWIR_DATA_FILE1__TYPE = str
LWIR_DATA_FILE1__RAW = str
LWIR_DATA_FILE2 = str
LWIR_DATA_FILE2__TYPE = str
LWIR_DATA_FILE2__RAW = str
LWIR_DATA_FILE3 = str
LWIR_DATA_FILE3__TYPE = str
LWIR_DATA_FILE3__RAW = str
LWIR_DATA_FILE4 = str
LWIR_DATA_FILE4__TYPE = str
LWIR_DATA_FILE4__RAW = str
LWIR_WINDOW_WIDTH = int
LWIR_WINDOW_WIDTH__TYPE = str
LWIR_WINDOW_WIDTH__RAW = str
LWIR_WINDOW_HEIGHT = int
LWIR_WINDOW_HEIGHT__TYPE = str
LWIR_WINDOW_HEIGHT__RAW = str
LWIR_TELEMETRY = int
LWIR_TELEMETRY__TYPE = str
LWIR_TELEMETRY__RAW = str
LWIR_FRAME_PERIOD = int
LWIR_FRAME_PERIOD__TYPE = str
LWIR_FRAME_PERIOD__RAW = str
LWIR_FRAME_DELAY = int
LWIR_FRAME_DELAY__TYPE = str
LWIR_FRAME_DELAY__RAW = str
LWIR_MS_PERIOD = int
LWIR_MS_PERIOD__TYPE = str
LWIR_MS_PERIOD__RAW = str
LWIR_TELEMETRY_REV = int
LWIR_TELEMETRY_REV__TYPE = str
LWIR_TELEMETRY_REV__RAW = str
LWIR_TELEMETRY_STATUS = int
LWIR_TELEMETRY_STATUS__TYPE = str
LWIR_TELEMETRY_STATUS__RAW = str
LWIR_TELEMETRY_SREV = int
LWIR_TELEMETRY_SREV__TYPE = str
LWIR_TELEMETRY_SREV__RAW = str
LWIR_TELEMETRY_TEMP_COUTS = int
LWIR_TELEMETRY_TEMP_COUTS__TYPE = str
LWIR_TELEMETRY_TEMP_COUTS__RAW = str
LWIR_TELEMETRY_TEMP_KELVIN = int
LWIR_TELEMETRY_TEMP_KELVIN__TYPE = str
LWIR_TELEMETRY_TEMP_KELVIN__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN = int
LWIR_TELEMETRY_TEMP_LAST_KELVIN__TYPE = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN__RAW = str
LWIR_TELEMETRY_TIME_LAST_MS = int
LWIR_TELEMETRY_TIME_LAST_MS__TYPE = str
LWIR_TELEMETRY_TIME_LAST_MS__RAW = str
LWIR_TELEMETRY_AGC_ROI_TOP = int
LWIR_TELEMETRY_AGC_ROI_TOP__TYPE = str
LWIR_TELEMETRY_AGC_ROI_TOP__RAW = str
LWIR_TELEMETRY_AGC_ROI_LEFT = int
LWIR_TELEMETRY_AGC_ROI_LEFT__TYPE = str
LWIR_TELEMETRY_AGC_ROI_LEFT__RAW = str
LWIR_TELEMETRY_AGC_ROI_BOTTOM = int
LWIR_TELEMETRY_AGC_ROI_BOTTOM__TYPE = str
LWIR_TELEMETRY_AGC_ROI_BOTTOM__RAW = str
LWIR_TELEMETRY_AGC_ROI_RIGHT = int
LWIR_TELEMETRY_AGC_ROI_RIGHT__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__RAW = str
LWIR_TELEMETRY_AGC_HIGH = int
LWIR_TELEMETRY_AGC_HIGH__TYPE = str
LWIR_TELEMETRY_AGC_HIGH__RAW = str
LWIR_TELEMETRY_AGC_LOW = int
LWIR_TELEMETRY_AGC_LOW__TYPE = str
LWIR_TELEMETRY_AGC_LOW__RAW = str
LWIR_TELEMETRY_VIDEO_FORMAT = int
LWIR_TELEMETRY_VIDEO_FORMAT__TYPE = str
LWIR_TELEMETRY_VIDEO_FORMAT__RAW = str
LWIR_GPIO_IN = int
LWIR_GPIO_IN__TYPE = str
LWIR_GPIO_IN__RAW = str
SENSOR_IMAGE_TYPE0 = str
SENSOR_IMAGE_TYPE0__TYPE = str
SENSOR_IMAGE_TYPE0__RAW = str
SENSOR_IMAGE_TYPE1 = str
SENSOR_IMAGE_TYPE1__TYPE = str
SENSOR_IMAGE_TYPE1__RAW = str
SENSOR_IMAGE_TYPE2 = str
SENSOR_IMAGE_TYPE2__TYPE = str
SENSOR_IMAGE_TYPE2__RAW = str
SENSOR_IMAGE_TYPE3 = str
SENSOR_IMAGE_TYPE3__TYPE = str
SENSOR_IMAGE_TYPE3__RAW = str
SIMULATE_CMPRS_CMODE0 = int
SIMULATE_CMPRS_CMODE0__TYPE = str
SIMULATE_CMPRS_CMODE0__RAW = str
SIMULATE_CMPRS_CMODE1 = int
SIMULATE_CMPRS_CMODE1__TYPE = str
SIMULATE_CMPRS_CMODE1__RAW = str
SIMULATE_CMPRS_CMODE2 = int
SIMULATE_CMPRS_CMODE2__TYPE = str
SIMULATE_CMPRS_CMODE2__RAW = str
SIMULATE_CMPRS_CMODE3 = int
SIMULATE_CMPRS_CMODE3__TYPE = str
SIMULATE_CMPRS_CMODE3__RAW = str
SENSOR12BITS_NGPL = int
SENSOR12BITS_NGPL__TYPE = str
SENSOR12BITS_NGPL__RAW = str
SENSOR12BITS_NVLO = int
SENSOR12BITS_NVLO__TYPE = str
SENSOR12BITS_NVLO__RAW = str
SENSOR12BITS_TMD = int
SENSOR12BITS_TMD__TYPE = str
SENSOR12BITS_TMD__RAW = str
SENSOR12BITS_TDDO = int
SENSOR12BITS_TDDO__TYPE = str
SENSOR12BITS_TDDO__RAW = str
SENSOR12BITS_TDDO1 = int
SENSOR12BITS_TDDO1__TYPE = str
SENSOR12BITS_TDDO1__RAW = str
HISTOGRAM_LEFT = int
HISTOGRAM_LEFT__TYPE = str
HISTOGRAM_LEFT__RAW = str
HISTOGRAM_TOP = int
HISTOGRAM_TOP__TYPE = str
HISTOGRAM_TOP__RAW = str
HISTOGRAM_WIDTH = int
HISTOGRAM_WIDTH__TYPE = str
HISTOGRAM_WIDTH__RAW = str
HISTOGRAM_HEIGHT = int
HISTOGRAM_HEIGHT__TYPE = str
HISTOGRAM_HEIGHT__RAW = str
HISTOGRAM_START_PAGE = int
HISTOGRAM_START_PAGE__TYPE = str
HISTOGRAM_START_PAGE__RAW = str
FRAME_WIDTH_ROUND_BITS = int
FRAME_WIDTH_ROUND_BITS__TYPE = str
FRAME_WIDTH_ROUND_BITS__RAW = str
WOI_WIDTH = int
WOI_WIDTH__TYPE = str
WOI_WIDTH__RAW = str
WOI_HEIGHT = int
WOI_HEIGHT__TYPE = str
WOI_HEIGHT__RAW = str
QUADRANTS_PXD_HACT_VACT = int
QUADRANTS_PXD_HACT_VACT__TYPE = str
QUADRANTS_PXD_HACT_VACT__RAW = str
SENSOR_PRIORITY = int
SENSOR_PRIORITY__TYPE = str
SENSOR_PRIORITY__RAW = str
py393/vrlg_orig.py 0 → 100644
View file @ 043d4849
from __future__ import print_function
from __future__ import division
'''
# Copyright (C) 2015, Elphel.inc.
# Module to keep globals (Verilog parameters) accessible for all modules
# that import (not import from) this one
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
DEFAULTS={}
dqs_dqm_patt=None
def init_vars(d):
global DEFAULTS
if d:
globals().update(d)
for k,v in d.items():
DEFAULTS[k]=v
def set_name_field(vname,
fieldIndex,
value):
"""
Set specified byte in the parameter
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
<value> value to set the specified byte to
"""
v=globals()[vname]
mask = 0xff << (8*fieldIndex)
val = value << (8*fieldIndex)
v = ((v ^ val) & mask) ^ v
globals()[vname]=v
def get_name_field(vname,
fieldIndex):
"""
Get specified byte in the parameter
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
Return specified byte
"""
# print ("value for %s is %s"%(vname,str(globals()[vname])))
# print ("dflt for %s is %s"%(vname,str(DEFAULTS[vname])))
# print ("value[%d] for %s is 0x%x"%(fieldIndex,vname,globals()[vname]))
# print ("dflt[%d] for %s is 0x%x"%(fieldIndex,vname,DEFAULTS[vname]))
return ( globals()[vname] >> (8*fieldIndex)) & 0xff
def get_default_field(vname,
fieldIndex):
"""
Get specified byte in the parameter default value (read at program
start from Verilog parameters)
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
Return specified byte
"""
global DEFAULTS
# print ("value for %s is %s"%(vname,str(globals()[vname])))
# print ("dflt for %s is %s"%(vname,str(DEFAULTS[vname])))
# print ("value[%d] for %s is 0x%x"%(fieldIndex,vname,globals()[vname]))
# print ("dflt[%d] for %s is 0x%x"%(fieldIndex,vname,DEFAULTS[vname]))
return (DEFAULTS[vname] >> (8*fieldIndex)) & 0xff
def get_default(vname):
"""
Get parameter default value (read at program start from Verilog parameters)
<vname> Verilog parameter name string (as listen in 'parameters')
Return specified parameter default
"""
global DEFAULTS
return DEFAULTS[vname]
def save_default(vname=None):
"""
Save parameter default value (replace read at program start from Verilog
parameters) using current parameter value
<vname> Verilog parameter name string (as listen in 'parameters')
"""
global DEFAULTS
if vname and vname in DEFAULTS:
DEFAULTS[vname] = globals()[vname]
else:
for vname in DEFAULTS:
DEFAULTS[vname] = globals()[vname]
def restore_default(vname=None):
"""
Restore parameter value from default
<vname> Verilog parameter name string (as listen in 'parameters')
"""
global DEFAULTS
if vname:
globals()[vname] = DEFAULTS[vname]
else:
for vname in DEFAULTS:
globals()[vname] = DEFAULTS[vname]
#### PyDev predefines
SS_EN__RAW = str
CLKIN_PERIOD_PCLK = int
SENSI2C_STATUS_REG_REL__TYPE = str
VOSPI_TELEMETRY__TYPE = str
SENSI2C_CMD_RUN_PBITS__RAW = str
XOR_HIST_BAYER__TYPE = str
HIST_SAXI_AWCACHE__RAW = str
CLK_STATUS_REG_ADDR__TYPE = str
MCONTR_TOP_16BIT_STATUS_CNTRL__TYPE = str
HIST_SAXI_ADDR_MASK = int
CONTROL_RBACK_ADDR_MASK = int
SENSOR_CHN_EN_BIT_SET__RAW = str
CMPRS_CBIT_QBANK__TYPE = str
LWIR_TELEMETRY_AGC_HIGH = int
CLKOUT_DIV_PCLK__RAW = str
SENS_GAMMA_CTRL__RAW = str
DFLT_INV_CLK_DIV__RAW = str
SENS_LENS_SCALES_MASK__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
LOGGER_ADDR__RAW = str
LWIR_MS_PERIOD = int
NUM_CYCLES_30__RAW = str
DLY_DQ_IDELAY__TYPE = str
VOSPI_SOF_TO_HACT = int
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__TYPE = str
MCONTR_LINTILE_RST_FRAME = int
CMPRS_CBIT_CMODE_MONO6__RAW = str
MCONTR_PHY_0BIT_DCI_RST = int
SENSOR_FIFO_2DEPTH = int
HIGH_PERFORMANCE_MODE__TYPE = str
VOSPI_MCLK = int
PXD_CAPACITANCE__RAW = str
AFI_LO_ADDR64__TYPE = str
VOSPI_MRST_BITS = int
MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
VOSPI_EN = int
AFI_SIZE64 = int
LOGGER_CONF_IMU_BITS = int
SENS_JTAG_TCK__RAW = str
HISPI_DIFF_TERM = str
MCONTR_PHY_0BIT_SDRST_ACT = int
SENSI2C_IBUF_LOW_PWR = str
CLKOUT_DIV_PCLK2X__RAW = str
CMPRS_JP4__TYPE = str
TABLE_CORING_INDEX = int
DQSTRI_LAST = int
MCNTRL_TEST01_CHN2_STATUS_CNTRL__TYPE = str
STATUS_2LSB_SHFT__TYPE = str
MEMBRIDGE_LEN64__TYPE = str
SENSOR_TIMING_STATUS_REG_INC = int
HISTOGRAM_ADDR_MASK__RAW = str
LOGGER_CONF_EN__RAW = str
VOSPI_IBUF_LOW_PWR__RAW = str
LWIR_TELEMETRY_AGC_LOW__TYPE = str
HIST_CONFIRM_WRITE = int
CMPRS_GROUP_ADDR__TYPE = str
CMDFRAMESEQ_ADDR_INC = int
CAMSYNC_TRIG_PERIOD = int
CMPRS_CBIT_FRAMES_BITS = int
SENSOR_HIST_EN_BITS__TYPE = str
CMDSEQMUX_STATUS__TYPE = str
DFLT_DQS_PATTERN__TYPE = str
MCONTR_LINTILE_SINGLE = int
MCNTRL_TEST01_ADDR__RAW = str
SENS_GAMMA_MODE_PAGE__RAW = str
CLKFBOUT_PHASE_SENSOR = float
DFLT_REFRESH_PERIOD = int
MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
NUM_CYCLES_20__TYPE = str
SENSI2C_TBL_NBRD__TYPE = str
SENS_JTAG_PGMEN = int
NUM_CYCLES_03__TYPE = str
VOSPI_SLEW = str
CMPRS_CBIT_RUN_BITS__TYPE = str
SENSOR12BITS_TDDO1 = int
TILED_EXTRA_PAGES__RAW = str
MEMBRIDGE_CTRL_IRQ__RAW = str
CMPRS_NUM_AFI_CHN = int
CAMSYNC_TRIG_SRC__RAW = str
MEMCLK_CAPACITANCE = str
MULT_SAXI_ADV_RD__TYPE = str
SENSIO_WIDTH__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
CONTROL_RBACK_ADDR__RAW = str
CMPRS_AFIMUX_CYCBITS = int
VOSPI_OUT_EN__RAW = str
RTC_MHZ = int
VOSPI_PACKET_WORDS = int
SENS_LENS_C_MASK = int
MCONTR_PHY_16BIT_EXTRA = int
HIST_SAXI_EN__TYPE = str
VOSPI_SEGMENT_FIRST = int
DEBUG_READ_REG_ADDR__TYPE = str
DEBUG_LOAD__RAW = str
WINDOW_Y0__RAW = str
CMPRS_STATUS_CNTRL = int
SENSI2C_CMD_ACIVE_SDA__RAW = str
CLK_STATUS_REG_ADDR__RAW = str
CMPRS_CSAT_CB_BITS__TYPE = str
SENSI2C_SLEW__TYPE = str
MEMBRIDGE_WIDTH64__RAW = str
LOGGER_CONF_MSG_BITS__RAW = str
SENS_GAMMA_MODE_REPET = int
SENSI2C_TBL_DLY__RAW = str
SENSOR_TIMING_LANE = int
CMPRS_CBIT_BAYER_BITS__TYPE = str
MCONTR_CMPRS_STATUS_INC = int
MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR = int
RTC_SET_STATUS__TYPE = str
CMPRS_CBIT_QBANK_BITS__RAW = str
DEBUG_READ_REG_ADDR = int
WINDOW_HEIGHT = int
NUM_INTERRUPTS__TYPE = str
CAMSYNC_TRIG_DELAY0__RAW = str
MCONTR_SENS_STATUS_INC__RAW = str
SENSOR_HIST_NRST_BITS = int
SENSI2C_ABS_RADDR__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
CLKFBOUT_MULT = int
RTC_STATUS_REG_ADDR__RAW = str
VOSPI_MCLK_HALFDIV__RAW = str
SENS_LENS_C_MASK__RAW = str
SIMULATE_CMPRS_CMODE0__RAW = str
NUM_CYCLES_11__TYPE = str
DEBUG_ADDR__TYPE = str
CMPRS_CBIT_QBANK_BITS__TYPE = str
SENS_GAMMA_MODE_TRIG = int
RTC_SET_USEC = int
RTC_BITC_PREDIV__TYPE = str
SIMULATE_CMPRS_CMODE0__TYPE = str
LD_DLY_CMDA = int
DLY_SET__RAW = str
SENSI2C_CMD_TABLE = int
MCNTRL_PS_ADDR__RAW = str
WOI_WIDTH__TYPE = str
NUM_FRAME_BITS__RAW = str
SENSI2C_CMD_ACIVE__RAW = str
HISTOGRAM_TOP__RAW = str
LOGGER_CONF_GPS__TYPE = str
HIST_SAXI_EN__RAW = str
SENSOR_16BIT_BIT__RAW = str
HIST_SAXI_AWCACHE__TYPE = str
SENSI2C_CMD_RUN_PBITS__TYPE = str
VOSPI_PACKET_LAST__TYPE = str
LWIR_TELEMETRY_TEMP_KELVIN__RAW = str
LOGGER_CONF_SYN_BITS__TYPE = str
MULTICLK_DIVCLK__RAW = str
GPIO_ADDR__TYPE = str
CAMSYNC_TRIG_SRC = int
SENS_CTRL_GP1__RAW = str
CLKOUT_DIV_PCLK__TYPE = str
LOGGER_PAGE_IMU = int
MEMCLK_IOSTANDARD__RAW = str
MAX_TILE_HEIGHT__RAW = str
BUF_IPCLK2X_SENS3__TYPE = str
IBUF_LOW_PWR = str
MCONTR_LINTILE_LINEAR = int
VOSPI_VSYNC_BITS__TYPE = str
DEBUG_CMD_LATENCY = int
CMD_DONE_BIT = int
NUM_CYCLES_31 = int
NUM_CYCLES_30 = int
HISPI_DELAY_CLK0__TYPE = str
CMPRS_CBIT_QBANK__RAW = str
SENS_SYNC_MASK__TYPE = str
MEMCLK_PERIOD__TYPE = str
MCONTR_BUF0_RD_ADDR__RAW = str
LWIR_TELEMETRY_SREV__RAW = str
SENS_PHASE_WIDTH = int
HIST_SAXI_MODE_ADDR_MASK__TYPE = str
MCONTR_CMPRS_STATUS_BASE__RAW = str
SENS_LENS_RADDR__TYPE = str
LWIR_TELEMETRY_AGC_HIGH__RAW = str
SENSI2C_CMD_SOFT_SCL = int
CAMSYNC_PRE_MAGIC__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
DEBUG_LOAD = int
CMPRS_JP4DIFF__TYPE = str
MULT_SAXI_CNTRL_IRQ__TYPE = str
LOGGER_CONF_DBG__RAW = str
FRAME_START_ADDRESS_INC__TYPE = str
DLY_DQS_IDELAY__TYPE = str
CLK_PHASE = float
MCNTRL_TILED_FRAME_PAGE_RESET = int
MCONTR_SENS_STATUS_BASE__TYPE = str
CMPRS_FORMAT__TYPE = str
DLY_LANE1_DQS_WLV_IDELAY__RAW = str
VOSPI_NO_INVALID__RAW = str
SENS_LENS_RADDR = int
SENSI2C_CMD_TABLE__TYPE = str
PXD_IOSTANDARD = str
SENSOR12BITS_TMD__RAW = str
CMPRS_CBIT_ROWS_LSB_BITS = int
MAX_TILE_HEIGHT = int
BUF_CLK1X_PCLK = str
LOGGER_CONF_DBG_BITS = int
SENS_CTRL_ARO__TYPE = str
SENS_LENS_SCALES_MASK__RAW = str
LWIR_WINDOW_HEIGHT__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str
MCONTR_LINTILE_BYTE32__RAW = str
HISTOGRAM_WIDTH_HEIGHT = int
LWIR_TELEMETRY_AGC_ROI_BOTTOM = int
MCONTR_RD_MASK__TYPE = str
MULT_SAXI_CNTRL_MASK = int
NUM_CYCLES_23__RAW = str
REF_JITTER1__RAW = str
CAMSYNC_MASK__TYPE = str
SENS_JTAG_PGMEN__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
MCONTR_BUF3_RD_ADDR__TYPE = str
LOGGER_CONF_EN_BITS__TYPE = str
VOSPI_TELEMETRY_BITS__TYPE = str
CLKIN_PERIOD_PCLK__RAW = str
HISPI_DQS_BIAS__TYPE = str
MULTICLK_DIV_DLYREF__TYPE = str
MULTICLK_MULT = int
SENS_LENS_POST_SCALE_MASK = int
MEMCLK_PERIOD = float
BUF_IPCLK2X_SENS1__RAW = str
HISTOGRAM_WIDTH__RAW = str
SENS_LENS_FAT0_OUT_MASK = int
SENS_SYNC_MULT__TYPE = str
NUM_CYCLES_27__RAW = str
SENSI2C_IOSTANDARD__RAW = str
SCANLINE_EXTRA_PAGES__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFF__RAW = str
CMPRS_AFIMUX_MASK__TYPE = str
MCONTR_SENS_INC = int
CAMSYNC_TRIG_PERIOD__TYPE = str
SENSIO_STATUS = int
DFLT_DQS_PATTERN = int
MCONTR_BUF3_RD_ADDR__RAW = str
CAMSYNC_TRIGGERED_BIT__TYPE = str
SENS_GAMMA_ADDR_DATA__RAW = str
DLY_LANE1_IDELAY__RAW = str
SLEW_CLK = str
CMPRS_JP4DIFF = int
RTC_STATUS_REG_ADDR = int
SENS_LENS_BY_MASK__TYPE = str
CMPRS_CBIT_CMODE__RAW = str
TILED_EXTRA_PAGES__TYPE = str
FRAME_START_ADDRESS__TYPE = str
AXI_RDADDR_LATENCY = int
VOSPI_VSYNC__TYPE = str
AFI_MUX_BUF_LATENCY = int
WINDOW_WIDTH = int
CLK_CNTRL__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS = int
MCONTR_LINTILE_RST_FRAME__TYPE = str
LAST_BUF_FRAME__RAW = str
FCLK1_PERIOD = float
CMPRS_AFIMUX_RADDR1__RAW = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
CMPRS_CBIT_DCSUB_BITS__RAW = str
SENS_CTRL_LD_DLY__RAW = str
HIST_SAXI_MODE_ADDR_REL__TYPE = str
MULT_SAXI_CNTRL_STATUS__RAW = str
CMPRS_CBIT_CMODE_JP46__TYPE = str
NUM_CYCLES_17__RAW = str
DFLT_WBUF_DELAY__RAW = str
CAMSYNC_POST_MAGIC__RAW = str
NUM_CYCLES_07__RAW = str
NUM_CYCLES_24__RAW = str
VOSPI_SEGM0_OK__RAW = str
NUM_INTERRUPTS = int
NUM_CYCLES_13__RAW = str
LOGGER_CONF_MSG__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
VOSPI_PACKETS_PER_LINE = int
LAST_FRAME_BITS__RAW = str
VOSPI_MCLK__RAW = str
SENS_DIVCLK_DIVIDE = int
SENSI2C_CMD_SOFT_SDA__TYPE = str
SENS_LENS_COEFF__RAW = str
GPIO_MASK = int
GPIO_STATUS_REG_ADDR = int
AXI_TASK_HOLD__RAW = str
MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
CMPRS_AFIMUX_RADDR0__TYPE = str
MCNTRL_TILED_WINDOW_WH__RAW = str
DLY_DM_ODELAY__RAW = str
CMPRS_FRMT_MBRM1_BITS = int
CAMSYNC_EXTERNAL_BIT = int
CMPRS_STATUS_REG_BASE__TYPE = str
AFI_MUX_BUF_LATENCY__TYPE = str
SENSOR_CTRL_RADDR = int
FRAME_WIDTH_BITS__RAW = str
ADDRESS_NUMBER__RAW = str
STATUS_PSHIFTER_RDY_MASK__TYPE = str
SENSI2C_ADDR_MASK = int
LD_DLY_LANE1_IDELAY = int
SENS_SYNC_MASK = int
DIVCLK_DIVIDE = int
CMD_PAUSE_BITS__RAW = str
SENSI2C_TBL_DLY_BITS = int
IDELAY_VALUE__RAW = str
MULTICLK_PHASE_SYNC__TYPE = str
BUFFER_DEPTH32 = int
SENS_CTRL_QUADRANTS__TYPE = str
SENS_LENS_BY_MASK__RAW = str
SENS_CTRL_GP0__TYPE = str
DFLT_REFRESH_ADDR = int
DLY_DQS_ODELAY__TYPE = str
TEST01_SUSPEND__RAW = str
SENS_GAMMA_HEIGHT01__TYPE = str
LWIR_TELEMETRY_AGC_LOW__RAW = str
LWIR_TELEMETRY_TEMP_KELVIN__TYPE = str
CMPRS_HIFREQ_REG_INC = int
STATUS_ADDR_MASK__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
TEST01_START_FRAME = int
LWIR_DATA_FILE3 = str
RTC_SET_USEC__RAW = str
LOGGER_CONF_SYN_BITS__RAW = str
CAMSYNC_ADDR__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__TYPE = str
LWIR_TELEMETRY_AGC_LOW = int
MULT_SAXI_BSLOG1__TYPE = str
LOGGER_CONF_MSG_BITS__TYPE = str
LOGGER_ADDR = int
MCONTR_PHY_0BIT_DCI_RST__RAW = str
REFCLK_FREQUENCY__RAW = str
VOSPI_TELEMETRY_BITS__RAW = str
LOGGER_BIT_HALF_PERIOD__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str
DLY_DQ_ODELAY__TYPE = str
SENSOR_FIFO_2DEPTH__TYPE = str
NUM_CYCLES_28 = int
NUM_CYCLES_29 = int
NUM_CYCLES_26 = int
NUM_CYCLES_27 = int
NUM_CYCLES_24 = int
NUM_CYCLES_25 = int
NUM_CYCLES_22 = int
NUM_CYCLES_23 = int
NUM_CYCLES_20 = int
NUM_CYCLES_21 = int
FRAME_FULL_WIDTH__TYPE = str
CAMSYNC_TRIG_DELAY2__TYPE = str
SENS_CTRL_QUADRANTS_WIDTH__RAW = str
FCLK0_PERIOD = float
CMDFRAMESEQ_REL__TYPE = str
HISPI_DELAY_CLK0 = str
MCNTRL_SCANLINE_DLY_WIDTH = int
MAX_TILE_WIDTH__RAW = str
PICKLE = str
AFI_SIZE64__TYPE = str
NUM_CYCLES_LOW_BIT__TYPE = str
MCONTR_PHY_0BIT_ADDR_MASK = int
SENSI2C_SLEW = str
VOSPI_DBG_SRC_BITS__RAW = str
DFLT_WBUF_DELAY__TYPE = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
SENSI2C_STATUS_REG_INC__TYPE = str
MULT_SAXI_CNTRL_STATUS__TYPE = str
CMPRS_FRMT_MBRM1_BITS__RAW = str
SCANLINE_EXTRA_PAGES = int
LD_DLY_LANE1_ODELAY__RAW = str
LOGGER_CONF_EN_BITS__RAW = str
SENS_CTRL_IGNORE_EMBED__TYPE = str
MAX_TILE_WIDTH__TYPE = str
SENS_LENS_FAT0_IN_MASK__TYPE = str
RSEL = int
LWIR_TELEMETRY_AGC_ROI_TOP__TYPE = str
TABLE_CORING_INDEX__TYPE = str
AXI_RD_ADDR_BITS__TYPE = str
CAMSYNC_CHN_EN_BIT__TYPE = str
CMDFRAMESEQ_ADDR_BASE__RAW = str
MCONTR_LINTILE_SKIP_LATE__TYPE = str
DEBUG_ADDR__RAW = str
VOSPI_NORESYNC = int
TILED_STARTY__RAW = str
RTC_BITC_PREDIV = int
CMPRS_FRMT_MBCM1_BITS__TYPE = str
SENS_CTRL_QUADRANTS_EN__RAW = str
HISPI_DELAY_CLK1__TYPE = str
NUM_CYCLES_14__TYPE = str
MCONTR_CMPRS_INC__TYPE = str
TILED_EXTRA_PAGES = int
DLY_DQS_ODELAY__RAW = str
CLKIN_PERIOD_PCLK__TYPE = str
FFCLK1_DIFF_TERM__RAW = str
SENS_JTAG_TDI__RAW = str
MCONTR_SENS_STATUS_BASE = int
AXI_WR_ADDR_BITS__RAW = str
SENSI2C_CMD_RUN__TYPE = str
MULTICLK_DIV_SYNC__RAW = str
VOSPI_EN__RAW = str
CMPRS_CORING_MODE = int
LOGGER_STATUS__TYPE = str
DFLT_REFRESH_PERIOD__TYPE = str
SENS_JTAG_TMS__TYPE = str
MCNTRL_TILED_MASK = int
MULTICLK_DIV_AXIHP = int
SENSIO_JTAG__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
SENSIO_STATUS__TYPE = str
GPIO_SLEW = str
LOGGER_CONF_SYN__TYPE = str
CAMSYNC_DELAY__RAW = str
LOGGER_CONF_DBG_BITS__RAW = str
FRAME_HEIGHT_BITS__RAW = str
MCONTR_LINTILE_KEEP_OPEN = int
SENS_SYNC_LATE__RAW = str
SENSI2C_TBL_NBRD_BITS__RAW = str
DLY_CMDA_ODELAY = int
GPIO_PORTEN__RAW = str
LOGGER_BIT_DURATION__RAW = str
VOSPI_DBG_SRC_BITS = int
MCONTR_ARBIT_ADDR_MASK = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_WINDOW_WH = int
WBUF_DLY_WLV__RAW = str
SIMULATE_CMPRS_CMODE3__RAW = str
VOSPI_TELEMETRY__RAW = str
TABLE_HUFFMAN_INDEX = int
VOSPI_HACT_TO_HACT_EOF__RAW = str
MCNTRL_TILED_FRAME_LAST = int
MCNTRL_TEST01_CHN2_MODE__RAW = str
CMPRS_RAW__TYPE = str
HISPI_DELAY_CLK1__RAW = str
SENSI2C_TBL_RNWREG__RAW = str
RTC_SEC_USEC_ADDR = int
LOGGER_CONF_DBG = int
CAMSYNC_EN_BIT__TYPE = str
LD_DLY_LANE0_IDELAY = int
NUM_CYCLES_01__TYPE = str
NUM_CYCLES_24__TYPE = str
FCLK0_PERIOD__RAW = str
VOSPI_SEGM0_OK_BITS__RAW = str
MCLK_PHASE__TYPE = str
SENSI2C_DRIVE__TYPE = str
SENS_CTRL_RST_MMCM__RAW = str
MCONTR_BUF2_WR_ADDR__TYPE = str
GPIO_SLEW__TYPE = str
SENS_LENS_BX__RAW = str
DQTRI_LAST__TYPE = str
TEST_INITIAL_BURST = int
SENS_REF_JITTER1__RAW = str
MCNTRL_TILED_FRAME_FULL_WIDTH = int
CMDFRAMESEQ_DEPTH = int
SENS_LENS_POST_SCALE__TYPE = str
RTC_MHZ__RAW = str
MCONTR_LINTILE_COPY_FRAME = int
CMPRS_CBIT_BE16 = int
SENSOR_PRIORITY__RAW = str
HIST_SAXI_ADDR_MASK__TYPE = str
SENS_CTRL_LD_DLY = int
VOSPI_VSYNC_BITS__RAW = str
SENS_LENS_FAT0_IN_MASK__RAW = str
SENS_LENS_AY_MASK__RAW = str
SENSOR_IMAGE_TYPE1__TYPE = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_LINTILE_DIS_NEED__TYPE = str
DFLT_DQS_PATTERN__RAW = str
MCNTRL_PS_STATUS_CNTRL__TYPE = str
MCONTR_PHY_16BIT_ADDR = int
REF_JITTER1__TYPE = str
MCNTRL_TEST01_MASK = int
FFCLK1_DIFF_TERM = str
MULTICLK_PHASE_AXIHP__TYPE = str
FFCLK0_IOSTANDARD__TYPE = str
MCNTRL_SCANLINE_DLY_DEFAULT__TYPE = str
WOI_WIDTH__RAW = str
STATUS_MSB_RSHFT = int
CMPRS_CONTROL_REG__RAW = str
CLKIN_PERIOD__TYPE = str
SENS_GAMMA_CTRL = int
HISPI_WAIT_ALL_LANES__TYPE = str
SENSIO_RADDR = int
VOSPI_NORESYNC_BITS__RAW = str
BUF_CLK1X_PCLK__RAW = str
LWIR_FRAME_DELAY = int
GPIO_N__TYPE = str
MCONTR_BUF4_RD_ADDR__TYPE = str
NUM_CYCLES_16__RAW = str
LD_DLY_LANE0_ODELAY__TYPE = str
MCONTR_TOP_16BIT_ADDR__RAW = str
MCNTRL_SCANLINE_DLY_WIDTH__RAW = str
HIST_SAXI_MODE_ADDR_REL = int
MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
BUFFER_DEPTH32__TYPE = str
CMPRS_CBIT_CMODE_JPEG18 = int
MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
HISTOGRAM_RADDR0__TYPE = str
HISPI_FIFO_DEPTH__TYPE = str
LOGGER_CONF_SYN_BITS = int
MCONTR_CMPRS_BASE__RAW = str
NUM_CYCLES_19 = int
MULTICLK_DIV_XCLK2X = int
SENS_CTRL_GP1__TYPE = str
MCNTRL_TEST01_MASK__TYPE = str
SENSOR_16BIT_BIT_SET__RAW = str
LWIR_TELEMETRY__TYPE = str
HISPI_IBUF_LOW_PWR__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
SENSOR_FIFO_DELAY__RAW = str
DLY_SET = int
CMDFRAMESEQ_CTRL__TYPE = str
HISPI_FIFO_DEPTH__RAW = str
SENSOR_HIST_BITS_SET__RAW = str
NUM_CYCLES_12 = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
MCNTRL_TILED_CHN2_ADDR__TYPE = str
NUM_CYCLES_11 = int
SENS_GAMMA_ADDR_MASK = int
NUM_CYCLES_10 = int
MEMCLK_IBUF_LOW_PWR__TYPE = str
HISTOGRAM_HEIGHT__TYPE = str
CMPRS_HIFREQ_REG_BASE__TYPE = str
FCLK0_PERIOD__TYPE = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
LWIR_WINDOW_WIDTH__TYPE = str
MULTICLK_DIVCLK__TYPE = str
DLY_DQ_ODELAY = int
BUF_IPCLK_SENS1__TYPE = str
VOSPI_DRIVE = int
MCONTR_TOP_16BIT_ADDR = int
CMPRS_TIMEOUT = int
LWIR_TELEMETRY_TEMP_COUTS__TYPE = str
HISPI_IOSTANDARD__TYPE = str
CMPRS_AFIMUX_RST = int
NUM_CYCLES_18 = int
SENS_LENS_POST_SCALE_MASK__RAW = str
NUM_CYCLES_13 = int
CMPRS_FRMT_MBRM1__TYPE = str
VERBOSE__RAW = str
LOGGER_CONF_IMU_BITS__RAW = str
NUM_CYCLES_17 = int
NUM_CYCLES_16 = int
NUM_CYCLES_15 = int
NUM_CYCLES_21__TYPE = str
CMPRS_CBIT_BAYER = int
SLEW_CLK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET = int
HISPI_DIFF_TERM__TYPE = str
CMPRS_CSAT_CB__RAW = str
CMD_PAUSE_BITS = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
HISPI_IOSTANDARD__RAW = str
SENSI2C_TBL_SA__TYPE = str
BUF_IPCLK_SENS3__TYPE = str
MCNTRL_TILED_MODE = int
MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
CMPRS_COLOR20__TYPE = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
MCNTRL_SCANLINE_START_DELAY__TYPE = str
LOGGER_CONF_SYN = int
MCNTRL_TILED_CHN4_ADDR__RAW = str
MCONTR_CMPRS_STATUS_BASE = int
MCONTR_PHY_16BIT_PATTERNS__TYPE = str
MCONTR_PHY_0BIT_CKE_EN__RAW = str
NUM_CYCLES_26__TYPE = str
PICKLE__RAW = str
DQSTRI_LAST__RAW = str
WRITELEV_OFFSET__TYPE = str
CMPRS_BASE_INC = int
SIMULATE_CMPRS_CMODE2 = int
SIMULATE_CMPRS_CMODE3 = int
SIMULATE_CMPRS_CMODE0 = int
SIMULATE_CMPRS_CMODE1 = int
MULT_SAXI_BSLOG3__RAW = str
MULTICLK_BUF_SYNC__TYPE = str
HIST_SAXI_ADDR_REL__RAW = str
SENS_GAMMA_MODE_PAGE_SET__RAW = str
LWIR_DATA_FILE1__RAW = str
CMPRS_CBIT_CMODE_MONO4__TYPE = str
HIST_SAXI_MODE_WIDTH__RAW = str
SENS_LENS_AX = int
MCONTR_PHY_16BIT_PATTERNS = int
SENSOR_CTRL_ADDR_MASK__TYPE = str
CMPRS_MONO16__RAW = str
RTC_ADDR = int
VOSPI_RESET_ERR__TYPE = str
SENSIO_RADDR__TYPE = str
CLKFBOUT_MULT_PCLK__TYPE = str
CLK_ADDR__TYPE = str
CMPRS_FORMAT = int
VOSPI_SEGM0_OK_BITS = int
SENSIO_STATUS_REG_REL = int
FFCLK1_CAPACITANCE = str
CMPRS_CBIT_CMODE_BITS__RAW = str
CMPRS_TABLES = int
HIST_SAXI_MODE_WIDTH = int
CMPRS_AFIMUX_RADDR0__RAW = str
CAMSYNC_EN_BIT = int
MCONTR_PHY_16BIT_PATTERNS__RAW = str
HISTOGRAM_RAM_MODE = str
VOSPI_GPIO_BITS = int
SENS_REFCLK_FREQUENCY__TYPE = str
HISTOGRAM_TOP__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENS_CTRL_ODD__TYPE = str
SENSI2C_TBL_SA_BITS__TYPE = str
DEBUG_ADDR = int
MCNTRL_SCANLINE_START_DELAY__RAW = str
SIMULATE_CMPRS_CMODE2__TYPE = str
MCONTR_LINTILE_LINEAR__RAW = str
LOGGER_PAGE_GPS = int
HIST_SAXI_MODE_ADDR_MASK = int
CMPRS_AFIMUX_SA_LEN__RAW = str
LOGGER_CONF_MSG = int
CMPRS_CSAT_CR__RAW = str
CMPRS_CBIT_RUN = int
SENS_LENS_ADDR_MASK__RAW = str
SENS_CTRL_QUADRANTS__RAW = str
SENSOR_TIMING_BITS__TYPE = str
RTC_MASK__RAW = str
SENS_LENS_ADDR_MASK__TYPE = str
SENS_LENS_AX__TYPE = str
PXD_DRIVE__TYPE = str
HIST_SAXI_NRESET = int
MULT_SAXI_HALF_BRAM_IN__RAW = str
HISTOGRAM_HEIGHT = int
SENSI2C_TBL_SA__RAW = str
CMPRS_CBIT_CMODE_JP4__RAW = str
VOSPI_RST_SEQ__RAW = str
MULTICLK_BUF_AXIHP__RAW = str
CLK_STATUS__TYPE = str
VOSPI_OUT_EN_BITS = int
GPIO_SET_STATUS__RAW = str
SENS_JTAG_TCK = int
SENS_CTRL_ODD__RAW = str
XOR_HIST_BAYER__RAW = str
DEBUG_STATUS_REG_ADDR__TYPE = str
REFRESH_OFFSET__TYPE = str
SENS_CTRL_ARST__RAW = str
CMPRS_CBIT_DCSUB__TYPE = str
DFLT_INV_CLK_DIV__TYPE = str
HISTOGRAM_RADDR_INC__RAW = str
MEMBRIDGE_WIDTH64__TYPE = str
SENS_GAMMA_MODE_BAYER__RAW = str
MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
CMPRS_CBIT_FOCUS_BITS__TYPE = str
STATUS_ADDR__RAW = str
NUM_CYCLES_30__TYPE = str
HISPI_MMCM1__TYPE = str
SDCLK_PHASE__RAW = str
SENS_SYNC_RADDR__TYPE = str
BUF_IPCLK_SENS0__TYPE = str
SENSI2C_CMD_RUN__RAW = str
VOSPI_SEGM0_OK = int
VOSPI_RST_SEQ = int
MCNTRL_TILED_STARTADDR__TYPE = str
DLY_LD_MASK = int
VOSPI_MRST_BITS__TYPE = str
CAMSYNC_TRIG_DELAY3__RAW = str
NUM_CYCLES_09__RAW = str
VOSPI_SPI_SEQ = int
SENS_SYNC_LBITS__RAW = str
MEMBRIDGE_SIZE64__TYPE = str
SENS_GAMMA_HEIGHT2 = int
DLY_LD_MASK__TYPE = str
STATUS_MSB_RSHFT__TYPE = str
MCONTR_BUF0_RD_ADDR = int
HIST_SAXI_ADDR_REL__TYPE = str
CMPRS_CBIT_CMODE_JPEG20 = int
CMPRS_TIMEOUT_BITS = int
CAMSYNC_PRE_MAGIC = int
SENS_JTAG_TMS = int
MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
MCNTRL_PS_EN_RST__TYPE = str
BUF_CLK1X_PCLK2X__TYPE = str
MCNTRL_TILED_CHN4_ADDR = int
MULT_SAXI_POINTERS_REG__RAW = str
MCONTR_SENS_INC__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__TYPE = str
LOGGER_MASK__RAW = str
IBUF_LOW_PWR__RAW = str
DLY_CMDA_ODELAY__TYPE = str
VOSPI_SPI_CLK_BITS = int
SENS_LENS_FAT0_OUT_MASK__TYPE = str
LWIR_GPIO_IN__TYPE = str
SENSI2C_ABS_RADDR__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
WBUF_DLY_WLV__TYPE = str
HISPI_MSB_FIRST__TYPE = str
MCONTR_TOP_16BIT_CHN_EN = int
LWIR_WINDOW_WIDTH__RAW = str
BUF_IPCLK2X_SENS1__TYPE = str
DEFAULT_STATUS_MODE = int
CMPRS_CBIT_CMODE_JPEG18__TYPE = str
MULT_SAXI_AWCACHE = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET = int
MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__RAW = str
VOSPI_EN_BITS = int
SENSI2C_TBL_RAH__RAW = str
CMPRS_CSAT_CR_BITS__TYPE = str
NUM_CYCLES_05 = int
NUM_CYCLES_06 = int
NUM_CYCLES_07 = int
NUM_CYCLES_00 = int
NUM_CYCLES_01 = int
NUM_CYCLES_02 = int
NUM_CYCLES_03 = int
SENSIO_ADDR_MASK__TYPE = str
NUM_CYCLES_08 = int
NUM_CYCLES_09 = int
MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str
SENS_SYNC_LBITS = int
STATUS_DEPTH__RAW = str
NUM_CYCLES_25__TYPE = str
MCONTR_LINTILE_REPEAT = int
CHNBUF_READ_LATENCY = int
SENS_CTRL_QUADRANTS_WIDTH = int
STATUS_PSHIFTER_RDY_MASK__RAW = str
WBUF_DLY_DFLT__RAW = str
SENS_GAMMA_MODE_BAYER__TYPE = str
MULT_SAXI_CNTRL_IRQ = int
TILE_WIDTH__TYPE = str
MCNTRL_TILED_FRAME_LAST__RAW = str
SENSI2C_CMD_RESET__RAW = str
REFRESH_OFFSET = int
MCNTRL_PS_EN_RST = int
MCONTR_SENS_BASE__RAW = str
SENS_GAMMA_ADDR_MASK__TYPE = str
CMPRS_CSAT_CR = int
CMPRS_CBIT_RUN_ENABLE = int
INITIALIZE_OFFSET = int
MCONTR_TOP_16BIT_CHN_EN__TYPE = str
CMPRS_CSAT_CB = int
VOSPI_SEGMENT_LAST__TYPE = str
VERBOSE = int
DLY_LANE1_ODELAY = int
LOGGER_PERIOD__RAW = str
LWIR_TELEMETRY_STATUS__RAW = str
MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
SENS_LENS_AX_MASK = int
AXI_RD_ADDR_BITS__RAW = str
MCONTR_PHY_16BIT_EXTRA__RAW = str
SENS_SS_MOD_PERIOD__TYPE = str
MCONTR_LINTILE_SKIP_LATE__RAW = str
SENS_JTAG_PGMEN__TYPE = str
CMPRS_CBIT_CMODE_RAW__RAW = str
MEMBRIDGE_LEN64__RAW = str
LWIR_DATA_FILE2__TYPE = str
MCONTR_LINTILE_EN = int
DFLT_REFRESH_ADDR__RAW = str
GPIO_N = int
MCONTR_ARBIT_ADDR_MASK__TYPE = str
SENS_CTRL_MRST__TYPE = str
HISTOGRAM_RADDR_INC__TYPE = str
SENS_CTRL_GP0 = int
SENS_CTRL_GP1 = int
FFCLK0_IBUF_LOW_PWR__TYPE = str
SENS_SYNC_MINBITS__TYPE = str
LWIR_TELEMETRY_REV = int
CMPRS_CBIT_DCSUB_BITS__TYPE = str
SENS_GAMMA_RADDR = int
NUM_CYCLES_14__RAW = str
CMPRS_AFIMUX_MASK__RAW = str
CLKIN_PERIOD_SENSOR__RAW = str
PHASE_WIDTH__TYPE = str
CMPRS_JP4__RAW = str
CMPRS_HIFREQ_REG_BASE__RAW = str
SS_MOD_PERIOD = int
MCONTR_CMPRS_BASE__TYPE = str
FFCLK1_IBUF_LOW_PWR = str
HISPI_CAPACITANCE__TYPE = str
MCONTR_LINTILE_KEEP_OPEN__TYPE = str
SENS_LENS_POST_SCALE = int
LOGGER_STATUS_REG_ADDR__TYPE = str
MEMBRIDGE_LO_ADDR64__TYPE = str
MCONTR_CMD_WR_ADDR__RAW = str
CMDFRAMESEQ_CTRL = int
DLY_LD__TYPE = str
MCNTRL_SCANLINE_STARTADDR__TYPE = str
SENS_JTAG_PROG__RAW = str
CMDFRAMESEQ_REL__RAW = str
CMPRS_AFIMUX_MASK = int
DLY_PHASE = int
CONTROL_RBACK_DEPTH__RAW = str
MCONTR_LINTILE_NRESET__RAW = str
MULT_SAXI_CNTRL_MODE = int
PHASE_WIDTH = int
DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
MULT_SAXI_ADV_WR = int
MCNTRL_SCANLINE_MASK = int
MCONTR_LINTILE_LINEAR__TYPE = str
MULTICLK_DIVCLK = int
MCNTRL_TILED_TILE_WHS__TYPE = str
MULT_SAXI_BSLOG3__TYPE = str
SENSOR12BITS_NGPL__RAW = str
CLKFBOUT_MULT__RAW = str
VOSPI_SEGMENT_FIRST__TYPE = str
CMPRS_STATUS_REG_INC__RAW = str
SENSOR_TIMING_STATUS_REG_INC__RAW = str
HISTOGRAM_RADDR0__RAW = str
HISPI_KEEP_IRST = int
STATUS_ADDR_MASK = int
PXD_CAPACITANCE = str
SENS_LENS_AY = int
CMPRS_CBIT_CMODE_MONO6__TYPE = str
MULTICLK_BUF_XCLK__RAW = str
HISTOGRAM_RAM_MODE__RAW = str
SENS_LENS_AX_MASK__RAW = str
SENSI2C_TBL_SA_BITS = int
CMPRS_FRMT_MBCM1__TYPE = str
CMPRS_TIMEOUT__TYPE = str
MCLK_PHASE__RAW = str
NUM_CYCLES_10__TYPE = str
MCONTR_LINTILE_EXTRAPG__RAW = str
SENS_LENS_FAT0_IN__RAW = str
CMPRS_AFIMUX_STATUS_CNTRL__TYPE = str
LOGGER_CONFIG__RAW = str
LD_DLY_LANE0_ODELAY__RAW = str
PXD_CLK_DIV_BITS__RAW = str
CMPRS_FRMT_LMARG_BITS = int
CMDSEQMUX_ADDR = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__TYPE = str
SENS_GAMMA_MODE_PAGE_SET = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__TYPE = str
SENSI2C_TBL_NBWR = int
DLY_DQS_IDELAY__RAW = str
SENS_SYNC_RADDR = int
CONTROL_RBACK_ADDR_MASK__TYPE = str
MCONTR_BUF4_WR_ADDR = int
SENS_DIVCLK_DIVIDE__RAW = str
SENSOR_BASE_INC__RAW = str
VOSPI_PACKET_FIRST__RAW = str
CMPRS_CBIT_DCSUB_BITS = int
HISTOGRAM_LEFT__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK = int
PXD_IBUF_LOW_PWR__TYPE = str
MCONTR_LINTILE_REPEAT__TYPE = str
HIST_SAXI_MODE_WIDTH__TYPE = str
VOSPI_MRST_BITS__RAW = str
HISTOGRAM_RADDR2__RAW = str
SENSI2C_STATUS = int
CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
MEMBRIDGE_LEN64 = int
SENS_SYNC_LATE_DFLT = int
SENSI2C_STATUS_REG_BASE__RAW = str
AFI_LO_ADDR64__RAW = str
TILED_STARTX__RAW = str
MCNTRL_SCANLINE_STARTADDR__RAW = str
SENSI2C_STATUS_REG_BASE__TYPE = str
DEBUG_LOAD__TYPE = str
MCONTR_PHY_16BIT_WBUF_DELAY = int
DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
VOSPI_EN_BITS__TYPE = str
MULTICLK_PHASE_SYNC = float
SENSI2C_TBL_SA_BITS__RAW = str
HISPI_MMCM3__RAW = str
CMPRS_CBIT_RUN_STANDALONE = int
LWIR_DATA_FILE2__RAW = str
READ_BLOCK_OFFSET__RAW = str
HISTOGRAM_LEFT_TOP__TYPE = str
MCONTR_CMPRS_INC = int
CMPRS_CBIT_RUN_ENABLE__TYPE = str
LOGGER_CONF_IMU = int
DLY_DQS_IDELAY = int
HISTOGRAM_WIDTH_HEIGHT__TYPE = str
TEST01_NEXT_PAGE = int
MULTICLK_DIV_XCLK = int
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
PXD_IBUF_LOW_PWR = str
NUM_CYCLES_17__TYPE = str
SLEW_CLK__RAW = str
MCONTR_BUF2_WR_ADDR = int
SENS_LENS_FAT0_IN__TYPE = str
SENSIO_CTRL__TYPE = str
SENSIO_WIDTH__RAW = str
CMPRS_MASK__TYPE = str
MEMBRIDGE_SIZE64__RAW = str
CMPRS_CBIT_CMODE_RAW__TYPE = str
HISPI_IFD_DELAY_VALUE__RAW = str
CAMSYNC_GPIO_EXT_OUT__RAW = str
MCNTRL_PS_STATUS_CNTRL = int
VOSPI_VSYNC_BITS = int
SS_MODE__TYPE = str
SENSI2C_STATUS__RAW = str
CMPRS_MASK = int
CMPRS_CBIT_CMODE_RAW = int
SENSI2C_CMD_ACIVE_EARLY0__RAW = str
T_RFC__TYPE = str
HISPI_IBUF_DELAY_VALUE__RAW = str
MCONTR_LINTILE_NRESET__TYPE = str
PXD_CLK_DIV__RAW = str
SENS_NUM_SUBCHN__RAW = str
CMPRS_CBIT_RUN_ENABLE__RAW = str
AXI_RDADDR_LATENCY__TYPE = str
BUF_IPCLK_SENS3__RAW = str
CLK_STATUS__RAW = str
CMPRS_CBIT_ROWS_LSB__RAW = str
MULTICLK_BUF_AXIHP = str
FRAME_WIDTH_BITS = int
READ_PATTERN_OFFSET__TYPE = str
SENS_CTRL_RST_MMCM = int
VOSPI_TELEMETRY_BITS = int
VOSPI_PACKET_LAST = int
MCONTR_CMD_WR_ADDR = int
SENSI2C_TBL_DLY_BITS__RAW = str
SENSOR12BITS_TDDO1__RAW = str
HISPI_MMCM0__TYPE = str
TILE_WIDTH = int
CMPRS_CONTROL_REG = int
DLY_LANE0_ODELAY = int
NUM_XFER_BITS = int
HISPI_NUMLANES__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR = int
LWIR_DATA_FILE4 = str
LWIR_DATA_FILE1 = str
DLY_LANE0_ODELAY__RAW = str
LWIR_DATA_FILE2 = str
MCONTR_BUF3_WR_ADDR__TYPE = str
SCANLINE_STARTX__TYPE = str
SIMUL_AXI_READ_WIDTH = int
WRITE_BLOCK_OFFSET = int
FRAME_FULL_WIDTH__RAW = str
LOGGER_CONF_EN__TYPE = str
LOGGER_PAGE_IMU__RAW = str
SENS_SYNC_MINPER__RAW = str
VOSPI_IBUF_LOW_PWR__TYPE = str
CMPRS_AFIMUX_MODE__RAW = str
DFLT_DQ_TRI_OFF_PATTERN = int
SENSI2C_TBL_RAH_BITS = int
MULT_SAXI_CNTRL_IRQ__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
CHNBUF_READ_LATENCY__TYPE = str
CMPRS_CBIT_CMODE_BITS__TYPE = str
LOGGER_BIT_DURATION__TYPE = str
HISPI_MMCM1__RAW = str
MULT_SAXI_CNTRL_STATUS = int
TEST_INITIAL_BURST__TYPE = str
SENSOR12BITS_NVLO = int
LWIR_TELEMETRY_AGC_ROI_LEFT = int
NUM_CYCLES_19__RAW = str
SIMULATE_CMPRS_CMODE2__RAW = str
MCNTRL_PS_MASK__RAW = str
CMPRS_CBIT_CMODE_JPEG20__TYPE = str
VOSPI_SPI_SEQ__TYPE = str
CMPRS_TIMEOUT_BITS__RAW = str
MEMBRIDGE_LO_ADDR64__RAW = str
LWIR_TELEMETRY_VIDEO_FORMAT = int
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
RTC_SET_USEC__TYPE = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str
MULT_SAXI_CNTRL_ADDR = int
CMPRS_TIMEOUT_BITS__TYPE = str
PHASE_CLK2X_PCLK__TYPE = str
FFCLK1_DIFF_TERM__TYPE = str
WRITELEV_OFFSET = int
MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
MULT_SAXI_ADV_RD__RAW = str
SENS_GAMMA_MODE_EN_SET__RAW = str
SENS_GAMMA_MODE_BAYER_SET__TYPE = str
T_RFC__RAW = str
VOSPI_IOSTANDARD__RAW = str
WBUF_DLY_DFLT__TYPE = str
HISPI_DELAY_CLK0__RAW = str
PXD_SLEW__TYPE = str
FRAME_START_ADDRESS = int
DEBUG_SET_STATUS__RAW = str
MCONTR_RD_MASK__RAW = str
LOGGER_CONF_EN = int
FFCLK0_CAPACITANCE = str
MULTICLK_MULT__TYPE = str
SS_EN__TYPE = str
VOSPI_IBUF_LOW_PWR = str
CMDSEQMUX_STATUS = int
SENSI2C_TBL_RNWREG__TYPE = str
MULT_SAXI_ADV_WR__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN__TYPE = str
FRAME_START_ADDRESS_INC = int
TILED_STARTY = int
LOGGER_MASK = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
CMPRS_GROUP_ADDR = int
CAMSYNC_PRE_MAGIC__RAW = str
PXD_CLK_DIV_BITS = int
SENSOR_CHN_EN_BIT = int
LD_DLY_LANE0_ODELAY = int
CMPRS_MONO16__TYPE = str
READ_PATTERN_OFFSET__RAW = str
SENSI2C_TBL_DLY__TYPE = str
LWIR_FRAME_DELAY__TYPE = str
MULTICLK_DIV_XCLK2X__TYPE = str
MEMBRIDGE_SIZE64 = int
SENSOR_IMAGE_TYPE1__RAW = str
MCONTR_PHY_0BIT_CKE_EN__TYPE = str
CMPRS_FRMT_MBCM1_BITS = int
SENS_GAMMA_MODE_REPET_SET__TYPE = str
HISTOGRAM_RAM_MODE__TYPE = str
AFI_LO_ADDR64 = int
HISTOGRAM_RADDR_INC = int
VOSPI_PACKETS_PER_LINE__TYPE = str
NUM_CYCLES_07__TYPE = str
SENS_LENS_FAT0_IN = int
CMPRS_FRMT_LMARG_BITS__TYPE = str
SENSOR12BITS_NGPL__TYPE = str
HISTOGRAM_RADDR1__TYPE = str
CAMSYNC_MASTER_BIT__TYPE = str
HISTOGRAM_ADDR_MASK = int
MCONTR_BUF2_RD_ADDR__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
MULTICLK_DIV_DLYREF__RAW = str
VERBOSE__TYPE = str
BUF_CLK1X_PCLK__TYPE = str
MULT_SAXI_BSLOG1__RAW = str
CLKFBOUT_MULT_PCLK__RAW = str
MCONTR_SENS_STATUS_INC__TYPE = str
LWIR_TELEMETRY_STATUS = int
CAMSYNC_TRIG_DELAY0__TYPE = str
LWIR_DATA_FILE3__RAW = str
SENSI2C_STATUS_REG_INC = int
CLKFBOUT_PHASE__TYPE = str
TABLE_QUANTIZATION_INDEX__RAW = str
MCNTRL_TILED_WINDOW_WH = int
CMDFRAMESEQ_MASK = int
CLK_ADDR = int
MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
MULTICLK_PHASE_FB = float
NUM_XFER_BITS__RAW = str
MCNTRL_TILED_WINDOW_STARTXY__RAW = str
LWIR_TELEMETRY_AGC_ROI_BOTTOM__TYPE = str
CMPRS_CSAT_CB_BITS__RAW = str
CMPRS_CBIT_RUN__RAW = str
SENS_GAMMA_RADDR__RAW = str
SENS_CTRL_EXT_CLK = int
MULT_SAXI_IRQLEN_ADDR__RAW = str
SENSI2C_CMD_ACIVE_EARLY0__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
SENS_GAMMA_BUFFER = int
GPIO_SET_PINS__RAW = str
SENS_CTRL_RST_MMCM__TYPE = str
AFI_MUX_BUF_LATENCY__RAW = str
CMPRS_CBIT_CMODE_JP46__RAW = str
MULTICLK_DIV_SYNC__TYPE = str
LWIR_WINDOW_HEIGHT__RAW = str
MULTICLK_BUF_DLYREF__TYPE = str
GPIO_DRIVE__RAW = str
GPIO_IBUF_LOW_PWR__TYPE = str
SENS_SYNC_FBITS__RAW = str
CMPRS_CORING_MODE__TYPE = str
CMPRS_FRMT_MBRM1_BITS__TYPE = str
MCNTRL_TILED_TILE_WHS__RAW = str
SENS_REFCLK_FREQUENCY = float
CMD_PAUSE_BITS__TYPE = str
SENS_CTRL_EXT_CLK__TYPE = str
SENS_LENS_BY = int
SENS_LENS_BX = int
NUM_CYCLES_02__TYPE = str
MCNTRL_TILED_STARTADDR = int
LWIR_TELEMETRY_TIME_LAST_MS__RAW = str
TILE_HEIGHT__TYPE = str
MULTICLK_DIV_XCLK2X__RAW = str
VOSPI_DBG_SRC = int
MCNTRL_TILED_CHN4_ADDR__TYPE = str
HISPI_NUMLANES__TYPE = str
VOSPI_DBG_SRC__RAW = str
HISPI_FIFO_START = int
TILED_STARTX__TYPE = str
FFCLK0_DIFF_TERM__RAW = str
MCNTRL_PS_STATUS_CNTRL__RAW = str
MCONTR_TOP_STATUS_REG_ADDR = int
SENSOR_TIMING_TO = int
VOSPI_SEGM0_OK__TYPE = str
SDCLK_PHASE = float
SLEW_CMDA = str
SENSOR_IMAGE_TYPE0__RAW = str
CMPRS_STATUS_REG_BASE__RAW = str
MCNTRL_SCANLINE_MODE__TYPE = str
GPIO_N__RAW = str
TEST01_NEXT_PAGE__TYPE = str
CONTROL_RBACK_ADDR = int
T_REFI__RAW = str
MULTICLK_PHASE_SYNC__RAW = str
CLKFBOUT_MULT_SENSOR = int
HISPI_MMCM2__RAW = str
CMPRS_AFIMUX_EN = int
COLADDR_NUMBER = int
MCNTRL_PS_CMD = int
VOSPI_OUT_EN_SINGL = int
LWIR_TELEMETRY_SREV__TYPE = str
TABLE_FOCUS_INDEX__TYPE = str
CAMSYNC_DELAY = int
BUF_IPCLK2X_SENS2__TYPE = str
SENSI2C_CMD_USE_EOF__TYPE = str
MULTICLK_PHASE_AXIHP__RAW = str
VOSPI_MRST_MS = int
QUADRANTS_PXD_HACT_VACT = int
FFCLK0_IOSTANDARD__RAW = str
MULTICLK_DIV_XCLK__RAW = str
DFLT_DQS_TRI_ON_PATTERN__TYPE = str
MCONTR_PHY_0BIT_DLY_RST__TYPE = str
TILED_KEEP_OPEN__RAW = str
AXI_WRADDR_LATENCY__TYPE = str
MULT_SAXI_IRQLEN_ADDR = int
XOR_HIST_BAYER = int
MULTICLK_BUF_XCLK__TYPE = str
MCONTR_TOP_0BIT_ADDR__TYPE = str
VOSPI_VSYNC__RAW = str
CLKFBOUT_PHASE_SENSOR__RAW = str
CMPRS_AFIMUX_REG_ADDR0 = int
MCONTR_SENS_BASE = int
CMPRS_CBIT_RUN__TYPE = str
SENS_LENS_FAT0_OUT = int
MCNTRL_SCANLINE_FRAME_SIZE = int
STATUS_DEPTH = int
NUM_CYCLES_20__RAW = str
MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
VOSPI_IOSTANDARD = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
CAMSYNC_EXTERNAL_BIT__RAW = str
HISTOGRAM_WIDTH = int
VOSPI_SLEW__RAW = str
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str
VOSPI_OUT_EN_SINGL__TYPE = str
SENSOR_TIMING_START__TYPE = str
SENSI2C_CMD_ACIVE_SDA = int
MCONTR_PHY_0BIT_ADDR__TYPE = str
PXD_CLK_DIV_BITS__TYPE = str
MCONTR_CMPRS_INC__RAW = str
CMPRS_HIFREQ_REG_INC__RAW = str
PXD_CLK_DIV__TYPE = str
SENSOR_DATA_WIDTH__RAW = str
SENSI2C_TBL_DLY_BITS__TYPE = str
MEMBRIDGE_MASK = int
SENSI2C_TBL_NBWR_BITS__TYPE = str
DLY_SET__TYPE = str
CMPRS_STATUS_REG_INC = int
FFCLK0_CAPACITANCE__TYPE = str
LAST_FRAME_BITS__TYPE = str
CLK_MASK__RAW = str
DLY_DM_ODELAY = int
MEMBRIDGE_STATUS_CNTRL__RAW = str
VOSPI_SPI_CLK__TYPE = str
DEBUG_SHIFT_DATA = int
LWIR_DATA_FILE4__TYPE = str
MEMBRIDGE_STATUS_REG = int
CMPRS_CBIT_CMODE_JPEG18__RAW = str
IPCLK2X_PHASE = float
VOSPI_OUT_EN_BITS__RAW = str
CMPRS_CBIT_FOCUS_BITS = int
LOGGER_CONF_SYN__RAW = str
CMPRS_COLOR20 = int
SENSI2C_CMD_USE_EOF__RAW = str
SENSI2C_CMD_TABLE__RAW = str
SENSIO_DELAYS__TYPE = str
ADDRESS_NUMBER__TYPE = str
WSEL__TYPE = str
CMPRS_AFIMUX_CYCBITS__RAW = str
MAX_TILE_WIDTH = int
NUM_CYCLES_09__TYPE = str
LD_DLY_LANE0_IDELAY__RAW = str
FRAME_WIDTH_BITS__TYPE = str
SENS_SYNC_LBITS__TYPE = str
NUM_CYCLES_25__RAW = str
SENSOR_NUM_HISTOGRAM__RAW = str
CMPRS_CBIT_CMODE = int
HIST_SAXI_ADDR_MASK__RAW = str
HISPI_WAIT_ALL_LANES__RAW = str
MEMBRIDGE_STATUS_REG__TYPE = str
CLKIN_PERIOD__RAW = str
SENS_SYNC_MULT__RAW = str
SENSOR_TIMING_STATUS_REG_BASE = int
SENSOR_HIST_NRST_BITS__RAW = str
SENS_LENS_BY__TYPE = str
NUM_CYCLES_02__RAW = str
CAMSYNC_GPIO_INT_IN = int
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str
VOSPI_MCLK_BITS__RAW = str
MCNTRL_TILED_WINDOW_X0Y0 = int
MCONTR_TOP_16BIT_REFRESH_PERIOD__RAW = str
MULT_SAXI_WLOG__TYPE = str
STATUS_2LSB_SHFT = int
HISPI_IFD_DELAY_VALUE = str
CMPRS_CBIT_CMODE_JP4DC = int
MULT_SAXI_IRQLEN_MASK = int
NUM_CYCLES_08__TYPE = str
NUM_CYCLES_LOW_BIT__RAW = str
SENSI2C_TBL_NBRD_BITS__TYPE = str
SENS_SYNC_MINBITS = int
MULTICLK_BUF_DLYREF = str
MCNTRL_SCANLINE_WINDOW_STARTXY = int
BUF_IPCLK_SENS2__RAW = str
CMPRS_STATUS_CNTRL__TYPE = str
MCONTR_RD_MASK = int
CMPRS_COLOR_SATURATION = int
NUM_CYCLES_21__RAW = str
MULTICLK_PHASE_DLYREF__RAW = str
SENSIO_DELAYS__RAW = str
CMDFRAMESEQ_RUN_BIT = int
SENS_SYNC_MINPER = int
CMPRS_FRMT_MBRM1__RAW = str
MCONTR_SENS_BASE__TYPE = str
LOGGER_BIT_HALF_PERIOD = int
CMPRS_CBIT_CMODE_JP4 = int
VOSPI_DRIVE__RAW = str
CAMSYNC_TRIGGERED_BIT = int
VOSPI_SPI_CLK_BITS__RAW = str
LOGGER_PAGE_IMU__TYPE = str
LOGGER_PAGE_GPS__RAW = str
SENS_PHASE_WIDTH__TYPE = str
CMPRS_COLOR18__TYPE = str
CMPRS_HIFREQ_REG_INC__TYPE = str
VOSPI_OUT_EN = int
PXD_CLK_DIV = int
MCNTRL_TILED_STATUS_CNTRL = int
NUM_CYCLES_29__RAW = str
GPIO_SET_STATUS__TYPE = str
SENSIO_STATUS_REG_REL__RAW = str
CMPRS_RAW__RAW = str
FFCLK0_CAPACITANCE__RAW = str
SENSOR12BITS_TDDO1__TYPE = str
CMDFRAMESEQ_ABS = int
CMPRS_MONO8 = int
MULT_SAXI_ADDR__RAW = str
DEBUG_CMD_LATENCY__TYPE = str
CAMSYNC_GPIO_EXT_OUT__TYPE = str
TILED_KEEP_OPEN = int
MCNTRL_SCANLINE_MASK__RAW = str
MULT_SAXI_STATUS_REG__RAW = str
MCONTR_LINTILE_EN__RAW = str
SENSI2C_ADDR_MASK__TYPE = str
SENSOR12BITS_NVLO__RAW = str
CAMSYNC_EXTERNAL_BIT__TYPE = str
CMPRS_BASE_INC__RAW = str
SENS_SYNC_FBITS = int
BUF_IPCLK_SENS0__RAW = str
MCNTRL_TEST01_ADDR = int
MCONTR_TOP_0BIT_MCONTR_EN__TYPE = str
MEMBRIDGE_CTRL__TYPE = str
TILED_KEEP_OPEN__TYPE = str
CMPRS_CBIT_RUN_RST__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str
MULTICLK_DIV_SYNC = int
CLK_STATUS_REG_ADDR = int
CLK_DIV_PHASE__TYPE = str
MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str
CLKFBOUT_USE_FINE_PS__RAW = str
VOSPI_SLEW__TYPE = str
GPIO_SET_PINS = int
FRAME_START_ADDRESS__RAW = str
LOGGER_BIT_DURATION = int
FCLK1_PERIOD__TYPE = str
CAMSYNC_MODE__TYPE = str
CHNBUF_READ_LATENCY__RAW = str
NUM_CYCLES_12__RAW = str
CMPRS_CBIT_RUN_BITS__RAW = str
CMPRS_AFIMUX_RST__TYPE = str
LD_DLY_PHASE = int
SENSI2C_CTRL_RADDR__TYPE = str
SENSIO_ADDR_MASK__RAW = str
LOGGER_CONF_EN_BITS = int
NUM_CYCLES_22__RAW = str
PXD_CAPACITANCE__TYPE = str
CAMSYNC_POST_MAGIC = int
PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str
CLK_CNTRL__TYPE = str
GPIO_MASK__RAW = str
DFLT_REFRESH_ADDR__TYPE = str
SENS_GAMMA_MODE_REPET__TYPE = str
SENSOR_TIMING_LANE__TYPE = str
CAMSYNC_TRIG_PERIOD__RAW = str
SENS_BANDWIDTH__RAW = str
CMPRS_CBIT_BE16_BITS__TYPE = str
SENS_SS_EN__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
LOGGER_PERIOD__TYPE = str
WSEL = int
SENS_REFCLK_FREQUENCY__RAW = str
LOGGER_STATUS_MASK__TYPE = str
HISPI_IOSTANDARD = str
LOGGER_CONF_IMU__RAW = str
CMPRS_CBIT_CMODE_JP4DC__RAW = str
MULT_SAXI_IRQLEN_MASK__RAW = str
MCNTRL_TEST01_CHN3_MODE__RAW = str
MCNTRL_TEST01_CHN1_MODE__TYPE = str
SENS_SYNC_FBITS__TYPE = str
HISPI_UNTUNED_SPLIT = str
CMPRS_AFIMUX_REG_ADDR0__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK = int
HISPI_IBUF_DELAY_VALUE__TYPE = str
SENSOR12BITS_NGPL = int
CMDFRAMESEQ_REL = int
CAMSYNC_POST_MAGIC__TYPE = str
NUM_CYCLES_29__TYPE = str
RTC_SET_SEC__TYPE = str
CAMSYNC_ADDR = int
FFCLK1_CAPACITANCE__RAW = str
VOSPI_SPI_SEQ__RAW = str
VOSPI_PACKET_LAST__RAW = str
RTC_SET_CORR__TYPE = str
PHASE_WIDTH__RAW = str
SLEW_DQ__RAW = str
CMPRS_CBIT_CMODE_JPEG20__RAW = str
CLK_STATUS = int
SENSI2C_STATUS_REG_INC__RAW = str
GPIO_ADDR__RAW = str
MEMBRIDGE_START64__TYPE = str
CMPRS_CBIT_CMODE_JP46 = int
MEMCLK_CAPACITANCE__TYPE = str
MCONTR_BUF0_WR_ADDR__RAW = str
HISTOGRAM_TOP = int
SENS_SS_MODE = str
SENSOR12BITS_TDDO = int
CAMSYNC_TRIG_DST = int
DLY_LANE1_ODELAY__TYPE = str
CMPRS_AFIMUX_WIDTH__TYPE = str
TILE_VSTEP__RAW = str
CMPRS_CBIT_QBANK = int
SENSI2C_TBL_RAH_BITS__TYPE = str
LWIR_WINDOW_WIDTH = int
CMPRS_AFIMUX_WIDTH = int
HISTOGRAM_ADDR_MASK__TYPE = str
HISTOGRAM_RADDR3__TYPE = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str
SENSOR_TIMING_START = int
SENSOR_NUM_HISTOGRAM = int
HIST_SAXI_NRESET__RAW = str
CMPRS_COLOR18 = int
LOGGER_CONF_MSG__TYPE = str
MCNTRL_TILED_MASK__RAW = str
MULTICLK_DIV_AXIHP__RAW = str
SENSI2C_CMD_SOFT_SDA__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
SENSI2C_STATUS_REG_BASE = int
MCNTRL_TILED_STATUS_CNTRL__RAW = str
CMPRS_CBIT_BAYER__RAW = str
DFLT_DQS_TRI_OFF_PATTERN = int
SENSIO_JTAG__TYPE = str
VOSPI_NORESYNC__RAW = str
SENSOR_GROUP_ADDR__RAW = str
LOGGER_MASK__TYPE = str
T_RFC = int
FFCLK1_IOSTANDARD__RAW = str
CMD_DONE_BIT__TYPE = str
SENSOR_DATA_WIDTH__TYPE = str
VOSPI_RESET_ERR__RAW = str
RTC_BITC_PREDIV__RAW = str
CMPRS_CORING_BITS__TYPE = str
STATUS_DEPTH__TYPE = str
SENSI2C_TBL_RAH__TYPE = str
CMPRS_AFIMUX_CYCBITS__TYPE = str
HISPI_MSB_FIRST = int
SENS_SS_EN__RAW = str
SENS_LENS_ADDR_MASK = int
SENSOR_CTRL_RADDR__TYPE = str
CMPRS_CBIT_FRAMES_SINGLE__RAW = str
VOSPI_PACKETS_PER_LINE__RAW = str
CLKOUT_DIV_PCLK = int
MCNTRL_SCANLINE_MASK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET__TYPE = str
PXD_IOSTANDARD__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR = int
LAST_BUF_FRAME = int
SENS_REF_JITTER1 = float
SENS_REF_JITTER2 = float
MCNTRL_TILED_FRAME_SIZE__RAW = str
VOSPI_MRST_AFTER_MS = int
MULT_SAXI_HALF_BRAM__RAW = str
SIMUL_AXI_READ_WIDTH__TYPE = str
DFLT_DQS_TRI_ON_PATTERN__RAW = str
LWIR_MS_PERIOD__RAW = str
SLEW_DQ = str
CAMSYNC_GPIO_INT_OUT__TYPE = str
SENS_GAMMA_MODE_REPET__RAW = str
SENSOR_DATA_WIDTH = int
SENSOR_TIMING_LANE__RAW = str
SLEW_DQS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT = int
VOSPI_SEGMENT_LAST__RAW = str
SENSIO_ADDR_MASK = int
TILE_HEIGHT__RAW = str
SCANLINE_STARTY = int
SCANLINE_STARTX = int
SIMULATE_CMPRS_CMODE1__RAW = str
GPIO_DRIVE__TYPE = str
FFCLK0_DIFF_TERM__TYPE = str
HISPI_UNTUNED_SPLIT__TYPE = str
LD_DLY_CMDA__TYPE = str
MCONTR_TOP_0BIT_REFRESH_EN = int
CMPRS_CBIT_RUN_RST = int
IPCLK2X_PHASE__RAW = str
VOSPI_NORESYNC_BITS__TYPE = str
SENSI2C_IOSTANDARD__TYPE = str
SENSOR_TIMING_STATUS_REG_BASE__RAW = str
REFCLK_FREQUENCY__TYPE = str
CLKOUT_DIV_PCLK2X__TYPE = str
MEMBRIDGE_CTRL = int
SENSOR_IMAGE_TYPE3__TYPE = str
HISTOGRAM_LEFT = int
MULT_SAXI_HALF_BRAM__TYPE = str
VOSPI_EN_BITS__RAW = str
MCONTR_PHY_STATUS_CNTRL = int
SENSOR_GROUP_ADDR = int
NUM_CYCLES_14 = int
CMPRS_CBIT_RUN_STANDALONE__TYPE = str
BUF_IPCLK_SENS1__RAW = str
WRITE_BLOCK_OFFSET__TYPE = str
VOSPI_NO_INVALID__TYPE = str
VOSPI_DRIVE__TYPE = str
SENS_SYNC_LATE_DFLT__TYPE = str
CAMSYNC_MODE = int
CLK_MASK__TYPE = str
MCNTRL_SCANLINE_STARTADDR = int
CONTROL_ADDR = int
DQSTRI_FIRST__TYPE = str
MULT_SAXI_HALF_BRAM_IN__TYPE = str
DEBUG_SET_STATUS = int
MCNTRL_SCANLINE_WINDOW_X0Y0 = int
STATUS_ADDR = int
LWIR_DATA_FILE1__TYPE = str
MCNTRL_TILED_STARTADDR__RAW = str
WINDOW_X0__RAW = str
VOSPI_EN__TYPE = str
LWIR_FRAME_PERIOD__RAW = str
CMDFRAMESEQ_IRQ_BIT = int
CONTROL_ADDR__TYPE = str
CLKFBOUT_MULT_PCLK = int
WINDOW_Y0 = int
LOGGER_CONF_GPS_BITS__TYPE = str
CAMSYNC_GPIO_EXT_IN__TYPE = str
SENS_LENS_AX_MASK__TYPE = str
HISTOGRAM_RADDR0 = int
HISTOGRAM_RADDR1 = int
HISTOGRAM_RADDR2 = int
HISTOGRAM_RADDR3 = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
HISTOGRAM_LEFT__TYPE = str
SENS_LENS_AY_MASK__TYPE = str
VOSPI_PACKET_TTT__RAW = str
VOSPI_MRST__RAW = str
SENS_CTRL_IGNORE_EMBED__RAW = str
READ_BLOCK_OFFSET__TYPE = str
CONTROL_ADDR_MASK__RAW = str
LD_DLY_CMDA__RAW = str
SENSI2C_STATUS_REG_REL__RAW = str
NUM_CYCLES_18__TYPE = str
MCNTRL_TEST01_CHN2_MODE = int
MCNTRL_TILED_WINDOW_WH__TYPE = str
SS_MOD_PERIOD__RAW = str
CMPRS_NUM_AFI_CHN__RAW = str
SENSOR_IMAGE_TYPE3 = str
MULTICLK_DIV_AXIHP__TYPE = str
LWIR_FRAME_PERIOD__TYPE = str
HISPI_DELAY_CLK2__TYPE = str
MULT_SAXI_ADV_RD = int
WSEL__RAW = str
SENSOR_PRIORITY = int
DLY_PHASE__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str
MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
BUF_IPCLK_SENS2 = str
BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS1 = str
VOSPI_VSYNC = int
MCNTRL_TEST01_CHN1_MODE__RAW = str
SLEW_CMDA__TYPE = str
MULT_SAXI_CNTRL_MODE__TYPE = str
NUM_CYCLES_19__TYPE = str
CMPRS_CORING_MODE__RAW = str
MEMBRIDGE_ADDR = int
CMPRS_CSAT_CR_BITS__RAW = str
MULTICLK_IN_PERIOD__RAW = str
CMPRS_CBIT_FOCUS = int
FFCLK1_CAPACITANCE__TYPE = str
SENSOR_FIFO_DELAY = int
MULTICLK_PHASE_AXIHP = float
MCNTRL_TEST01_CHN1_STATUS_CNTRL__TYPE = str
WBUF_DLY_DFLT = int
SENS_JTAG_PROG = int
MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
FFCLK0_IOSTANDARD = str
AXI_TASK_HOLD__TYPE = str
SENS_GAMMA_ADDR_MASK__RAW = str
SENSOR_IMAGE_TYPE3__RAW = str
DLY_LANE1_IDELAY__TYPE = str
SENS_LENS_BY_MASK = int
DEBUG_MASK__RAW = str
VOSPI_NORESYNC__TYPE = str
NUM_INTERRUPTS__RAW = str
MCNTRL_TEST01_CHN2_MODE__TYPE = str
MEMBRIDGE_ADDR__RAW = str
LWIR_GPIO_IN = int
CMPRS_COLOR_SATURATION__RAW = str
AXI_RD_ADDR_BITS = int
MULTICLK_IN_PERIOD__TYPE = str
LD_DLY_LANE1_ODELAY__TYPE = str
CMPRS_STATUS_CNTRL__RAW = str
VOSPI_GPIO__TYPE = str
MCONTR_LINTILE_SKIP_LATE = int
SENS_CTRL_ARO = int
LOGGER_CONF_DBG_BITS__TYPE = str
RTC_SEC_USEC_ADDR__TYPE = str
WINDOW_X0__TYPE = str
CMPRS_CBIT_QBANK_BITS = int
MCNTRL_TEST01_CHN1_MODE = int
DLY_CMDA = int
SENS_GAMMA_MODE_BAYER = int
LAST_BUF_FRAME__TYPE = str
CMPRS_HIFREQ_REG_BASE = int
FCLK1_PERIOD__RAW = str
MCONTR_ARBIT_ADDR = int
MEMBRIDGE_CTRL__RAW = str
CMPRS_CBIT_RUN_RST__RAW = str
TABLE_QUANTIZATION_INDEX = int
NUM_CYCLES_04__TYPE = str
SENSOR_IMAGE_TYPE2 = str
SENSOR_IMAGE_TYPE1 = str
SENSOR_IMAGE_TYPE0 = str
SENS_CTRL_IGNORE_EMBED = int
RTC_MASK__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS = int
NUM_CYCLES_00__TYPE = str
VOSPI_MCLK_HALFDIV = int
CMPRS_MASK__RAW = str
MEMBRIDGE_CTRL_IRQ__TYPE = str
MCNTRL_TEST01_MASK__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK = int
CAMSYNC_TRIG_DELAY1__TYPE = str
HIGH_PERFORMANCE_MODE = str
DQTRI_LAST__RAW = str
MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
SIMULATE_CMPRS_CMODE3__TYPE = str
DFLT_DQM_PATTERN = int
HISPI_NUMLANES = int
SENSI2C_CMD_RUN = int
CMPRS_CBIT_BE16_BITS = int
AXI_WRDATA_LATENCY__RAW = str
LWIR_FRAME_PERIOD = int
NUM_CYCLES_04 = int
SENS_LENS_C__TYPE = str
MCONTR_PHY_16BIT_EXTRA__TYPE = str
CAMSYNC_TRIGGERED_BIT__RAW = str
VOSPI_NO_INVALID = int
SENSI2C_CMD_SOFT_SCL__RAW = str
CMPRS_CSAT_CR__TYPE = str
SENS_LENS_POST_SCALE__RAW = str
DLY_LANE1_IDELAY = int
HIST_SAXI_NRESET__TYPE = str
MCNTRL_SCANLINE_CHN1_ADDR__TYPE = str
CMPRS_AFIMUX_SA_LEN__TYPE = str
SENS_LENS_SCALES__RAW = str
MCNTRL_SCANLINE_FRAME_SIZE__TYPE = str
DLY_LANE0_ODELAY__TYPE = str
SENS_LENS_FAT0_IN_MASK = int
CMPRS_CBIT_CMODE_JP4__TYPE = str
LOGGER_CONF_GPS = int
MULT_SAXI_AWCACHE__RAW = str
MCONTR_PHY_0BIT_CKE_EN = int
CMPRS_AFIMUX_STATUS_CNTRL = int
CMPRS_CBIT_FRAMES__RAW = str
SLEW_DQS = str
MCONTR_WR_MASK = int
MCONTR_LINTILE_ABORT_LATE = int
CMPRS_FRMT_MBCM1 = int
MEMBRIDGE_STATUS_CNTRL__TYPE = str
GPIO_IOSTANDARD__TYPE = str
CLKFBOUT_USE_FINE_PS__TYPE = str
CMPRS_FRMT_LMARG = int
CMPRS_AFIMUX_EN__RAW = str
CMPRS_TIMEOUT__RAW = str
MEMCLK_IBUF_LOW_PWR__RAW = str
SENS_LENS_FAT0_OUT_MASK__RAW = str
SENSI2C_CMD_FIFO_RD__RAW = str
RTC_ADDR__TYPE = str
MCONTR_LINTILE_COPY_FRAME__RAW = str
SENSI2C_ABS_RADDR = int
PXD_IOSTANDARD__RAW = str
CMPRS_CBIT_FRAMES = int
SENS_GAMMA_HEIGHT01__RAW = str
CONTROL_RBACK_DEPTH__TYPE = str
CMPRS_CBIT_CMODE_MONO1__RAW = str
MCNTRL_SCANLINE_DLY_DEFAULT__RAW = str
GPIO_PORTEN__TYPE = str
CMDSEQMUX_ADDR__RAW = str
DLY_DM_ODELAY__TYPE = str
SENSIO_CTRL = int
LWIR_TELEMETRY_TEMP_COUTS = int
MULT_SAXI_MASK__TYPE = str
SENSI2C_CMD_ACIVE_SDA__TYPE = str
SCANLINE_STARTY__RAW = str
GPIO_ADDR = int
SENS_SYNC_MINBITS__RAW = str
SENS_SS_MOD_PERIOD__RAW = str
SENSOR_TIMING_TO__RAW = str
COLADDR_NUMBER__TYPE = str
SENSOR_TIMING_FROM = int
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
CAMSYNC_CHN_EN_BIT__RAW = str
LOGGER_PAGE_MSG = int
SENS_HIGH_PERFORMANCE_MODE = str
WINDOW_X0 = int
INITIALIZE_OFFSET__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
IDELAY_VALUE__TYPE = str
SENSOR_IMAGE_TYPE2__RAW = str
CMPRS_CBIT_CMODE_JP4DC__TYPE = str
MULT_SAXI_IRQLEN_ADDR__TYPE = str
MULT_SAXI_IRQLEN_MASK__TYPE = str
PICKLE__TYPE = str
SENSI2C_TBL_NBWR__RAW = str
TABLE_FOCUS_INDEX__RAW = str
MCONTR_LINTILE_WRITE__RAW = str
MCNTRL_TILED_CHN2_ADDR__RAW = str
CMPRS_CONTROL_REG__TYPE = str
SENS_CTRL_ARST__TYPE = str
CMPRS_CBIT_FOCUS__RAW = str
CMPRS_MONO8__TYPE = str
NUM_CYCLES_00__RAW = str
IPCLK_PHASE__RAW = str
SENSI2C_CTRL = int
SENS_SYNC_MULT = int
CLK_ADDR__RAW = str
SENSIO_CTRL__RAW = str
HISTOGRAM_WIDTH__TYPE = str
MCNTRL_TILED_TILE_WHS = int
MCONTR_LINTILE_COPY_FRAME__TYPE = str
VOSPI_GPIO = int
CMPRS_CBIT_BE16__TYPE = str
NUM_CYCLES_03__RAW = str
MULT_SAXI_HALF_BRAM = int
DLY_LANE1_DQS_WLV_IDELAY = int
MULTICLK_PHASE_DLYREF = float
HIST_SAXI_ADDR_REL = int
CMDFRAMESEQ_ADDR_BASE = int
STATUS_SEQ_SHFT__RAW = str
SENS_SS_MODE__TYPE = str
CMPRS_AFIMUX_RADDR0 = int
CMPRS_FRMT_MBCM1_BITS__RAW = str
CMPRS_AFIMUX_REG_ADDR1__TYPE = str
CMPRS_CBIT_FRAMES__TYPE = str
MCONTR_TOP_0BIT_ADDR = int
NUM_CYCLES_05__RAW = str
MCNTRL_TILED_FRAME_LAST__TYPE = str
QUADRANTS_PXD_HACT_VACT__RAW = str
CMPRS_CBIT_ROWS_LSB_BITS__TYPE = str
MCONTR_CMPRS_STATUS_INC__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR = int
TABLE_CORING_INDEX__RAW = str
MCONTR_LINTILE_ABORT_LATE__TYPE = str
SENSI2C_CMD_RESET__TYPE = str
LWIR_DATA_FILE4__RAW = str
VOSPI_NORESYNC_BITS = int
MCONTR_ARBIT_ADDR__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN = int
AXI_TASK_HOLD = float
CMPRS_CBIT_ROWS_LSB__TYPE = str
ADDRESS_NUMBER = int
CAMSYNC_GPIO_EXT_OUT = int
SENSOR_TIMING_FROM__RAW = str
SENS_SYNC_LATE__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
GPIO_STATUS_REG_ADDR__TYPE = str
HIST_SAXI_AWCACHE = int
SENSI2C_CMD_RUN_PBITS = int
CMPRS_MONO8__RAW = str
CMPRS_AFIMUX_REG_ADDR1 = int
SENS_LENS_FAT0_OUT__TYPE = str
SENS_BANDWIDTH__TYPE = str
LD_DLY_LANE0_IDELAY__TYPE = str
CLKFBOUT_PHASE__RAW = str
NUM_CYCLES_08__RAW = str
GPIO_IBUF_LOW_PWR__RAW = str
HISTOGRAM_RADDR3__RAW = str
NUM_XFER_BITS__TYPE = str
LWIR_GPIO_IN__RAW = str
TABLE_QUANTIZATION_INDEX__TYPE = str
BUF_IPCLK2X_SENS2__RAW = str
MCNTRL_TEST01_CHN4_MODE__TYPE = str
MULT_SAXI_ADDR__TYPE = str
CMPRS_CBIT_DCSUB__RAW = str
SENS_LENS_AY__TYPE = str
CMPRS_CBIT_CMODE_JP46DC = int
CAMSYNC_MODE__RAW = str
REFCLK_FREQUENCY = float
STATUS_ADDR_MASK__RAW = str
CMPRS_AFIMUX_MODE = int
DLY_CMDA__RAW = str
BUFFER_DEPTH32__RAW = str
LWIR_TELEMETRY_REV__RAW = str
DIVCLK_DIVIDE__RAW = str
MCNTRL_PS_CMD__RAW = str
VOSPI_PACKET_WORDS__RAW = str
CAMSYNC_ADDR__RAW = str
MCONTR_BUF3_WR_ADDR = int
SENS_NUM_SUBCHN__TYPE = str
REFRESH_OFFSET__RAW = str
HISPI_MMCM0 = str
HISPI_MMCM3 = str
HISPI_MMCM2 = str
MULT_SAXI_CNTRL_ADDR__TYPE = str
HISPI_KEEP_IRST__TYPE = str
MULT_SAXI_STATUS_REG__TYPE = str
CAMSYNC_GPIO_EXT_IN = int
MEMCLK_IOSTANDARD__TYPE = str
NUM_CYCLES_27__TYPE = str
SENSI2C_TBL_NBRD = int
CMPRS_CBIT_BAYER_BITS = int
PXD_SLEW__RAW = str
CAMSYNC_GPIO_INT_OUT = int
MULT_SAXI_STATUS_REG = int
CLKIN_PERIOD_SENSOR__TYPE = str
QUADRANTS_PXD_HACT_VACT__TYPE = str
SENS_GAMMA_MODE_BAYER_SET__RAW = str
SENSOR_PRIORITY__TYPE = str
SENS_LENS_BY__RAW = str
MCNTRL_PS_CMD__TYPE = str
SENS_SYNC_MASK__RAW = str
MEMBRIDGE_START64__RAW = str
SENS_CTRL_QUADRANTS_WIDTH__TYPE = str
SENSI2C_DRIVE = int
NUM_CYCLES_04__RAW = str
SENS_GAMMA_HEIGHT2__RAW = str
MULT_SAXI_POINTERS_REG__TYPE = str
HISPI_DELAY_CLK1 = str
HISPI_DELAY_CLK2 = str
HISPI_DELAY_CLK3 = str
MULT_SAXI_BSLOG0__TYPE = str
DQTRI_FIRST__RAW = str
DIVCLK_DIVIDE__TYPE = str
WBUF_DLY_WLV = int
MCONTR_BUF3_WR_ADDR__RAW = str
MEMBRIDGE_WIDTH64 = int
MCNTRL_TEST01_CHN3_MODE = int
MULTICLK_DIV_DLYREF = int
TABLE_HUFFMAN_INDEX__RAW = str
LD_DLY_PHASE__RAW = str
TEST_INITIAL_BURST__RAW = str
SENSOR_TIMING_FROM__TYPE = str
CMPRS_CBIT_FRAMES_BITS__TYPE = str
CMPRS_FRMT_MBCM1__RAW = str
FFCLK0_DIFF_TERM = str
DIVCLK_DIVIDE_PCLK__TYPE = str
HISPI_FIFO_START__TYPE = str
SENSOR_HIST_EN_BITS = int
DFLT_DQS_TRI_OFF_PATTERN__RAW = str
CMPRS_FRMT_MBRM1 = int
CAMSYNC_SNDEN_BIT__RAW = str
MCONTR_ARBIT_ADDR_MASK__RAW = str
VOSPI_SEGMENT_LAST = int
WINDOW_WIDTH__TYPE = str
MCONTR_CMPRS_STATUS_INC__TYPE = str
DFLT_INV_CLK_DIV = int
DEFAULT_STATUS_MODE__TYPE = str
HISTOGRAM_LEFT_TOP = int
PHASE_CLK2X_PCLK = float
GPIO_SLEW__RAW = str
MULTICLK_PHASE_DLYREF__TYPE = str
TEST01_START_FRAME__RAW = str
CMDFRAMESEQ_ABS__RAW = str
FRAME_WIDTH_ROUND_BITS__TYPE = str
BUF_IPCLK2X_SENS0__RAW = str
VOSPI_SPI_CLK_BITS__TYPE = str
MCONTR_BUF4_WR_ADDR__RAW = str
DFLT_DQM_PATTERN__RAW = str
CMPRS_CSAT_CB__TYPE = str
T_REFI__TYPE = str
MCONTR_CMD_WR_ADDR__TYPE = str
RTC_MASK = int
SENSI2C_CMD_SOFT_SCL__TYPE = str
CLKFBOUT_MULT_SENSOR__RAW = str
CMPRS_CSAT_CR_BITS = int
MCONTR_LINTILE_RST_FRAME__RAW = str
LOGGER_CONFIG__TYPE = str
MCNTRL_SCANLINE_DLY_DEFAULT = int
LWIR_TELEMETRY_AGC_ROI_TOP = int
TEST01_NEXT_PAGE__RAW = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str
LWIR_TELEMETRY_AGC_ROI_TOP__RAW = str
SENSOR12BITS_NVLO__TYPE = str
MCONTR_LINTILE_EXTRAPG__TYPE = str
SENSOR_16BIT_BIT_SET__TYPE = str
NUM_CYCLES_06__TYPE = str
SCANLINE_STARTX__RAW = str
SLEW_DQS__RAW = str
FRAME_HEIGHT_BITS__TYPE = str
CMPRS_CBIT_BAYER__TYPE = str
MCONTR_PHY_0BIT_ADDR = int
AXI_WRADDR_LATENCY = int
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__TYPE = str
MAX_TILE_HEIGHT__TYPE = str
MCONTR_TOP_16BIT_CHN_EN__RAW = str
HISTOGRAM_WIDTH_HEIGHT__RAW = str
WRITELEV_OFFSET__RAW = str
READ_PATTERN_OFFSET = int
CLK_PHASE__TYPE = str
SENSOR_16BIT_BIT = int
MCNTRL_PS_STATUS_REG_ADDR = int
SENS_CTRL_EXT_CLK__RAW = str
SENSOR_CHN_EN_BIT_SET = int
WOI_HEIGHT = int
LOGGER_PAGE_GPS__TYPE = str
T_REFI = int
HIST_CONFIRM_WRITE__TYPE = str
HISTOGRAM_LEFT_TOP__RAW = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__TYPE = str
LOGGER_STATUS_REG_ADDR = int
CMDSEQMUX_ADDR__TYPE = str
DEBUG_STATUS_REG_ADDR = int
SENS_JTAG_TDI__TYPE = str
SENS_GAMMA_MODE_PAGE = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
MCONTR_TOP_16BIT_STATUS_CNTRL__RAW = str
LWIR_TELEMETRY__RAW = str
MCONTR_PHY_0BIT_ADDR_MASK__RAW = str
CAMSYNC_MASTER_BIT = int
DLY_LD_MASK__RAW = str
CMDFRAMESEQ_RST_BIT__TYPE = str
LD_DLY_LANE1_ODELAY = int
NUM_CYCLES_28__RAW = str
LWIR_TELEMETRY_STATUS__TYPE = str
SENS_GAMMA_MODE_PAGE__TYPE = str
CMPRS_COLOR_SATURATION__TYPE = str
SENSI2C_CMD_SOFT_SDA = int
SENSI2C_CMD_TAND = int
CMPRS_AFIMUX_SA_LEN = int
SENS_CTRL_QUADRANTS_EN__TYPE = str
MCNTRL_PS_EN_RST__RAW = str
HISPI_IFD_DELAY_VALUE__TYPE = str
CMPRS_CBIT_BAYER_BITS__RAW = str
MULTICLK_BUF_AXIHP__TYPE = str
GPIO_IOSTANDARD__RAW = str
MEMBRIDGE_MASK__RAW = str
CAMSYNC_GPIO_EXT_IN__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2 = int
RTC_SET_CORR__RAW = str
SENSI2C_TBL_RAH_BITS__RAW = str
TILED_STARTY__TYPE = str
HIGH_PERFORMANCE_MODE__RAW = str
SENSOR_TIMING_BITS__RAW = str
DFLT_DQM_PATTERN__TYPE = str
STATUS_ADDR__TYPE = str
MCONTR_PHY_0BIT_CMDA_EN = int
WOI_WIDTH = int
CMPRS_AFIMUX_WIDTH__RAW = str
BUF_CLK1X_PCLK2X = str
MCNTRL_TEST01_CHN4_MODE = int
HISPI_DQS_BIAS = str
TABLE_FOCUS_INDEX = int
CMPRS_CBIT_RUN_STANDALONE__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = int
DFLT_DQ_TRI_OFF_PATTERN__RAW = str
CMPRS_CBIT_DCSUB = int
CMPRS_CBIT_CMODE_JP4DIFF = int
MULT_SAXI_CNTRL_MASK__TYPE = str
LWIR_DATA_FILE3__TYPE = str
LWIR_TELEMETRY_TEMP_KELVIN = int
VOSPI_GPIO__RAW = str
INITIALIZE_OFFSET__RAW = str
CMD_DONE_BIT__RAW = str
DEBUG_STATUS_REG_ADDR__RAW = str
CMPRS_AFIMUX_RST__RAW = str
SENSOR12BITS_TDDO__RAW = str
CAMSYNC_TRIG_DST__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
CAMSYNC_TRIG_DELAY3__TYPE = str
CMDFRAMESEQ_IRQ_BIT__RAW = str
IPCLK_PHASE = float
SENSI2C_CTRL_RADDR = int
SENSOR_TIMING_TO__TYPE = str
HIST_SAXI_MODE_ADDR_REL__RAW = str
AXI_WRDATA_LATENCY = int
MCNTRL_SCANLINE_START_DELAY = int
SENS_CTRL_QUADRANTS_EN = int
MCNTRL_SCANLINE_WINDOW_WH__RAW = str
MULTICLK_PHASE_FB__TYPE = str
SENSI2C_TBL_NBWR_BITS = int
VOSPI_RST_SEQ__TYPE = str
BUF_IPCLK2X_SENS2 = str
BUF_IPCLK2X_SENS3 = str
BUF_IPCLK2X_SENS0 = str
BUF_IPCLK2X_SENS1 = str
LOGGER_CONFIG = int
DLY_LD__RAW = str
HISPI_MMCM3__TYPE = str
NUM_CYCLES_12__TYPE = str
MCONTR_LINTILE_EXTRAPG = int
MEMCLK_IOSTANDARD = str
DLY_LANE1_ODELAY__RAW = str
SENSI2C_IBUF_LOW_PWR__RAW = str
SENSI2C_STATUS_REG_REL = int
AXI_RDADDR_LATENCY__RAW = str
SENSOR_CTRL_ADDR_MASK = int
SENS_GAMMA_MODE_BAYER_SET = int
NUM_CYCLES_16__TYPE = str
SS_MODE = str
CMDFRAMESEQ_MASK__RAW = str
SENSOR12BITS_TMD__TYPE = str
SENS_CTRL_LD_DLY__TYPE = str
MCONTR_TOP_16BIT_ADDR__TYPE = str
PXD_SLEW = str
VOSPI_DBG_SRC_BITS__TYPE = str
MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
TEST01_SUSPEND = int
NUM_FRAME_BITS = int
LOGGER_STATUS_REG_ADDR__RAW = str
CMPRS_CBIT_FRAMES_BITS__RAW = str
MCNTRL_TILED_MASK__TYPE = str
DEBUG_MASK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN = int
SENSI2C_CMD_ACIVE = int
CMPRS_FRMT_LMARG__TYPE = str
LWIR_TELEMETRY_TIME_LAST_MS__TYPE = str
SENSI2C_TBL_NBRD_BITS = int
SENSIO_JTAG = int
DLY_LD = int
CMPRS_CBIT_FRAMES_SINGLE = int
SENS_SYNC_LATE = int
MEMBRIDGE_CTRL_IRQ = int
CMDFRAMESEQ_CTRL__RAW = str
SENSIO_DELAYS = int
MULTICLK_BUF_SYNC = str
MCONTR_BUF0_RD_ADDR__TYPE = str
CMPRS_STATUS_REG_INC__TYPE = str
DLY_LANE0_IDELAY__TYPE = str
MCNTRL_PS_ADDR__TYPE = str
VOSPI_SPI_TIMEOUT_MS = int
WINDOW_WIDTH__RAW = str
MULTICLK_MULT__RAW = str
MCONTR_PHY_16BIT_ADDR__RAW = str
SENS_CTRL_MRST__RAW = str
SENS_GAMMA_HEIGHT2__TYPE = str
VOSPI_GPIO_BITS__TYPE = str
IPCLK2X_PHASE__TYPE = str
SENSOR_HIST_BITS_SET = int
CLK_MASK = int
MCNTRL_SCANLINE_CHN1_ADDR = int
VOSPI_MCLK__TYPE = str
MULT_SAXI_HALF_BRAM_IN = int
CMDFRAMESEQ_ADDR_INC__RAW = str
IPCLK_PHASE__TYPE = str
NUM_CYCLES_18__RAW = str
NUM_CYCLES_13__TYPE = str
MCONTR_WR_MASK__RAW = str
MCNTRL_TILED_WINDOW_STARTXY = int
MCONTR_TOP_0BIT_MCONTR_EN = int
SENS_LENS_BX__TYPE = str
LOGGER_CONF_GPS__RAW = str
SENS_GAMMA_MODE_TRIG__RAW = str
RTC_SET_CORR = int
CMPRS_CBIT_FOCUS__TYPE = str
CMPRS_NUM_AFI_CHN__TYPE = str
CMPRS_GROUP_ADDR__RAW = str
CAMSYNC_GPIO_INT_IN__TYPE = str
SENS_LENS_AX__RAW = str
CMPRS_JP4DIFF__RAW = str
SENS_SS_MODE__RAW = str
CAMSYNC_SNDEN_BIT__TYPE = str
DEBUG_CMD_LATENCY__RAW = str
CMPRS_CBIT_CMODE__TYPE = str
CAMSYNC_GPIO_INT_OUT__RAW = str
LOGGER_STATUS_MASK = int
MULTICLK_PHASE_XCLK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN__RAW = str
HISPI_CAPACITANCE = str
HISTOGRAM_START_PAGE__RAW = str
CONTROL_ADDR_MASK = int
LOGGER_PERIOD = int
MEMCLK_PERIOD__RAW = str
MCONTR_BUF0_WR_ADDR = int
MCNTRL_PS_STATUS_REG_ADDR__RAW = str
LOGGER_STATUS_MASK__RAW = str
RTC_ADDR__RAW = str
CMPRS_CBIT_FOCUS_BITS__RAW = str
CMDFRAMESEQ_RUN_BIT__TYPE = str
VOSPI_GPIO_BITS__RAW = str
MCNTRL_TILED_STATUS_CNTRL__TYPE = str
SENSI2C_CTRL__RAW = str
MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
SENS_CTRL_GP0__RAW = str
SENSI2C_CMD_USE_EOF = int
MCONTR_BUF2_WR_ADDR__RAW = str
MULT_SAXI_BSLOG0 = int
MULT_SAXI_BSLOG1 = int
MULT_SAXI_BSLOG2 = int
MULT_SAXI_BSLOG3 = int
MCONTR_BUF4_RD_ADDR__RAW = str
SENS_SS_MOD_PERIOD = int
DQSTRI_FIRST = int
VOSPI_HACT_TO_HACT_EOF = int
SENS_REF_JITTER2__RAW = str
SCANLINE_EXTRA_PAGES__RAW = str
CMDSEQMUX_STATUS__RAW = str
MCONTR_PHY_0BIT_SDRST_ACT__RAW = str
SENSOR_IMAGE_TYPE0__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__RAW = str
DIVCLK_DIVIDE_PCLK = int
SENSOR_TIMING_STATUS_REG_INC__TYPE = str
MCNTRL_PS_MASK = int
SENSI2C_STATUS__TYPE = str
CMPRS_CSAT_CB_BITS = int
SENSI2C_TBL_NBRD__RAW = str
HISPI_IBUF_DELAY_VALUE = str
SENSI2C_IOSTANDARD = str
GPIO_IOSTANDARD = str
MCNTRL_SCANLINE_WINDOW_X0Y0__RAW = str
SENS_SYNC_MINPER__TYPE = str
SENSI2C_CTRL_RADDR__RAW = str
SENS_SYNC_LATE_DFLT__RAW = str
MCONTR_LINTILE_DIS_NEED__RAW = str
MCONTR_LINTILE_WRITE__TYPE = str
CAMSYNC_MASTER_BIT__RAW = str
MEMBRIDGE_STATUS_CNTRL = int
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR = int
GPIO_SET_PINS__TYPE = str
CONTROL_RBACK_ADDR__TYPE = str
CMPRS_CORING_BITS__RAW = str
CMDFRAMESEQ_RST_BIT = int
CAMSYNC_SNDEN_BIT = int
DQSTRI_FIRST__RAW = str
SENSI2C_CTRL_MASK__TYPE = str
LWIR_TELEMETRY_SREV = int
VOSPI_SPI_TIMEOUT_MS__RAW = str
SENS_LENS_SCALES__TYPE = str
SENS_LENS_COEFF__TYPE = str
LOGGER_STATUS__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN__RAW = str
SENS_JTAG_TMS__RAW = str
VOSPI_RESET_ERR = int
FRAME_WIDTH_ROUND_BITS__RAW = str
FFCLK0_IBUF_LOW_PWR__RAW = str
SENS_CTRL_MRST = int
MCNTRL_SCANLINE_FRAME_LAST__TYPE = str
MCONTR_SENS_STATUS_BASE__RAW = str
MCNTRL_TEST01_CHN3_MODE__TYPE = str
MCONTR_BUF2_RD_ADDR__TYPE = str
SENS_SYNC_RADDR__RAW = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
VOSPI_MRST_AFTER_MS__RAW = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
CLKFBOUT_PHASE_SENSOR__TYPE = str
SENSOR_HIST_NRST_BITS__TYPE = str
GPIO_PORTEN = int
RTC_STATUS_REG_ADDR__TYPE = str
SENS_JTAG_TCK__TYPE = str
VOSPI_SPI_TIMEOUT_MS__TYPE = str
MCNTRL_TILED_FRAME_SIZE__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str
WOI_HEIGHT__RAW = str
SIMULATE_CMPRS_CMODE1__TYPE = str
SENS_LENS_COEFF = int
MULTICLK_PHASE_XCLK__RAW = str
SENSOR_CHN_EN_BIT_SET__TYPE = str
MCNTRL_SCANLINE_DLY_WIDTH__TYPE = str
MCONTR_WR_MASK__TYPE = str
SENS_LENS_C__RAW = str
CMDFRAMESEQ_ADDR_BASE__TYPE = str
AXI_WRDATA_LATENCY__TYPE = str
SENS_GAMMA_HEIGHT01 = int
RTC_SET_SEC__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
SS_MODE__RAW = str
MCNTRL_SCANLINE_CHN3_ADDR = int
NUM_CYCLES_26__RAW = str
DEFAULT_STATUS_MODE__RAW = str
MCONTR_LINTILE_KEEP_OPEN__RAW = str
VOSPI_MRST_AFTER_MS__TYPE = str
MCONTR_PHY_16BIT_ADDR__TYPE = str
VOSPI_PACKET_TTT__TYPE = str
CMDFRAMESEQ_RST_BIT__RAW = str
SENSIO_RADDR__RAW = str
DFLT_CHN_EN__TYPE = str
MCONTR_PHY_0BIT_ADDR__RAW = str
MCLK_PHASE = float
CMPRS_INTERRUPTS = int
SENSI2C_SLEW__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
MEMCLK_CAPACITANCE__RAW = str
DQTRI_FIRST = int
CONTROL_RBACK_DEPTH = int
CAMSYNC_TRIG_DELAY0 = int
CAMSYNC_TRIG_DELAY1 = int
CAMSYNC_TRIG_DELAY2 = int
CAMSYNC_TRIG_DELAY3 = int
SIMUL_AXI_READ_WIDTH__RAW = str
MCONTR_SENS_STATUS_INC = int
CAMSYNC_GPIO_INT_IN__RAW = str
CMPRS_CBIT_BE16__RAW = str
VOSPI_IOSTANDARD__TYPE = str
SENS_GAMMA_MODE_TRIG__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY__RAW = str
CMPRS_FRMT_LMARG_BITS__RAW = str
LWIR_TELEMETRY_TIME_LAST_MS = int
MEMBRIDGE_ADDR__TYPE = str
LAST_FRAME_BITS = int
SENSOR_FIFO_2DEPTH__RAW = str
CMPRS_COLOR20__RAW = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__RAW = str
WINDOW_Y0__TYPE = str
SENSI2C_CTRL__TYPE = str
LOGGER_PAGE_MSG__RAW = str
MCONTR_TOP_16BIT_STATUS_CNTRL = int
CMPRS_CBIT_CMODE_MONO4__RAW = str
MULT_SAXI_MASK = int
SENS_LENS_BX_MASK__TYPE = str
MCNTRL_SCANLINE_WINDOW_STARTXY__TYPE = str
CMDFRAMESEQ_DEPTH__TYPE = str
LWIR_TELEMETRY_VIDEO_FORMAT__TYPE = str
DLY_LANE0_IDELAY__RAW = str
HISPI_UNTUNED_SPLIT__RAW = str
HISTOGRAM_RADDR1__RAW = str
SENSI2C_CMD_TAND__TYPE = str
MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
HISTOGRAM_HEIGHT__RAW = str
SENSOR_TIMING_BITS = int
MCNTRL_SCANLINE_MODE__RAW = str
LOGGER_BIT_HALF_PERIOD__TYPE = str
VOSPI_OUT_EN_SINGL__RAW = str
FRAME_START_ADDRESS_INC__RAW = str
SENSOR12BITS_TDDO__TYPE = str
LWIR_TELEMETRY_AGC_ROI_LEFT__TYPE = str
CLKIN_PERIOD = int
RSEL__TYPE = str
CMDFRAMESEQ_ADDR_INC__TYPE = str
LOGGER_CONF_GPS_BITS = int
HISPI_FIFO_DEPTH = int
CLKFBOUT_PHASE = float
SENS_GAMMA_ADDR_DATA = int
HISPI_WAIT_ALL_LANES = int
MULT_SAXI_CNTRL_MODE__RAW = str
SENS_GAMMA_ADDR_DATA__TYPE = str
VOSPI_OUT_EN__TYPE = str
CAMSYNC_DELAY__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
SENS_REF_JITTER1__TYPE = str
SENS_LENS_RADDR__RAW = str
MCONTR_PHY_0BIT_DCI_RST__TYPE = str
HISPI_DQS_BIAS__RAW = str
MCONTR_LINTILE_WRITE = int
TILE_VSTEP__TYPE = str
MCONTR_PHY_STATUS_CNTRL__RAW = str
VOSPI_MRST_MS__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY = int
MCNTRL_SCANLINE_STATUS_CNTRL = int
CMDSEQMUX_MASK__TYPE = str
SENSI2C_CMD_RESET = int
SENSI2C_TBL_NABRD__TYPE = str
NUM_CYCLES_01__RAW = str
WINDOW_HEIGHT__RAW = str
GPIO_IBUF_LOW_PWR = str
DQTRI_LAST = int
SENSI2C_CTRL_MASK = int
PHASE_CLK2X_PCLK__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__TYPE = str
MCONTR_TOP_0BIT_ADDR__RAW = str
HISPI_IBUF_LOW_PWR = str
SENS_GAMMA_MODE_REPET_SET = int
HISPI_KEEP_IRST__RAW = str
LOGGER_CONF_DBG__TYPE = str
AFI_SIZE64__RAW = str
SENSI2C_TBL_RNWREG = int
STATUS_PSHIFTER_RDY_MASK = int
SENSI2C_CMD_FIFO_RD__TYPE = str
SENS_LENS_C_MASK__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST__RAW = str
SENSI2C_CMD_ACIVE_EARLY0 = int
SENS_PHASE_WIDTH__RAW = str
SENS_REF_JITTER2__TYPE = str
FFCLK0_IBUF_LOW_PWR = str
DFLT_DQ_TRI_ON_PATTERN__TYPE = str
FRAME_WIDTH_ROUND_BITS = int
VOSPI_MCLK_BITS__TYPE = str
LD_DLY_LANE1_IDELAY__TYPE = str
CMPRS_AFIMUX_MODE__TYPE = str
DQTRI_FIRST__TYPE = str
MCNTRL_SCANLINE_FRAME_SIZE__RAW = str
CMPRS_CBIT_CMODE_BITS = int
TEST01_START_FRAME__TYPE = str
MULT_SAXI_CNTRL_ADDR__RAW = str
FFCLK1_IOSTANDARD__TYPE = str
CAMSYNC_TRIG_DELAY2__RAW = str
MCNTRL_TEST01_CHN4_MODE__RAW = str
DLY_CMDA__TYPE = str
CLKFBOUT_MULT__TYPE = str
DEBUG_MASK = int
MCONTR_PHY_0BIT_CMDA_EN__RAW = str
SENS_GAMMA_MODE_PAGE_SET__TYPE = str
IDELAY_VALUE = int
DQSTRI_LAST__TYPE = str
HISTOGRAM_RADDR2__TYPE = str
SENS_JTAG_PROG__TYPE = str
TILE_VSTEP = int
DFLT_DQS_TRI_OFF_PATTERN__TYPE = str
CAMSYNC_EN_BIT__RAW = str
SENSIO_WIDTH = int
MCONTR_PHY_0BIT_DLY_RST__RAW = str
BUF_CLK1X_PCLK2X__RAW = str
MULT_SAXI_POINTERS_REG = int
MCONTR_TOP_0BIT_REFRESH_EN__RAW = str
SENSI2C_TBL_RAH = int
SENS_LENS_FAT0_OUT__RAW = str
SENSI2C_ADDR_MASK__RAW = str
SENS_HIGH_PERFORMANCE_MODE__TYPE = str
TEST01_SUSPEND__TYPE = str
NUM_CYCLES_15__RAW = str
DLY_DQ_IDELAY = int
CLKFBOUT_USE_FINE_PS = int
MCNTRL_TEST01_ADDR__TYPE = str
CMPRS_STATUS_REG_BASE = int
MCONTR_LINTILE_NRESET = int
CMPRS_CBIT_RUN_BITS = int
SENS_LENS_AY_MASK = int
BUF_IPCLK2X_SENS3__RAW = str
MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
MULTICLK_DIV_XCLK__TYPE = str
HISPI_MMCM2__TYPE = str
SENSOR_NUM_HISTOGRAM__TYPE = str
HIST_SAXI_EN = int
RTC_SET_SEC = int
MCONTR_LINTILE_SINGLE__TYPE = str
DLY_DQ_IDELAY__RAW = str
MCONTR_LINTILE_ABORT_LATE__RAW = str
SENSOR_CTRL_RADDR__RAW = str
CMPRS_MONO16 = int
CONTROL_ADDR__RAW = str
SENSI2C_TBL_DLY = int
SENSIO_STATUS__RAW = str
SENSOR_16BIT_BIT_SET = int
MCONTR_LINTILE_DIS_NEED = int
SENS_LENS_BX_MASK = int
HISPI_FIFO_START__RAW = str
DLY_DQ_ODELAY__RAW = str
MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
CMPRS_CORING_BITS = int
CMDFRAMESEQ_MASK__TYPE = str
FFCLK1_IOSTANDARD = str
CMPRS_RAW = int
CLK_PHASE__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
GPIO_MASK__TYPE = str
CMPRS_CBIT_ROWS_LSB_BITS__RAW = str
MULT_SAXI_BSLOG2__TYPE = str
TILED_STARTX = int
MEMBRIDGE_MASK__TYPE = str
SENS_GAMMA_MODE_EN = int
MCONTR_BUF3_RD_ADDR = int
NUM_CYCLES_28__TYPE = str
NUM_CYCLES_31__TYPE = str
HISPI_CAPACITANCE__RAW = str
CMPRS_CBIT_BE16_BITS__RAW = str
CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
HISPI_DIFF_TERM__RAW = str
BUF_IPCLK_SENS2__TYPE = str
SENSOR_FIFO_DELAY__TYPE = str
CMDFRAMESEQ_ABS__TYPE = str
NUM_CYCLES_06__RAW = str
SENS_JTAG_TDI = int
CMPRS_JP4 = int
CAMSYNC_CHN_EN_BIT = int
SENSIO_STATUS_REG_REL__TYPE = str
MULTICLK_BUF_XCLK = str
VOSPI_MRST__TYPE = str
HISTOGRAM_START_PAGE__TYPE = str
MCNTRL_SCANLINE_MODE = int
DLY_LANE0_IDELAY = int
VOSPI_SEGMENT_FIRST__RAW = str
DEBUG_SHIFT_DATA__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
STATUS_2LSB_SHFT__RAW = str
VOSPI_PACKET_TTT = int
CLK_DIV_PHASE__RAW = str
STATUS_MSB_RSHFT__RAW = str
SLEW_CMDA__RAW = str
HISPI_MMCM0__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI = int
MCONTR_TOP_STATUS_REG_ADDR__RAW = str
DFLT_DQS_TRI_ON_PATTERN = int
SENSI2C_REL_RADDR = int
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__RAW = str
DFLT_CHN_EN = int
GPIO_STATUS_REG_ADDR__RAW = str
DLY_DQS_ODELAY = int
SENSOR_CHN_EN_BIT__RAW = str
VOSPI_MRST_MS__RAW = str
CMPRS_AFIMUX_RADDR1 = int
CAMSYNC_TRIG_SRC__TYPE = str
SENSI2C_CMD_FIFO_RD = int
LOGGER_CONF_IMU__TYPE = str
DEBUG_READ_REG_ADDR__RAW = str
SENS_LENS_AY__RAW = str
SS_EN = str
LWIR_TELEMETRY_AGC_ROI_LEFT__RAW = str
SENSI2C_CMD_TAND__RAW = str
WINDOW_HEIGHT__TYPE = str
SENSOR_IMAGE_TYPE2__TYPE = str
IBUF_LOW_PWR__TYPE = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
CLK_DIV_PHASE = float
VOSPI_MRST = int
MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
SENS_CTRL_ARO__RAW = str
BUF_IPCLK2X_SENS0__TYPE = str
MULTICLK_BUF_SYNC__RAW = str
MCONTR_PHY_0BIT_DLY_SET__RAW = str
NUM_CYCLES_11__RAW = str
SENS_GAMMA_MODE_REPET_SET__RAW = str
SENSI2C_DRIVE__RAW = str
LWIR_WINDOW_HEIGHT = int
SENSOR_HIST_BITS_SET__TYPE = str
HISPI_MMCM1 = str
LWIR_TELEMETRY_AGC_HIGH__TYPE = str
SENS_LENS_C = int
SENSOR_CTRL_ADDR_MASK__RAW = str
DFLT_CHN_EN__RAW = str
NUM_CYCLES_LOW_BIT = int
READ_BLOCK_OFFSET = int
RSEL__RAW = str
VOSPI_TELEMETRY = int
LWIR_FRAME_DELAY__RAW = str
VOSPI_SEGM0_OK_BITS__TYPE = str
SDCLK_PHASE__TYPE = str
NUM_CYCLES_31__RAW = str
LWIR_TELEMETRY_REV__TYPE = str
SENSI2C_IBUF_LOW_PWR__TYPE = str
SENS_LENS_POST_SCALE_MASK__TYPE = str
SCANLINE_STARTY__TYPE = str
VOSPI_PACKET_WORDS__TYPE = str
SENS_LENS_SCALES_MASK = int
LOGGER_PAGE_MSG__TYPE = str
CAMSYNC_MASK__RAW = str
RTC_MHZ__TYPE = str
MEMBRIDGE_START64 = int
MEMBRIDGE_LO_ADDR64 = int
CMPRS_AFIMUX_EN__TYPE = str
CMPRS_BASE_INC__TYPE = str
SENSI2C_CMD_ACIVE__TYPE = str
NUM_FRAME_BITS__TYPE = str
CLKFBOUT_MULT_SENSOR__TYPE = str
MCONTR_LINTILE_BYTE32 = int
SENSI2C_TBL_SA = int
SENSI2C_CTRL_MASK__RAW = str
SENSI2C_TBL_NABRD = int
CLK_CNTRL = int
SENSI2C_TBL_NABRD__RAW = str
MULTICLK_PHASE_XCLK = float
LOGGER_ADDR__TYPE = str
NUM_CYCLES_15__TYPE = str
MCNTRL_TILED_MODE__RAW = str
SENSOR_TIMING_START__RAW = str
NUM_CYCLES_23__TYPE = str
MCNTRL_TILED_MODE__TYPE = str
MULTICLK_IN_PERIOD = int
MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
MULTICLK_PHASE_FB__RAW = str
TABLE_HUFFMAN_INDEX__TYPE = str
SENS_GAMMA_MODE_EN_SET__TYPE = str
CMPRS_CBIT_ROWS_LSB = int
RTC_SET_STATUS__RAW = str
SENS_CTRL_QUADRANTS = int
LD_DLY_PHASE__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
CMPRS_INTERRUPTS__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
CMDSEQMUX_MASK__RAW = str
DFLT_WBUF_DELAY = int
CONTROL_RBACK_ADDR_MASK__RAW = str
AXI_WR_ADDR_BITS__TYPE = str
RTC_SET_STATUS = int
SENSOR_HIST_EN_BITS__RAW = str
MULT_SAXI_ADV_WR__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
FRAME_FULL_WIDTH = int
VOSPI_SOF_TO_HACT__TYPE = str
CMPRS_AFIMUX_REG_ADDR0__RAW = str
CMPRS_FRMT_LMARG__RAW = str
NUM_CYCLES_22__TYPE = str
DLY_PHASE__RAW = str
MCONTR_SENS_INC__RAW = str
MULT_SAXI_WLOG__RAW = str
TILE_WIDTH__RAW = str
CMPRS_FORMAT__RAW = str
LWIR_TELEMETRY_TEMP_COUTS__RAW = str
CLKIN_PERIOD_SENSOR = float
SENS_GAMMA_CTRL__TYPE = str
HIST_CONFIRM_WRITE__RAW = str
SENS_CTRL_ARST = int
LD_DLY_LANE1_IDELAY__RAW = str
MEMBRIDGE_STATUS_REG__RAW = str
CMDFRAMESEQ_DEPTH__RAW = str
SENS_LENS_BX_MASK__RAW = str
SENSI2C_TBL_NBWR_BITS__RAW = str
WRITE_BLOCK_OFFSET__RAW = str
SENS_GAMMA_MODE_EN_SET = int
MCONTR_LINTILE_SINGLE__RAW = str
MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str
VOSPI_MCLK_HALFDIV__TYPE = str
SENS_GAMMA_BUFFER__TYPE = str
SLEW_DQ__TYPE = str
MCONTR_BUF4_RD_ADDR = int
MCNTRL_PS_MASK__TYPE = str
SENSOR_TIMING_STATUS_REG_BASE__TYPE = str
LWIR_MS_PERIOD__TYPE = str
DIVCLK_DIVIDE_PCLK__RAW = str
LWIR_TELEMETRY_VIDEO_FORMAT__RAW = str
HISPI_DELAY_CLK3__TYPE = str
MCONTR_LINTILE_BYTE32__TYPE = str
VOSPI_HACT_TO_HACT_EOF__TYPE = str
CMPRS_TABLES__RAW = str
SENS_GAMMA_MODE_EN__TYPE = str
CMDFRAMESEQ_IRQ_BIT__TYPE = str
VOSPI_DBG_SRC__TYPE = str
MCONTR_BUF4_WR_ADDR__TYPE = str
MCNTRL_TILED_CHN2_ADDR = int
LWIR_TELEMETRY_AGC_ROI_BOTTOM__RAW = str
CAMSYNC_MASK = int
COLADDR_NUMBER__RAW = str
STATUS_SEQ_SHFT = int
SENS_GAMMA_BUFFER__RAW = str
MULT_SAXI_AWCACHE__TYPE = str
NUM_CYCLES_05__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS__TYPE = str
SENSI2C_TBL_NBWR__TYPE = str
AXI_WR_ADDR_BITS = int
FFCLK1_IBUF_LOW_PWR__RAW = str
MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int
CMPRS_INTERRUPTS__TYPE = str
LWIR_TELEMETRY = int
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
WOI_HEIGHT__TYPE = str
STATUS_SEQ_SHFT__TYPE = str
MCONTR_CMPRS_BASE = int
DEBUG_SET_STATUS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__TYPE = str
HISTOGRAM_START_PAGE = int
VOSPI_MCLK_BITS = int
RTC_SEC_USEC_ADDR__RAW = str
MCNTRL_PS_ADDR = int
SENS_BANDWIDTH = str
MEMCLK_IBUF_LOW_PWR = str
HISPI_DELAY_CLK3__RAW = str
CAMSYNC_TRIG_DST__TYPE = str
CMPRS_AFIMUX_RADDR1__TYPE = str
MCONTR_PHY_STATUS_CNTRL__TYPE = str
MULT_SAXI_WLOG = int
DLY_CMDA_ODELAY__RAW = str
SENSOR_GROUP_ADDR__TYPE = str
MCONTR_BUF2_RD_ADDR = int
MCNTRL_TILED_FRAME_SIZE = int
GPIO_SET_STATUS = int
CLKOUT_DIV_PCLK2X = int
VOSPI_PACKET_FIRST = int
MULT_SAXI_ADDR = int
VOSPI_SPI_CLK__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
SENS_CTRL_ODD = int
VOSPI_OUT_EN_BITS__TYPE = str
SENSOR_BASE_INC = int
MULT_SAXI_CNTRL_MASK__RAW = str
VOSPI_SOF_TO_HACT__RAW = str
SENSI2C_REL_RADDR__RAW = str
MCONTR_ARBIT_ADDR__RAW = str
MCONTR_LINTILE_EN__TYPE = str
SENSI2C_REL_RADDR__TYPE = str
AXI_WRADDR_LATENCY__RAW = str
GPIO_DRIVE = int
HISPI_MSB_FIRST__RAW = str
SENS_LENS_SCALES = int
CONTROL_ADDR_MASK__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__RAW = str
REF_JITTER1 = float
SENSOR_BASE_INC__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
SENS_DIVCLK_DIVIDE__TYPE = str
VOSPI_PACKET_FIRST__TYPE = str
LOGGER_CONF_MSG_BITS = int
SENS_GAMMA_RADDR__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR__RAW = str
CMPRS_CBIT_CMODE_MONO1 = int
CMPRS_CBIT_CMODE_MONO6 = int
SENS_SS_EN = str
CMPRS_CBIT_CMODE_MONO4 = int
HISPI_DELAY_CLK2__RAW = str
SS_MOD_PERIOD__TYPE = str
TILE_HEIGHT = int
MULT_SAXI_MASK__RAW = str
SENSOR12BITS_TMD = int
MCONTR_CMPRS_STATUS_BASE__TYPE = str
NUM_CYCLES_10__RAW = str
CMPRS_TABLES__TYPE = str
VOSPI_SPI_CLK = int
DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str
SENS_NUM_SUBCHN = int
FRAME_HEIGHT_BITS = int
MCONTR_BUF0_WR_ADDR__TYPE = str
SENSOR_CHN_EN_BIT__TYPE = str
CMPRS_COLOR18__RAW = str
LOGGER_STATUS = int
CMDFRAMESEQ_RUN_BIT__RAW = str
py393/x393_export_c.py
View file @ 043d4849
......@@ -324,7 +324,8 @@ class X393ExportC(object):
stypedefs += self.get_typedef32(comment = "Sensor/multiplexer I/O pins status",
data = [self._enc_status_sens_io(),
self._enc_status_sens_io_hispi(),
self._enc_status_sens_io_vospi()],
self._enc_status_sens_io_vospi(),
self._enc_status_sens_io_boson()],
name = "x393_status_sens_io", typ="ro",
frmt_spcs = frmt_spcs)
......@@ -434,7 +435,8 @@ class X393ExportC(object):
stypedefs += self.get_typedef32(comment = "Sensor port I/O control",
data = [self._enc_sensio_ctrl_par12(),
self._enc_sensio_ctrl_hispi(),
self._enc_sensio_ctrl_vospi()],
self._enc_sensio_ctrl_vospi(),
self._enc_sensio_ctrl_boson()],
name = "x393_sensio_ctl", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA",
......@@ -450,12 +452,14 @@ class X393ExportC(object):
"""
stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 0 (different meanings for different sensor types)",
data = [self._enc_sensio_par12_tim0(),
self._enc_sensio_hispi_tim0()],
self._enc_sensio_hispi_tim0(),
self._enc_sensio_boson_tim0()],
name = "x393_sensio_tim0", typ="rw",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 1 (different meanings for different sensor types)",
data = [self._enc_sensio_par12_tim1(),
self._enc_sensio_hispi_tim1()],
self._enc_sensio_hispi_tim1(),
self._enc_sensio_boson_tim1()],
name = "x393_sensio_tim1", typ="rw",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 2 (different meanings for different sensor types)",
......@@ -1898,6 +1902,25 @@ class X393ExportC(object):
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_io_boson(self):
dw=[]
dw.append(("ps_out", 0, 8,0, "Sensor MMCM current phase"))
dw.append(("ps_rdy", 8, 1,0, "Sensor MMCM phase ready"))
dw.append(("perr", 9, 1,0, "Parity error in video stream"))
dw.append(("clkfb_pxd_stopped_mmcm",10, 1,0, "Sensor MMCM feedback clock stopped"))
dw.append(("clkin_pxd_stopped_mmcm",11, 1,0, "Sensor MMCM input clock stopped"))
dw.append(("locked_pxd_mmcm", 12, 1,0, "Sensor MMCM locked"))
dw.append(("hact_alive", 13, 1,0, "HACT signal from the sensor (or internal) is toggling"))
dw.append(("recv_prgrs", 14, 1,0, "UART packet receive in progress"))
dw.append(("recv_dav", 15, 1,0, "Byte available in received UART packet"))
dw.append(("recv_data", 16, 8,0, "Received UART data byte"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("xmit_busy", 25, 1,0, "UART transmitter busy"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self):
dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
......@@ -1964,6 +1987,7 @@ class X393ExportC(object):
dw.append(("nbwr", vrlg.SENSI2C_TBL_NBWR, vrlg.SENSI2C_TBL_NBWR_BITS,0, "Number of bytes to write (1..10)"))
dw.append(("dly", vrlg.SENSI2C_TBL_DLY, vrlg.SENSI2C_TBL_DLY_BITS, 0, "Bit delay - number of mclk periods in 1/4 of the SCL period"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2, 2, "Should be 2 to select table data write mode"))
dw.append(("extif_mode", vrlg.SENSI2C_TBL_EXTIF, vrlg.SENSI2C_TBL_EXTIF_BITS,0, "External interface mode: 0 - I2C (old), 1 - UART (Boson)"))
return dw
def _enc_i2c_tbl_rmode(self):
......@@ -2156,6 +2180,29 @@ class X393ExportC(object):
dw.append(("dbg_src_set", vrlg.VOSPI_DBG_SRC+3, 1, 0, "Enable write to dbg_src"))
return dw
def _enc_sensio_ctrl_boson(self):
dw=[]
dw.append(("mrst", vrlg.SENS_CTRL_MRST, 1, 0, "MRST signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("mrst_set", vrlg.SENS_CTRL_MRST + 1, 1, 0, "when set to 1, MRST is set to the 'mrst' field value"))
# dw.append(("arst", vrlg.SENS_CTRL_ARST, 1, 0, "ARST signal to the sensor"))
# dw.append(("arst_set", vrlg.SENS_CTRL_ARST + 1, 1, 0, "ARST set to the 'arst' field"))
# dw.append(("aro", vrlg.SENS_CTRL_ARO, 1, 0, "ARO signal to the sensor"))
# dw.append(("aro_set", vrlg.SENS_CTRL_ARO + 1, 1, 0, "ARO set to the 'aro' field"))
dw.append(("mmcm_rst", vrlg.SENS_CTRL_RST_MMCM, 1, 0, "MMCM (for sensor clock) reset signal"))
dw.append(("mmcm_rst_set", vrlg.SENS_CTRL_RST_MMCM + 1, 1, 0, "MMCM reset set to 'mmcm_rst' field"))
# dw.append(("ign_embed", vrlg.SENS_CTRL_IGNORE_EMBED, 1, 0, "Ignore embedded data (non-image pixel lines"))
# dw.append(("ign_embed_set",vrlg.SENS_CTRL_IGNORE_EMBED + 1,1,0, "Set mode to 'ign_embed' field"))
dw.append(("set_dly", vrlg.SENS_CTRL_LD_DLY, 1, 0, "Set all pre-programmed delays to the sensor port input delays"))
dw.append(("gp0", vrlg.SENS_CTRL_GP0, 2, 0 , "GP0 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp0_set", vrlg.SENS_CTRL_GP0 + 2, 1, 0, "Set GP0 to 'gp0' value"))
dw.append(("gp1", vrlg.SENS_CTRL_GP1, 2, 0 , "GP1 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp1_set", vrlg.SENS_CTRL_GP1 + 2, 1, 0, "Set GP1 to 'gp1' value"))
dw.append(("gp2", vrlg.SENS_CTRL_GP2, 2, 0 , "GP2 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp2_set", vrlg.SENS_CTRL_GP2 + 2, 1, 0, "Set GP2 to 'gp2' value"))
dw.append(("gp3", vrlg.SENS_CTRL_GP3, 2, 0 , "GP3 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp3_set", vrlg.SENS_CTRL_GP3 + 2, 1, 0, "Set GP3 to 'gp3' value"))
return dw
def _enc_sensio_jtag(self):
dw=[]
dw.append(("tdi", vrlg.SENS_JTAG_TDI, 1, 0, "JTAG TDI level"))
......@@ -2266,6 +2313,26 @@ class X393ExportC(object):
dw.append(("phase_h", 0, 8, 0, "MMCM phase"))
return dw
def _enc_sensio_boson_tim0(self):
dw=[]
dw.append(("uart_txd", 0, 8, 0, "UART transmit data byte"))
return dw
def _enc_sensio_boson_tim1(self):
dw=[]
dw.append(("uart_extif_en", vrlg.SENS_UART_EXTIF_EN, 1, 0, "UART: enable sequencer commands"))
dw.append(("uart_extif_en_set", vrlg.SENS_UART_EXTIF_EN+1, 1, 0, "set 'uart_extif_en' field"))
dw.append(("uart_xmit_rst", vrlg.SENS_UART_XMIT_RST, 1, 0, "UART: reset software packet transmission"))
dw.append(("uart_xmit_rst_set", vrlg.SENS_UART_XMIT_RST+1, 1, 0, "set 'uart_xmit_rst' field"))
dw.append(("uart_recv_rst", vrlg.SENS_UART_RECV_RST, 1, 0, "UART: reset software packet receiving"))
dw.append(("uart_recv_rst_set", vrlg.SENS_UART_RECV_RST+1, 1, 0, "set 'uart_recv_rst' field"))
dw.append(("uart_xmit_start", vrlg.SENS_UART_XMIT_START, 1, 0, "UART: start transmiting prepared packet"))
dw.append(("uart_recv_next", vrlg.SENS_UART_RECV_NEXT, 1, 0, "UART: advance receive FIFO to next byte"))
return dw
def _enc_sensio_width(self):
dw=[]
dw.append(("sensor_width", 0, 16, 0, "Sensor frame width (0 - use line sync signals from the sensor)"))
......@@ -2784,4 +2851,4 @@ class X393ExportC(object):
\ No newline at end of file
py393/x393_sens_cmprs.py
View file @ 043d4849
......@@ -131,13 +131,17 @@ FRAME_START_ADDRESS_INC = 0x80000
# for now - single sensor type per interface
SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"},
x393_sensor.SENSOR_INTERFACE_VOSPI: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"}}
x393_sensor.SENSOR_INTERFACE_VOSPI: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
x393_sensor.SENSOR_INTERFACE_BOSON: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}} # see if freq is not needed
# x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":2500, "freq":24.444, "iface":"1V8_LVDS"}}
#slave is 7 bit
#BOSON: add parameters for uart instead of the i2C
#Use 'hardware' dimensions here, simulation ones will be overwritten
SENSOR_DEFAULTS= { x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2},
# x393_sensor.SENSOR_INTERFACE_VOSPI: {"width":160, "height":120, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2}}
x393_sensor.SENSOR_INTERFACE_VOSPI: {"width":160, "height":122, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2}}
x393_sensor.SENSOR_INTERFACE_VOSPI: {"width":160, "height":122, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2},
x393_sensor.SENSOR_INTERFACE_BOSON: {"width":640, "height":513, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2}}
#SENSOR_DEFAULTS_SIMULATION= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
# x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2}}
......@@ -187,8 +191,10 @@ class X393SensCmprs(object):
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_VOSPI]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_VOSPI]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_BOSON]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_BOSON]["height"]= vrlg.WOI_HEIGHT + 0
print ("Using simulation size sensor defaults ",SENSOR_DEFAULTS)
except:
......@@ -792,6 +798,37 @@ class X393SensCmprs(object):
spi_en = 3, #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
out_en = True)
elif sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
self.x393Sensor.set_sensor_io_ctl_boson (
num_sensor = num_sensor,
mrst = True,
mmcm_rst = True, #reset mmcm
set_delays = False)
self.x393Sensor.func_sensor_uart_ctl_boson (
uart_extif_en = False,
uart_xmit_rst = True,
uart_recv_rst = True,
uart_xmit_start = False,
uart_recv_next = False)
self.x393Sensor.set_sensor_io_ctl_boson (
num_sensor = num_sensor,
mrst = False,
mmcm_rst = True, #reset mmcm
set_delays = False)
self.x393Sensor.set_sensor_io_ctl_boson (
num_sensor = num_sensor,
mrst = False,
mmcm_rst = False,
set_delays = False)
self.x393Sensor.func_sensor_uart_ctl_boson (
uart_extif_en = True,
uart_xmit_rst = False,
uart_recv_rst = False,
uart_xmit_start = False,
uart_recv_next = False)
if exit_step == 17: return False
"""
......@@ -1844,7 +1881,8 @@ class X393SensCmprs(object):
num_bytes_rd = 2,
bit_delay = i2c_delay,
verbose = verbose)
elif sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
pass
else:
raise ("Unknown sensor type: %s"%(sensorType))
......
py393/x393_sensor.py
View file @ 043d4849
......@@ -49,6 +49,7 @@ import x393_mcntrl
SENSOR_INTERFACE_PARALLEL = "PAR12"
SENSOR_INTERFACE_HISPI = "HISPI"
SENSOR_INTERFACE_VOSPI = "VOSPI"
SENSOR_INTERFACE_BOSON = "BOSON"
class X393Sensor(object):
DRY_MODE= True # True
......@@ -74,11 +75,21 @@ class X393Sensor(object):
Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi
@return "PAR12" or "HISPI"
"""
if self.DRY_MODE is True:
print ("===== Running in dry mode, using parallel sensor======")
return SENSOR_INTERFACE_PARALLEL
print(self.x393_axi_tasks.read_status(address=0xfe))
sens_type = (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI,SENSOR_INTERFACE_VOSPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
print ("===== Was: Running in dry mode, using parallel sensor======")
# if self.DRY_MODE is True:
# print ("===== Running in dry mode, using parallel sensor======")
# return SENSOR_INTERFACE_PARALLEL
try:
print(self.x393_axi_tasks.read_status(address=0xfe))
except:
print ("===== Failed to read sesnor type, using parallel sensor======")
if self.DRY_MODE is True:
return SENSOR_INTERFACE_PARALLEL
sens_type = (SENSOR_INTERFACE_PARALLEL,
SENSOR_INTERFACE_HISPI,
SENSOR_INTERFACE_VOSPI,
SENSOR_INTERFACE_BOSON
)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
print ("===== Sensor type read from FPGA = >>> %s <<< ======"%(sens_type))
return sens_type
......@@ -186,6 +197,20 @@ class X393Sensor(object):
print (" senspgmin = %d"%((status>>24) & 1))
print (" busy = %d"%((status>>25) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
elif (sensorType == SENSOR_INTERFACE_BOSON):
print (" ps_out = %d"%((status>> 0) & 0xff))
print (" ps_rdy = %d"%((status>> 8) & 1))
print (" perr = %d"%((status>> 9) & 1))
print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1))
print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1))
print (" locked_pxd_mmcm = %d"%((status>>12) & 1))
print (" hact_alive = %d"%((status>>13) & 1))
print (" recv_prgrs = %d"%((status>>14) & 1))
print (" recv_dav = %d"%((status>>15) & 1))
print (" recv_data = %d"%((status>>16) & 0xff))
print (" senspgmin = %d"%((status>>24) & 1))
print (" xmit_busy = %d"%((status>>25) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
else:
#last_in_line_1cyc_mclk, dout_valid_1cyc_mclk
"""
......@@ -376,12 +401,14 @@ class X393Sensor(object):
rah,
num_bytes,
bit_delay,
extif = 0,
verbose = 1):
"""
@param slave_addr - 7-bit i2c slave address
@param rah - register address high byte (bits [15:8]) optionally used for register write commands
@param num_bytes - number of bytes to send (including register address bytes) 1..10
@param bit_delay - number of mclk clock cycle in 1/4 of the SCL period
@param extif - extrenal intgerface instead of i2c. 0 - i2c, 1 - uart,2,3 - reserved
@param verbose - verbose level
@return combined table data word.
"""
......@@ -392,6 +419,7 @@ class X393Sensor(object):
rslt |= (rah & ((1 << vrlg.SENSI2C_TBL_RAH_BITS) - 1)) << vrlg.SENSI2C_TBL_RAH
rslt |= (num_bytes & ((1 << vrlg.SENSI2C_TBL_NBWR_BITS) - 1)) << vrlg.SENSI2C_TBL_NBWR
rslt |= (bit_delay & ((1 << vrlg.SENSI2C_TBL_DLY_BITS) - 1)) << vrlg.SENSI2C_TBL_DLY
rslt |= (extif & ((1 << vrlg.SENSI2C_TBL_EXTIF_BITS) - 1)) << vrlg.SENSI2C_TBL_EXTIF
return rslt
def func_sensor_i2c_table_reg_rd (self,
......@@ -551,7 +579,68 @@ class X393Sensor(object):
return rslt
def func_sensor_io_ctl_boson (self,
mrst = None,
mmcm_rst = None,
set_delays = False,
gpio0 = None,
gpio1 = None,
gpio2 = None,
gpio3 = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
@param mmcm_rst - True - activate MMCM reset, False - deactivate MMCM reset, None - no change (needed after clock change/interruption)
@param set_delays - (self-clearing) load all pre-programmed delays for the sensor pad inputs
@param gpio0 - GPIO[0]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@return sensor i/o control word
"""
rslt = 0
if not mrst is None:
rslt |= (3,2)[mrst] << vrlg.SENS_CTRL_MRST
if not mmcm_rst is None:
rslt |= (2,3)[mmcm_rst] << vrlg.SENS_CTRL_RST_MMCM
rslt |= (0,1)[set_delays] << vrlg.SENS_CTRL_LD_DLY
#GPIO are not yet used in Boson?
if not gpio0 is None:
rslt |= (4 | (gpio0 & 3)) << vrlg.SENS_CTRL_GP0
if not gpio1 is None:
rslt |= (4 | (gpio1 & 3)) << vrlg.SENS_CTRL_GP1
if not gpio2 is None:
rslt |= (4 | (gpio2 & 3)) << vrlg.SENS_CTRL_GP2
if not gpio3 is None:
rslt |= (4 | (gpio3 & 3)) << vrlg.SENS_CTRL_GP3
return rslt
def func_sensor_uart_ctl_boson (self,
uart_extif_en = None,
uart_xmit_rst = None,
uart_recv_rst = None,
uart_xmit_start = False,
uart_recv_next = False):
"""
Combine sensor UART control parameters into a control word
@param uart_extif_en - True - enable sequencer commands, False - disable sequencer commands
@param uart_xmit_rst - True - persistent reset software packet transmission, False - disable reset software packet transmission (normal operation)
@param uart_recv_rst - True - persistent reset packet receive, False - disable reset packet receive (normal operation)
@param uart_xmit_start - start transmiting prepared packet
@param uart_recv_next - advance receive FIFO to next byte
@return uart control word
"""
rslt = 0
if not uart_extif_en is None:
rslt |= (3,2)[uart_extif_en] << vrlg.SENS_UART_EXTIF_EN
if not uart_xmit_rst is None:
rslt |= (3,2)[uart_xmit_rst] << vrlg.SENS_UART_XMIT_RST
if not uart_recv_rst is None:
rslt |= (3,2)[uart_recv_rst] << vrlg.SENS_UART_RECV_RST
rslt |= (0,1)[uart_xmit_start] << vrlg.SENS_UART_XMIT_START
rslt |= (0,1)[uart_recv_next] << vrlg.SENS_UART_RECV_NEXT
return rslt
def func_sensor_jtag_ctl(self,
pgmen = None, # <2: keep PGMEN, 2 - PGMEN low (inactive), 3 - high (active) enable JTAG control
......@@ -733,15 +822,17 @@ class X393Sensor(object):
rah,
num_bytes,
bit_delay,
extif = 0,
verbose = 1):
"""
Set table entry for a single index for register write
@param num_sensor - sensor port number (0..3)
@param page - 1 byte table index (later provided as high byte of the 32-bit command)
@param slave_addr - 7-bit i2c slave address
@param rah - register address high byte (bits [15:8]) optionally used for register write commands
@param num_bytes - number of bytes to send (including register address bytes) 1..10
@param slave_addr - 7-bit i2c slave address (number of payload bytes for UART command (0..4)
@param rah - register address high byte (bits [15:8]) optionally used for register write commands (module # for UART)
@param num_bytes - number of bytes to send (including register address bytes) 1..10 (always 4 for UART)
@param bit_delay - number of mclk clock cycle in 1/4 of the SCL period
@param extif - extrenal intgerface instead of i2c. 0 - i2c, 1 - uart,2,3 - reserved
@param verbose - verbose level
"""
ta = (1 << vrlg.SENSI2C_CMD_TABLE) | (1 << vrlg.SENSI2C_CMD_TAND) | (page & 0xff)
......@@ -750,6 +841,7 @@ class X393Sensor(object):
rah = rah,
num_bytes = num_bytes,
bit_delay = bit_delay,
extif = extif,
verbose = verbose)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, ta)
......@@ -1166,6 +1258,118 @@ class X393Sensor(object):
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data)
def set_sensor_io_ctl_boson (self,
num_sensor,
mrst = None,
mmcm_rst = None,
set_delays = False,
gpio0 = None,
gpio1 = None,
gpio2 = None,
gpio3 = None):
"""
Set sensor I/O controls, including I/O signals
@param num_sensor - sensor port number (0..3)
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
@param mmcm_rst - True - activate MMCM reset, False - deactivate MMCM reset, None - no change (needed after clock change/interruption)
@param set_delays - (self-clearing) load all pre-programmed delays for the sensor pad inputs
@param gpio0 - GPIO[0]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_io_ctl_boson (num_sensor,
mrst = mrst,
mmcm_rst = mmcm_rst,
set_delays = set_delays,
gpio0 = gpio0,
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3)
return
except:
pass
data = self.func_sensor_io_ctl_boson (
mrst = mrst,
mmcm_rst = mmcm_rst,
set_delays = set_delays,
gpio0 = gpio0,
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data)
def set_sensor_uart_ctl_boson (self,
num_sensor,
uart_extif_en = None,
uart_xmit_rst = None,
uart_recv_rst = None,
uart_xmit_start = False,
uart_recv_next = False):
"""
Set sensor UART control signals
@param num_sensor - sensor port number (0..3)
@param uart_extif_en - True - enable sequencer commands, False - disable sequencer commands
@param uart_xmit_rst - True - persistent reset software packet transmission, False - disable reset software packet transmission (normal operation)
@param uart_recv_rst - True - persistent reset packet receive, False - disable reset packet receive (normal operation)
@param uart_xmit_start - start transmiting prepared packet
@param uart_recv_next - advance receive FIFO to next byte
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_uart_ctl_boson (num_sensor,
uart_extif_en = uart_extif_en,
uart_xmit_rst = uart_xmit_rst,
uart_recv_rst = uart_recv_rst,
uart_xmit_start = uart_xmit_start,
uart_recv_next = uart_recv_next)
return
except:
pass
data = self.func_sensor_uart_ctl_boson (
uart_extif_en = uart_extif_en,
uart_xmit_rst = uart_xmit_rst,
uart_recv_rst = uart_recv_rst,
uart_xmit_start = uart_xmit_start,
uart_recv_next = uart_recv_next)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + (vrlg.SENSIO_DELAYS + 1);
self.x393_axi_tasks.write_control_register(reg_addr, data)
def set_sensor_uart_fifo_byte_boson (self,
num_sensor,
uart_tx_byte):
"""
Write byte tio the sensor UART transmit FIFO
@param num_sensor - sensor port number (0..3)
@param uart_tx_byte - Byte to write to FIFO
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_uart_fifo_byte_boson (num_sensor,
uart_tx_byte = uart_tx_byte)
return
except:
pass
data = uart_tx_byte & 0xff;
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + (vrlg.SENSIO_DELAYS + 0);
self.x393_axi_tasks.write_control_register(reg_addr, data)
# TODO: Make one for HiSPi (it is different)
def set_sensor_io_dly_parallel (self,
num_sensor,
mmcm_phase,
......
py393/x393_tiff_verilog.py
View file @ 043d4849
......@@ -50,6 +50,7 @@ try:
outname = sys.argv[3]
except IndexError:
outname = fname.replace(".tiff",".dat")
print("Generating %s frm %s"%(outname, fname))
tif = Image.open(fname)
......@@ -59,6 +60,9 @@ f="%%0%dx"%(digits)
with open(outname,"w") as outfile:
print("//",file=outfile)
print("// autogenerated from %s"%(fname),file=outfile)
print("// GENERATOR = %s"%(sys.argv[0]),file=outfile)
print("// WIDTH = %d"%(image_array.shape[1]),file=outfile)
print("// HEIGHT = %d"%(image_array.shape[0]),file=outfile)
print("//",file=outfile)
for image_line in image_array:
for pixel in image_line:
......
sensor/boson_uart.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> boson_uart
* @file boson_uart.v
* @date 2020-12-12
* @author eyesis
*
* @brief 921.6K8N1 UART to communicate with Boson
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* boson_uart.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* boson_uart.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
`include "system_defines.vh" // just for debugging histograms
module boson_uart #(
// parameter BOSON_BAUD = 921600,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output txd, // serial data out
input rxd, // serial data in
input [7:0] tx_byte, // transmit byte in
input tx_stb, // transmit strobe for byte in
output tx_busy, // transmit in progress
output tx_rdy, // ready to accept tx_stb
output [7:0] rx_byte, // received byte
output rx_stb // received data strobe (valid 1 cycle before and later for 1 bit)
);
localparam CLK_DIV_BITS = clogb2(CLK_DIV); // + 1);
localparam RX_DEBOUNCE_BITS = clogb2(RX_DEBOUNCE + 1);
reg [CLK_DIV_BITS-1:0] clk_div_cntr_rx;
reg [CLK_DIV_BITS-1:0] clk_div_cntr_tx;
reg [RX_DEBOUNCE_BITS-1:0] debounce_cntr;
reg rxd_r;
reg [9:0] rx_sr; // receive channel shift register, including start_stop
reg [9:0] tx_sr; // transmit channel shift register, including start_stop
reg [7:0] tx_r; // transmit channel data input register
reg [3:0] rx_bcntr; // read channel bit counter;
reg [3:0] tx_bcntr; // read channel bit counter;
reg rx_err;
reg rx_bit;
reg [1:0] tx_bit;
reg [1:0] rx_stb_r;
reg tx_busy_r;
reg tx_rq; // request to transmit
reg mrst_d;
reg tx_start;
reg tx_continue;
wire debounced;
wire rx_bitw;
wire tx_bitw;
wire mark;
wire rx_errw;
wire start_bit_rx;
wire stop_bit_rx;
wire stop_bit_tx;
wire tx_startw; // start next 10-bit transmission
wire tx_continuew;
assign debounced = (debounce_cntr == 0);
assign rx_bitw = (clk_div_cntr_rx == 0);
assign tx_bitw = (clk_div_cntr_tx == 0);
assign mark = &rx_sr; // all ones
assign start_bit_rx = (rx_bcntr == 0);
assign stop_bit_rx = (rx_bcntr == 9);
assign stop_bit_tx = (tx_bcntr == 9);
assign rx_errw = rxd_r ? start_bit_rx : stop_bit_rx; // 1 at start, 0 at stop
assign tx_startw = tx_bit[0] && stop_bit_tx && tx_rq;
assign tx_continuew = tx_bit[0] && !stop_bit_tx;
assign rx_byte = rx_sr[8:1];
assign rx_stb = rx_stb_r[1];
assign tx_rdy = tx_rq;
assign tx_busy = tx_busy_r || !tx_rq;
assign txd = tx_sr[0];
always @(posedge mclk) begin
if (mrst) rxd_r <= rxd;
else if (debounced) rxd_r <= rxd;
if (rxd_r == rxd) debounce_cntr <= RX_DEBOUNCE;
else if (!debounced) debounce_cntr <= debounce_cntr - 1;
if (mrst) clk_div_cntr_rx <= CLK_DIV - 2;
else if (rx_bit) clk_div_cntr_rx <= CLK_DIV - 2;
else if (debounced) clk_div_cntr_rx <= (CLK_DIV >> 1); // half interval
else clk_div_cntr_rx <= clk_div_cntr_rx - 1;
rx_bit <= rx_bitw;
if (mrst) rx_sr <= 10'h3ff; // inactive "1"
else if (rx_bit) rx_sr <= {rxd_r,rx_sr[9:1]}; // little endian as RX232
if (mark || rx_err || (rx_bit && stop_bit_rx)) rx_bcntr <= 0;
else if (rx_bit) rx_bcntr <= rx_bcntr + 1;
if (mark) rx_err <= 0;
else if (rx_bit && rx_errw) rx_err <= 1;
rx_stb_r <= {rx_stb_r[0], stop_bit_rx & rx_bit};
end
// Transmit path
always @(posedge mclk) begin
if (tx_stb) tx_r <= tx_byte;
mrst_d <= mrst;
tx_bit <= {tx_bit[0],tx_bitw};
if (mrst) clk_div_cntr_tx <= CLK_DIV - 3;
else if (tx_bit[1]) clk_div_cntr_tx <= CLK_DIV - 3;
else clk_div_cntr_tx <= clk_div_cntr_tx - 1;
if (mrst) tx_sr <= 10'h3ff;
else if (tx_start) tx_sr <= {1'b1, tx_r, 1'b0};
else if (tx_bit[1]) tx_sr <= {1'b1, tx_sr[9:1]};
if (mrst) tx_busy_r <= 0;
else if (tx_start) tx_busy_r <= 1;
else if (tx_bit[1] && stop_bit_tx) tx_busy_r <= 0;
if (mrst) tx_rq <= 0;
else if (mrst_d) tx_rq <= 1; // single-cycle turn-on after mrst
else if (tx_stb) tx_rq <= 0;
else if (tx_start) tx_rq <= 1;
if (mrst) tx_bcntr <= 0;
else if (tx_start) tx_bcntr <= 0;
else if (tx_continue) tx_bcntr <= tx_bcntr + 1;
tx_start <= tx_startw;
tx_continue <= tx_continuew;
end
function integer clogb2;
input [31:0] value;
begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin // SuppressThisWarning VEditor - VDT bug
value = value >> 1;
end
end
endfunction
endmodule
sensor/crc16_xmodem.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> crc16_xmodem
* @file crc16_xmodem.v
* @date 2020-12-13
* @author eyesis
*
* @brief Calculate and insert/verify crc16 (both receive and transmit)
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* crc16_xmodem.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* crc16_xmodem.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module crc16_xmodem#(
parameter INITIAL_CRC16 = 16'h1d0f
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
// Transmit channel
input tx_start, // initialize crc16
input [7:0] txd_in, // transmit payload
input tx_in_stb, // strobe for the txd_in
input tx_over, // payload data ended, should output crc16 (should be after the last tx_in_stb)
input tx_rdy, // stuffer is ready to accept next byte
output tx_in_rdy, // module ready to accept next byte
output [7:0] txd_out, // delayed txt_in, followed by the CRC16
output tx_out_stb, // load txd_out to stuffer
output tx_busy // does not include destuffer and uart
// implementing only transmit CRC16 as response is only needed for non-sequencer operation
/*
// receive channel
,input rx_start,
input [7:0] rxd_in, // byte input from stuffer
input rx_in_stb, // next byte from destuffer in rxd_in
input rx_over, // no more data from destuffer (last 2 bytes were crc16: msb, lsb)
output [7:0] rxd_out, // received chn, payload and crc data
output rx_out_stb, // received data output strobe
output rx_busy, // received channel busy
output rx_crc_good // valid with !rx_busy
*/
);
reg [7:0] txd_in_r;
reg tx_busy_r;
reg tx_stb_crc_m;
reg tx_stb_crc_l;
reg tx_stb_crc_l2; // next cycle after tx_stb_crc_l, same as last tx_out_stb
reg [15:0] tx_crc16_r;
reg [3:0] tx_crc16_s;
reg [7:0] crc16_addr;
reg [7:0] txd_out_r;
reg tx_pre_crc;
reg [1:0] tx_crc_out;
reg [1:0] tx_crc_out_d;
reg tx_in_rdy_r;
reg tx_dav_r;
reg tx_out_stb_r;
reg tx_out_stb_r2;
reg tx_gen_bsy;
wire tx_crc16_next; // calculate next CRC16
wire [15:0] crc16_table; // valid at tx_crc16_s[3]
wire [15:0] tx_crc16_w;
assign tx_crc16_next =tx_crc16_s[3];
assign tx_crc16_w = {tx_crc16_r[7:0] ^ crc16_table[15:8], crc16_table[7:0]};
assign tx_busy = tx_busy_r;
assign txd_out = txd_out_r;
assign tx_in_rdy = tx_in_rdy_r;
assign tx_out_stb = tx_out_stb_r;
always @(posedge mclk) begin
if (mrst) tx_in_rdy_r <= 0;
else if (tx_start || tx_crc16_s[0]) tx_in_rdy_r <= 1; // tx_crc16_next
else if (tx_in_stb || tx_over) tx_in_rdy_r <= 0;
if (mrst) tx_gen_bsy <= 0;
else if (tx_in_stb) tx_gen_bsy <= 1;
else if (tx_out_stb_r) tx_gen_bsy <= 0;
if (mrst) tx_pre_crc <= 0;
else if (tx_start) tx_pre_crc <= 0;
else if (tx_over) tx_pre_crc <= 1;
if (mrst) tx_crc_out[0] <= 0;
else if (tx_start) tx_crc_out[0] <= 0;
else if (tx_pre_crc && !tx_gen_bsy) tx_crc_out[0] <= 1;
if (mrst) tx_crc_out[1] <= 0;
else if (tx_start) tx_crc_out[1] <= 0;
else if (tx_crc_out[0] && tx_out_stb_r) tx_crc_out <= 2'h1;
tx_crc_out_d <= tx_crc_out;
if (mrst) tx_dav_r <= 0;
else if (tx_out_stb_r) tx_dav_r <= 0;
else if (tx_crc16_next || tx_stb_crc_m || tx_stb_crc_l) tx_dav_r <= 1;
tx_out_stb_r <= !tx_out_stb_r && !tx_out_stb_r2 && tx_dav_r && tx_rdy;
tx_out_stb_r2 <= tx_out_stb_r;
tx_stb_crc_m <= tx_crc_out[0] && !tx_crc_out[1] && !tx_crc_out_d[0]; // tx_crc_out[0] just 0->1
tx_stb_crc_l <= tx_crc_out[1] && !tx_crc_out_d[1]; // tx_crc_out[1] just 0->1
if (tx_crc16_next) txd_out_r <= txd_in_r;
else if (tx_stb_crc_m) txd_out_r <= tx_crc16_r[15:8];
else if (tx_stb_crc_l) txd_out_r <= tx_crc16_r[ 7:0];
if (mrst) tx_crc16_s <= 0;
else tx_crc16_s <= {tx_crc16_s[2:0],tx_in_stb};
if (tx_crc16_s[0]) crc16_addr <= tx_crc16_r[15:8] ^ txd_in_r;
if (tx_in_stb) txd_in_r <= txd_in;
tx_stb_crc_l2 <= tx_stb_crc_l;
if (mrst) tx_busy_r <= 0;
else if (tx_start) tx_busy_r <= 1;
else if (tx_stb_crc_l2) tx_busy_r <= 0;
if (tx_start) tx_crc16_r <= INITIAL_CRC16;
else if (tx_crc16_next) tx_crc16_r <= tx_crc16_w;
end
ram18_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (4),
.LOG2WIDTH_RD (4),
.DUMMY (0)
`ifdef PRELOAD_BRAMS
, .INIT_00 (256'hF1EFE1CED1ADC18CB16BA14A9129810870E760C650A540843063204210210000)
, .INIT_01 (256'hE3DEF3FFC39CD3BDA35AB37B8318933962D672F7429452B52252327302101231)
, .INIT_02 (256'hD58DC5ACF5CFE5EE95098528B54BA56A548544A474C764E61401042034432462)
, .INIT_03 (256'hC7BCD79DE7FEF7DF87389719A77AB75B46B4569566F676D70630161126723653)
, .INIT_04 (256'hB92BA90A99698948F9AFE98ED9EDC9CC382328021861084078A7688658E548C4)
, .INIT_05 (256'hAB1ABB3B8B589B79EB9EFBBFCBDCDBFD2A123A330A501A716A967AB74AD45AF5)
, .INIT_06 (256'h9D498D68BD0BAD2ADDCDCDECFD8FEDAE1C410C603C032C225CC54CE47C876CA6)
, .INIT_07 (256'h8F789F59AF3ABF1BCFFCDFDDEFBEFF9F0E701E512E323E134EF45ED56EB67E97)
, .INIT_08 (256'h606770464025500420E330C200A11080E16FF14EC12DD10CA1EBB1CA81A99188)
, .INIT_09 (256'h725662775214423532D222F3129002B1F35EE37FD31CC33DB3DAA3FB939883B9)
, .INIT_0A (256'h4405542464477466048114A024C334E2C50DD52CE54FF56E858995A8A5CBB5EA)
, .INIT_0B (256'h563446157676665716B0069136F226D3D73CC71DF77EE75F97B88799B7FAA7DB)
, .INIT_0C (256'h28A3388208E118C06827780648655844A9ABB98A89E999C8E92FF90EC96DD94C)
, .INIT_0D (256'h3A922AB31AD00AF17A166A375A544A75BB9AABBB9BD88BF9FB1EEB3FDB5CCB7D)
, .INIT_0E (256'h0CC11CE02C833CA24C455C646C077C268DC99DE8AD8BBDAACD4DDD6CED0FFD2E)
, .INIT_0F (256'h1EF00ED13EB22E935E744E557E366E179FF88FD9BFBAAF9BDF7CCF5DFF3EEF1F)
`endif
) i_crc16 (
.rclk (mclk), // input
.raddr ({2'b0, crc16_addr[7:0]}), // input[8:0]
.ren (tx_crc16_s[1]), // input
.regen (tx_crc16_s[2]), // input
.data_out (crc16_table[15:0]), // output[15:0]
.wclk (1'b0), // input
.waddr (10'b0), // input[8:0]
.we (1'b0), // input
.web (4'b0), // input[3:0]
.data_in (16'b0) // input[15:0]
);
endmodule
sensor/sens_103993.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b>sens_103993
* @file sens_103993.v
* @date 2015-10-15
* @author Andrey Filippov
*
* @brief Top level module for the 10398 SFE (with MT9F002 sensor)
*
* @copyright Copyright (c) 2020 Elphel, Inc .
*
* <b>License:</b>
*
* sens_103993.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993 #(
parameter SENSIO_ADDR = 'h330,
parameter SENSIO_ADDR_MASK = 'h7f8,
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
/// parameter SENSIO_JTAG = 'h2,
/// parameter SENSIO_WIDTH = 'h3, // HERE - number of lines to skip
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7 - each address sets 4 delays through 4 bytes of 32-bit data
// 5, swap lanes 6 - delays, 7 - phase
parameter SENSIO_STATUS_REG = 'h21,
/// parameter SENS_JTAG_PGMEN = 8,
/// parameter SENS_JTAG_PROG = 6,
/// parameter SENS_JTAG_TCK = 4,
/// parameter SENS_JTAG_TMS = 2,
/// parameter SENS_JTAG_TDI = 0,
parameter SENS_CTRL_MRST= 0, // 1: 0
/// parameter SENS_CTRL_ARST= 2, // 3: 2
/// parameter SENS_CTRL_ARO= 4, // 5: 4
parameter SENS_CTRL_RST_MMCM= 6, // 7: 6
// parameter SENS_CTRL_EXT_CLK= 8, // 9: 8
/// parameter SENS_CTRL_IGNORE_EMBED = 8, // 9: 8
parameter SENS_CTRL_LD_DLY= 10, // 10
// parameter SENS_CTRL_GP0= 12, // 13:12
// parameter SENS_CTRL_GP1= 14, // 15:14
parameter SENS_CTRL_GP0= 12, // 14:12 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP1= 15, // 17:15 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7
// parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
// parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
// parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
parameter IODELAY_GRP = "IODELAY_SENSOR",
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
// parameter LVDS_MSB_FIRST = 0,
parameter NUMLANES = 3,
parameter LVDS_DELAY_CLK = "FALSE",
parameter LVDS_MMCM = "TRUE",
// parameter LVDS_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
// parameter LVDS_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
// parameter LVDS_FIFO_DEPTH = 4,
// parameter LVDS_FIFO_START = 7,
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// Other (non-HiSPi) sensor I/Os
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "LVCMOS18", // 1.8V single-ended
parameter PXD_SLEW = "SLOW",
parameter PXD_CAPACITANCE = "DONT_CARE",
// parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
// parameter PXD_CLK_DIV_BITS = 4,
// ,parameter STATUS_ALIVE_WIDTH = 4
// parameter SENSIO_SKIP_BITS = 8, // number of bits in line skip counter
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
parameter REPLACED_START_FRAME_BYTE = 'h81,
parameter REPLACED_END_FRAME_BYTE = 'hA1,
parameter REPLACED_ESCAPE_BYTE = 'h91,
parameter INITIAL_CRC16 = 16'h1d0f,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60,
parameter EXTIF_MODE = 1 // 1,2 or 3 if there are several different extif
)(
output pclk, // global clock input, pixel rate (220MHz for MT9F002)
output locked_pclk,
input prst,
output prsts, // @pclk - includes sensor reset and sensor PLL reset
// delay control inputs
input mclk,
input mrst,
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
// input trigger_mode, // running in triggered mode (0 - free running mode)
input ext_sync, // trig, // per-sensor trigger input
// I/O pads
input [NUMLANES-1:0] sns_dp,
input [NUMLANES-1:0] sns_dn,
input sns_clkp,
input sns_clkn,
inout sns_gp2, // sns1_dn[6] just to reduce EMI from the clock == gp[2]
inout sns_pgm, // (pullup) SENSPGM
output sns_ext_sync, // (TCK)
output sns_mrst, // sns_dp[7]
inout sns_gp3, // sns_dn[7] == gp[3] TMS
inout sns_gp0, // sns_dp[5] == gp[0] TDI (differs from 10353)
inout sns_gp1, // sns_dn[5] == gp[1]
output sns_txd, // flash_tdo, // sns_dp[4] TDO (differs from 10353)
input sns_rxd, // shutter_done,// sns_dn[4] DONE (differs from 10353)
output [15:0] pxd,
output vsync,
output hsync, // @pclk
output dvalid, // @pclk
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
// interface for uart in write-only mode for short commands
// 1-st byte - SA (use 2 LSB to select 0,1,2 data bytes
// 2-nd byte module
// 3-rd byte function
// 4 (optional) data[15:8] or data[7:0] if last
// 5 (optional) data[7:0]
input extif_dav, // data byte available for external interface
// input extif_last, // last byte for external interface (with extif_dav)
input [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
input [7:0] extif_byte, // data to external interface (first - extif_sa)
output extif_ready, // acknowledges extif_dav
input extif_rst
);
wire dvalid_w;
reg dvalid_r;
// wire vact_w;
// wire dvalid_w;
reg [31:0] data_r;
// reg [3:0] set_idelay;
// reg set_lanes_map; // set sequence of lanes im the composite pixel line
// reg set_fifo_dly; // set how long to wait after strating to fill FIFOs (in items) ~= 1/2 2^FIFO_DEPTH
reg set_uart_ctrl; // set UART control bits (both TX and receive)
reg set_uart_tx; // set UART tx data (full, starting witgh channel number = 0)
reg set_idelays;
reg set_iclk_phase;
reg set_ctrl_r;
reg set_status_r;
// reg set_jtag_r;
wire perr; // parity error from deserializer
wire ps_rdy;
wire [7:0] ps_out;
// wire locked_pxd_mmcm;
wire clkin_pxd_stopped_mmcm;
wire clkfb_pxd_stopped_mmcm;
// programmed resets to the sensor
reg imrst = 0; // active low
reg rst_mmcm=1; // rst and command - en/dis
reg ld_idelay=0;
wire [25:0] status;
wire cmd_we;
wire [2:0] cmd_a;
wire [31:0] cmd_data;
reg [7:0] gp_r; // sensor GP0, GP1. 2 bits per port : 00 - float, 01 - low, 10 - high , 11 - trigger
reg [1:0] prst_with_sens_mrst = 2'h3; // prst extended to include sensor reset and rst_mmcm
wire async_prst_with_sens_mrst = ~imrst | rst_mmcm; // mclk domain
wire hact_mclk;
wire perr_mclk;
reg hact_alive;
reg perr_persistent;
// new for Boson
wire txd;
wire rxd;
reg extif_en; // enable sequencer commands (disable during software ones if needed)
reg xmit_rst; // input
reg recv_rst; // input
reg xmit_start; // input
reg recv_next; // input
wire xmit_busy; // output
wire recv_prgrs; // output
wire recv_dav; // output fifo not empty
wire [7:0] recv_data; // output[7:0]
wire senspgmin; // detect sensorboard
// GP0..GP3 are not yet used, fake-use gp_comb to keep
wire [3:0] gp;
wire gp_comb = &gp[3:0];
assign status = {recv_data[7:0], // [23:16]
recv_dav, // 15
recv_prgrs, // 14
mrst ? gp_comb : hact_alive, // 13 using gp_comb to keep
locked_pclk, // 12
clkin_pxd_stopped_mmcm, // 11
clkfb_pxd_stopped_mmcm, // 10
perr_persistent, // 9 deserializer parity error
ps_rdy, // 8
ps_out[7:0], // [7:0]
xmit_busy, // 25
senspgmin}; // 24
assign prsts = prst_with_sens_mrst[0]; // @pclk - includes sensor reset and sensor PLL reset
assign dvalid = dvalid_w;
always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
else if (prst) prst_with_sens_mrst <= 2'h3;
else prst_with_sens_mrst <= prst_with_sens_mrst >> 1;
end
always @(posedge pclk) begin
dvalid_r <= dvalid_w;
end
//dvalid_r
always @(posedge mclk) begin
if (mrst) data_r <= 0;
else if (cmd_we) data_r <= cmd_data;
if (mrst) set_uart_tx <= 0;
else set_uart_tx <= cmd_we & (cmd_a==(SENSIO_DELAYS+0)); // TODO - add Symbolic names
if (mrst) set_uart_ctrl <= 0;
else set_uart_ctrl <= cmd_we & (cmd_a==(SENSIO_DELAYS+1));
if (mrst) set_idelays <= 0;
else set_idelays <= cmd_we & (cmd_a==(SENSIO_DELAYS+2));
if (mrst) set_iclk_phase <= 0;
else set_iclk_phase <= cmd_we & (cmd_a==(SENSIO_DELAYS+3));
if (mrst) set_status_r <=0;
else set_status_r <= cmd_we && (cmd_a== SENSIO_STATUS);
if (mrst) set_ctrl_r <=0;
else set_ctrl_r <= cmd_we && (cmd_a== SENSIO_CTRL);
if (mrst) imrst <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_MRST + 1]) imrst <= data_r[SENS_CTRL_MRST];
if (mrst) rst_mmcm <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_RST_MMCM + 1]) rst_mmcm <= data_r[SENS_CTRL_RST_MMCM];
if (mrst) ld_idelay <= 0;
else ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY];
if (mrst) gp_r[1:0] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP0 + 2]) gp_r[1:0] <= data_r[SENS_CTRL_GP0+:2];
if (mrst) gp_r[3:2] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP1 + 2]) gp_r[3:2] <= data_r[SENS_CTRL_GP1+:2];
if (mrst) gp_r[5:4] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP2 + 2]) gp_r[5:4] <= data_r[SENS_CTRL_GP2+:2];
if (mrst) gp_r[7:6] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP3 + 2]) gp_r[7:6] <= data_r[SENS_CTRL_GP3+:2];
if (mrst) extif_en <= 0;
else if (set_uart_ctrl && data_r[SENS_UART_EXTIF_EN + 1]) extif_en <= data_r[SENS_UART_EXTIF_EN];
if (mrst) xmit_rst <= 0;
else if (set_uart_ctrl && data_r[SENS_UART_XMIT_RST + 1]) xmit_rst <= data_r[SENS_UART_XMIT_RST];
if (mrst) recv_rst <= 0;
else if (set_uart_ctrl && data_r[SENS_UART_RECV_RST + 1]) recv_rst <= data_r[SENS_UART_RECV_RST];
xmit_start <= !mrst && set_uart_ctrl && data_r[SENS_UART_XMIT_START];
recv_next <= !mrst && set_uart_ctrl && data_r[SENS_UART_RECV_NEXT];
if (mrst || set_iclk_phase || set_idelays) hact_alive <= 0;
else if (hact_mclk) hact_alive <= 1;
if (mrst || set_ctrl_r) perr_persistent <= 0;
else if (perr_mclk) perr_persistent <= 1;
end
cmd_deser #(
.ADDR (SENSIO_ADDR),
.ADDR_MASK (SENSIO_ADDR_MASK),
.NUM_CYCLES (6),
.ADDR_WIDTH (3),
.DATA_WIDTH (32)
) cmd_deser_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(26) // +3) // +STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_r), // input
.wd (data_r[7:0]), // input[7:0]
.status (status), // input[22:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
serial_103993 #(
.START_FRAME_BYTE (START_FRAME_BYTE), // 'h8E),
.END_FRAME_BYTE (END_FRAME_BYTE), // 'hAE),
.ESCAPE_BYTE (ESCAPE_BYTE), // 'h9E),
.REPLACED_START_FRAME_BYTE (REPLACED_START_FRAME_BYTE), // 'h81),
.REPLACED_END_FRAME_BYTE (REPLACED_END_FRAME_BYTE), // 'hA1),
.REPLACED_ESCAPE_BYTE (REPLACED_ESCAPE_BYTE), // 'h91),
.INITIAL_CRC16 (INITIAL_CRC16), // 16'h1d0f),
.CLK_DIV (CLK_DIV), // 217),
.RX_DEBOUNCE (RX_DEBOUNCE), // 60),
.EXTIF_MODE (EXTIF_MODE) // 1)
) serial_103993_i (
.mrst (mrst), // input
.mclk (mclk), // input
.txd (txd), // output
.rxd (rxd), // input
.extif_dav (extif_dav), // input
.extif_sel (extif_sel), // input[1:0]
.extif_byte (extif_byte), // input[7:0]
.extif_ready (extif_ready), // output
.extif_rst (extif_rst), // input
.extif_en (extif_en), // input
.xmit_rst (xmit_rst), // input
.xmit_start (xmit_start), // input
.xmit_data (data_r[7:0]), // input[7:0]
.xmit_stb (set_uart_tx), // input
.xmit_busy (xmit_busy), // output
.recv_rst (recv_rst), // input
.recv_next (recv_next), // input
.recv_prgrs (recv_prgrs), // output
.recv_dav (recv_dav), // output fifo not empty
.recv_data (recv_data) // output[7:0]
);
sens_103993_l3 #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR), // 37.037),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), // (30),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), // (0.000),
.PCLK_PHASE (PCLK_PHASE), // (0.000),
.IPCLK2X_PHASE (IPCLK2X_PHASE), //(0.000),
.BUF_PCLK (BUF_PCLK), // "BUFR"),
.BUF_IPCLK2X (BUF_IPCLK2X), // "BUFR"),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), // 1),
.SENS_REF_JITTER1 (SENS_REF_JITTER1), // 0.010),
.SENS_REF_JITTER2 (SENS_REF_JITTER2), // 0.010),
.SENS_SS_EN (SENS_SS_EN), // "FALSE"),
.SENS_SS_MODE (SENS_SS_MODE), // "CENTER_HIGH"),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), // 10000),
.NUMLANES (NUMLANES), // 3),
.LVDS_DELAY_CLK (LVDS_DELAY_CLK), // "FALSE"),
.LVDS_MMCM (LVDS_MMCM), // "TRUE"),
.LVDS_CAPACITANCE (LVDS_CAPACITANCE), // "DONT_CARE"),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM), // "TRUE"),
.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT), // "FALSE"),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS), // "TRUE"),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE), // "0"),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR), // "TRUE"),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE), // "AUTO"),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD) // "DIFF_SSTL18_I")
) sens_103993_l3_i (
.pclk (pclk), // output
.sns_dp (sns_dp), // input[2:0]
.sns_dn (sns_dn), // input[2:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.pxd_out (pxd), // output[15:0]
.vsync (vsync), // output
.hsync (hsync), // output
.dvalid (dvalid_w), // output
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (data_r[23:0]), // input[23:0]
.set_idelay ({NUMLANES{set_idelays}}),// input[2:0]
.ld_idelay (ld_idelay), // input
.set_clk_phase (set_iclk_phase), // input
.rst_mmcm (rst_mmcm), // input
.perr (perr), // output
.ps_rdy (ps_rdy), // output
.ps_out (ps_out), // output[7:0]
.locked_pxd_mmcm (locked_pclk), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
);
mpullup i_senspgm_pullup (sns_pgm);
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_pgm_i (
.O (senspgmin), // output
.IO (sns_pgm), // inout
.I (1'b0), // input
.T (1'b1) // input
);
// generate ext_sync
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) ext_sync_i (
.O (sns_ext_sync), // output
.I (ext_sync) // input
);
// generate MRST
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_mrst_i (
.O (sns_mrst), // output
.I (imrst) // input
);
// General purpose I/O - reserved for future use
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) gp0_i (
.O (gp[0]), // output
.IO (sns_gp0), // inout
.I (gp_r[1]), // input
.T (~|gp_r[1:0]) // input
);
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) gp1_i (
.O (gp[1]), // output
.IO (sns_gp1), // inout
.I (gp_r[3]), // input
.T (~|gp_r[3:2]) // input
);
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) gp2_i (
.O (gp[2]), // output
.IO (sns_gp2), // inout
.I (gp_r[5]), // input
.T (~|gp_r[5:4]) // input
);
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) gp3_i (
.O (gp[3]), // output
.IO (sns_gp3), // inout
.I (gp_r[7]), // input
.T (~|gp_r[7:6]) // input
);
// READ RXD
ibuf_ibufg #(
.CAPACITANCE (PXD_CAPACITANCE),
.IBUF_DELAY_VALUE ("0"),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IFD_DELAY_VALUE ("AUTO"),
.IOSTANDARD (PXD_IOSTANDARD)
) rxd_i (
.O(rxd), // output
.I(sns_rxd) // input
);
// generate TXD
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) txd_i (
.O (sns_txd), // output
.I (txd) // input
);
// perr - cross clocks
pulse_cross_clock perr_mclk_i (
.rst (1'b0), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (perr), // input
.out_pulse (perr_mclk), // output
.busy () // output
);
// just to verify hact is active
pulse_cross_clock hact_mclk_i (
.rst (1'b0), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (dvalid_w && !dvalid_r), // input
.out_pulse (hact_mclk), // output
.busy () // output
);
endmodule
sensor/sens_103993_clock.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b>sens_hispi_clock
* @file sens_103993_clock.v
* @date 2020-12-16
* @author Andrey Filippov
*
* @brief Recover iclk/iclk2x from the 103993 differntial clock
*
* @copyright Copyright (c) 2020 Elphel, Inc .
*
* <b>License:</b>
*
* sens_103993.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_clock#(
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
// Used with delay
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter LVDS_DELAY_CLK = "FALSE",
parameter LVDS_MMCM = "TRUE",
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)(
input mclk,
input mrst,
input [7:0] phase,
input set_phase,
input load, // only used when delay, not phase
input rst_mmcm,
input clp_p,
input clk_n,
// output ipclk, // 165 MHz
output ipclk2x, // 330 MHz
output pclk, // 27 MHz
output ps_rdy, // output
output [7:0] ps_out, // output[7:0] reg
output locked_pxd_mmcm,
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
);
wire pclk_pre;
wire ipclk2x_pre; // output
wire clk_fb;
wire prst = mrst;
wire clk_in;
wire clk_int;
wire set_phase_w = (LVDS_DELAY_CLK == "TRUE") ? 1'b0: set_phase;
wire [7:0] phase_w = (LVDS_DELAY_CLK == "TRUE") ? 8'b0: phase;
wire ps_rdy_w;
wire [7:0] ps_out_w;
assign ps_rdy = (LVDS_DELAY_CLK == "TRUE") ? 1'b1 : ps_rdy_w;
assign ps_out = (LVDS_DELAY_CLK == "TRUE") ? 8'b0 : ps_out_w;
generate
if (LVDS_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end
endgenerate
generate
if (LVDS_DELAY_CLK == "TRUE") begin
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) clk_dly_i(
.clk (mclk),
.rst (mrst),
.set (set_phase),
.ld (load),
.delay (phase[4:0]),
.data_in (clk_int),
.data_out (clk_in)
);
end else begin
assign clk_in = clk_int;
end
endgenerate
// generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock
// received from the sensor (may need to reset MMCM after resetting sensor)
generate
if (LVDS_MMCM == "TRUE") begin
mmcm_phase_cntr #(
.PHASE_WIDTH (SENS_PHASE_WIDTH),
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), // 4
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_USE_FINE_PS ("TRUE"),
.CLKOUT1_USE_FINE_PS ("TRUE"),
.CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR), // /30, -> 27MHz
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 10), // /3, -> 270MHz
.COMPENSATION ("ZHOLD"),
.REF_JITTER1 (SENS_REF_JITTER1),
.REF_JITTER2 (SENS_REF_JITTER2),
.SS_EN (SENS_SS_EN),
.SS_MODE (SENS_SS_MODE),
.SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STARTUP_WAIT ("FALSE")
) mmcm_or_pll_i (
.clkin1 (clk_in), // input 27MHz
.clkin2 (1'b0), // input
.sel_clk2 (1'b0), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
.psclk (mclk), // input
.ps_we (set_phase_w), // input
.ps_din (phase_w), // input[7:0]
.ps_ready (ps_rdy_w), // output
.ps_dout (ps_out_w), // output[7:0] reg
.clkout0 (pclk_pre), // output -> 27MHz
.clkout1 (ipclk2x_pre), // output 270Mhz
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkout6(), // output
.clkout0b(), // output
.clkout1b(), // output
.clkout2b(), // output
.clkout3b(), // output
.clkfbout (clk_fb), // output
.clkfboutb(), // output
.locked (locked_pxd_mmcm),
.clkin_stopped (clkin_pxd_stopped_mmcm), // output
.clkfb_stopped (clkfb_pxd_stopped_mmcm) // output
// output
);
end else begin
pll_base #(
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT_SENSOR), // 30
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT0_DIVIDE (CLKFBOUT_MULT_SENSOR), // /30, -> 27MHz
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 10), // /3, -> 270MHz
.REF_JITTER1 (SENS_REF_JITTER1),
.STARTUP_WAIT ("FALSE")
) mmcm_or_pll_i (
.clkin (clk_in), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
.clkout0 (pclk_pre), // output -> 27MHz
.clkout1 (ipclk2x_pre), // output 270Mhz
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout (clk_fb), // output
.locked (locked_pxd_mmcm)
// output
);
assign clkin_pxd_stopped_mmcm = 0;
assign clkfb_pxd_stopped_mmcm = 0;
assign ps_rdy_w = 1;
assign ps_out_w = 0; // alternatively - register delay written
end
endgenerate
generate
if (BUF_IPCLK2X == "BUFG") BUFG clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFH") BUFH clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFR") BUFR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre), .CE(1'b1), .CLR(prst));
else if (BUF_IPCLK2X == "BUFMR") BUFMR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFIO") BUFIO clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else assign ipclk2x = ipclk2x_pre;
endgenerate
generate
if (BUF_PCLK == "BUFG") BUFG clk2x_i (.O(pclk), .I(pclk_pre));
else if (BUF_PCLK == "BUFH") BUFH clk2x_i (.O(pclk), .I(pclk_pre));
else if (BUF_PCLK == "BUFR") BUFR clk2x_i (.O(pclk), .I(pclk_pre), .CE(1'b1), .CLR(prst));
else if (BUF_PCLK == "BUFMR") BUFMR clk2x_i (.O(pclk), .I(pclk_pre));
else if (BUF_PCLK == "BUFIO") BUFIO clk2x_i (.O(pclk), .I(pclk_pre));
else assign pclk = pclk_pre;
endgenerate
endmodule
sensor/sens_103993_deser10.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> sens_103993_deser10
* @file sens_103993_deser10.v
* @date 2020-12-16
* @author eyesis
*
* @brief 10:1 deserializer for 103993 (270MHz->27MHz)
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* sens_103993_deser10.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_deser10.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_deser10(
input pclk10,
input pclk,
input din,
output [9:0] dout
);
reg [9:0] sr;
reg [9:0] dout_r;
assign dout = dout_r;
always @(posedge pclk10) begin
sr <= {sr[8:0], din};
end
always @(posedge pclk) begin
dout_r <= sr;
end
endmodule
sensor/sens_103993_din.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b>sens_103993_din
* @file sens_hispi_din.v
* @date 2020-12-16
* @author Andrey Filippov
*
* @brief Input differential receivers for HiSPi lanes
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* sens_103993_din.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_din.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_din #(
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter NUMLANES = 3,
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)(
input mclk,
input mrst,
input [NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input [NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input ld_idelay, // mclk synchronous set idealy value
input pclk, // 27 MHz
// input ipclk, // 165 MHz
input ipclk2x, // 330 MHz
// input irst, // reset @posedge iclk
input [NUMLANES-1:0] din_p,
input [NUMLANES-1:0] din_n,
output [NUMLANES * 10-1:0] dout
);
wire [NUMLANES-1:0] din;
wire [NUMLANES-1:0] din_dly;
generate
genvar i;
for (i=0; i < NUMLANES; i=i+1) begin: din_block
if (LVDS_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) pxd_dly_i(
.clk (mclk),
.rst (mrst),
.set (set_idelay[i]),
.ld (ld_idelay),
.delay (dly_data[3 + 8*i +: 5]),
.data_in (din[i]),
.data_out (din_dly[i])
);
sens_103993_deser10 sens_103993_deser10_i (
.pclk10 (ipclk2x), // input
.pclk (pclk), // input
.din (din_dly[i]), // input
.dout (dout[10*i +: 10]) // output[9:0]
);
end
endgenerate
endmodule
sensor/sens_103993_l3.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b>sens_103993_l3
* @file sens_hispi12l4.v
* @date 2015-10-13
* @author Andrey Filippov
*
* @brief data from 103993 over 3 lanes
*
* @copyright Copyright (c) 2020 Elphel, Inc .
*
* <b>License:</b>
*
* sens_103993_l3.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_l3.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
//`define MON_HISPI // moved to system_defines
module sens_103993_l3#(
parameter IODELAY_GRP = "IODELAY_SENSOR",
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter NUMLANES = 3,
parameter LVDS_DELAY_CLK = "FALSE",
parameter LVDS_MMCM = "TRUE",
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
)(
output pclk, // global clock input, pixel rate (27MHz for 103993) (220MHz for MT9F002)
// I/O pads
input [NUMLANES-1:0] sns_dp,
input [NUMLANES-1:0] sns_dn,
input sns_clkp,
input sns_clkn,
// output
output [15:0] pxd_out,
output vsync,
output hsync,
output dvalid,
// delay control inputs
input mclk,
input mrst,
input [NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input [NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input ld_idelay, // mclk synchronous set idelay value
input set_clk_phase, // mclk synchronous set idelay value
input rst_mmcm,
// MMCP output status
output perr, // parity error
output ps_rdy, // output
output [7:0] ps_out, // output[7:0] reg
output locked_pxd_mmcm,
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
);
wire ipclk2x;// re-generated HiSPi clock (270 MHa) 330 MHz)
wire [NUMLANES * 10-1:0] sns_d;
reg [15:0] pxd_out_r;
reg vsync_r;
reg hsync_r;
reg dvalid_r;
reg perr_r;
reg cp_r;
assign pxd_out = pxd_out_r;
assign vsync = vsync_r;
assign hsync = hsync_r;
assign dvalid = dvalid_r;
assign perr = perr_r;
sens_103993_clock #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.PCLK_PHASE (PCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_PCLK (BUF_PCLK),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.LVDS_DELAY_CLK (LVDS_DELAY_CLK),
.LVDS_MMCM (LVDS_MMCM),
.LVDS_CAPACITANCE (LVDS_CAPACITANCE),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD)
) sens_103993_clock_i (
.mclk (mclk), // input
.mrst (mrst), // input
.phase (dly_data[7:0]), // input[7:0]
.set_phase (set_clk_phase), // input
.load (ld_idelay), // input
.rst_mmcm (rst_mmcm), // input
.clp_p (sns_clkp), // input
.clk_n (sns_clkn), // input
.pclk (pclk), // output 27MHz
.ipclk2x (ipclk2x), // output
.ps_rdy (ps_rdy), // output
.ps_out (ps_out), // output[7:0]
.locked_pxd_mmcm (locked_pxd_mmcm), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
);
sens_103993_din #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.NUMLANES (NUMLANES),
.LVDS_CAPACITANCE (LVDS_CAPACITANCE),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM),
.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD)
) sens_103993_din_i (
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (dly_data), // input[31:0]
.set_idelay (set_idelay), // input[3:0]
.ld_idelay (ld_idelay), // input
.pclk (pclk), // input
.ipclk2x (ipclk2x), // input
.din_p (sns_dp), // input[2:0]
.din_n (sns_dn), // input[2:0]
.dout (sns_d) // output[29:0]
);
always @(posedge pclk) begin
pxd_out_r <= {sns_d[19:12],sns_d[9:2]};
vsync_r <= sns_d[1]; // input - active high
hsync_r <= sns_d[11]; // input - active high
dvalid_r <= sns_d[21]; // input - active hight
cp_r <= sns_d [0];
perr_r <= ~ cp_r ^ (^pxd_out_r) ^ vsync_r ^ hsync_r ^ dvalid_r;
end
endmodule
sensor/sens_boson.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> sens_boson
* @file sens_boson.v
* @date 2020-12-14
* @author eyesis
*
* @brief senosr port for Boson LWIR sensor
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* sens_boson.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_boson.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
`include "system_defines.vh" // just for debugging histograms
module sens_boson#(
parameter SENSIO_ADDR = 'h330,
parameter SENSIO_ADDR_MASK = 'h7f8,
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_STATUS_REG = 'h21
)(
);
endmodule
sensor/sens_parallel12.v
View file @ 043d4849
......@@ -68,12 +68,12 @@ module sens_parallel12 #(
parameter LINE_WIDTH_BITS = 16,
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW",
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
......
sensor/sensor_channel.v
View file @ 043d4849
......@@ -6,7 +6,7 @@
*
* @brief Top module for a sensor channel
*
* @copyright Copyright (c) 2015 Elphel, Inc.
* @copyright Copyright (c) 2015-2020 Elphel, Inc.
*
* <b>License:</b>
*
......@@ -41,7 +41,8 @@
module sensor_channel#(
// parameters, individual to sensor channels and those likely to be modified
parameter SENSOR_NUMBER = 0, // sensor number (0..3)
// Moving to the end to be always present
// parameter SENSOR_NUMBER = 0, // sensor number (0..3)
parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x30, x32, x34, x36
......@@ -111,7 +112,9 @@ module sensor_channel#(
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2,
parameter SENSI2C_STATUS = 'h1,
parameter SENS_GAMMA_RADDR = 'h38, //4, 'h38..'h3b
......@@ -157,45 +160,78 @@ module sensor_channel#(
parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
parameter SENSIO_ADDR_MASK = 'h7f8,
`ifdef LWIR
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
`else
parameter SENSIO_CTRL = 'h0,
`ifdef LWIR
// parameter SENSIO_CTRL = 'h0,
// parameter SENSIO_STATUS = 'h1,
`else // all not LWIR
// sens_parallel12 registers
parameter SENSIO_CTRL = 'h0,
// parameter SENSIO_CTRL = 'h0,
// SENSIO_CTRL register bits
parameter SENS_CTRL_MRST = 0, // 1: 0
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
parameter SENS_CTRL_MRST = 0, // 1: 0
`ifndef BOSON
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
parameter SENSIO_JTAG = 'h2, // not used for BOSON:
// SENSIO_JTAG register bits
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
`endif
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
parameter SENS_CTRL_LD_DLY = 10, // 10
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
`endif // `ifdef LWIR / else
`ifdef HISPI
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
`else
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
`elsif PAR12
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
`endif
`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
parameter SENS_CTRL_ODD = 6, //
parameter SENS_CTRL_QUADRANTS_EN = 20, // 18:12, enable - 20 (1 bits reserved)
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
`elsif BOSON
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7
`elsif PAR12
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
parameter SENS_CTRL_ODD = 6, //
parameter SENS_CTRL_QUADRANTS_EN = 20, // 18:12, enable - 20 (1 bits reserved)
`endif
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// SENSIO_JTAG register bits
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
`ifndef HISPI
`ifdef PAR12
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
`endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
`ifdef HISPI
`ifdef MON_HISPI
parameter SENSOR_TIMING_STATUS_REG_BASE = 'h40, // 4 locations" x40, x41, x42, x43
parameter SENSOR_TIMING_STATUS_REG_INC = 1, // increment to the next sensor
parameter SENSOR_TIMING_BITS = 24, // increment to the next sensor
parameter SENSOR_TIMING_START = 16, // bit # in JTAB control word to start timing measurement (now f = 660/4 = 165)
parameter SENSOR_TIMING_LANE = 14, // 15:14 - select lane
parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif
/*
`elsif BOSON
`ifdef MON_HISPI
parameter SENSOR_TIMING_STATUS_REG_BASE = 'h40, // 4 locations" x40, x41, x42, x43
parameter SENSOR_TIMING_STATUS_REG_INC = 1, // increment to the next sensor
......@@ -205,8 +241,10 @@ module sensor_channel#(
parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif
`endif
`endif
*/
`endif //`ifdef HISPI
//// `endif // seems to be extra?
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_BASE_ADDR)
parameter SENSI2C_ABS_RADDR = 'h10, // 'h410..'h41f
......@@ -231,8 +269,7 @@ module sensor_channel#(
parameter NUM_FRAME_BITS = 4,
`ifdef HISPI
`elsif LWIR
`ifdef LWIR
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
......@@ -278,38 +315,50 @@ module sensor_channel#(
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185 // Wait to tymeout SPI when needed to re-sync
`else
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`elsif PAR12
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5 // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif
// start with comma!
`ifdef LWIR
,parameter SENSI2C_IOSTANDARD = "LVCMOS25"
`else
// sens_parallel12 other parameters
,parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
`ifdef HISPI
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`elsif HISPI
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4,
//`else
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
`elsif BOSON
parameter PXD_CAPACITANCE = "DONT_CARE",
// parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
// parameter PXD_CLK_DIV_BITS = 4,
`elsif PAR12
// sens_parallel12 other parameters
// parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
// parameter integer IDELAY_VALUE = 0,
/// parameter integer PXD_DRIVE = 12,
/// parameter PXD_IBUF_LOW_PWR = "TRUE",
/// parameter PXD_SLEW = "SLOW",
// parameter real SENS_REFCLK_FREQUENCY = 300.0,
// parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
`ifdef LWIR
`else
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real SENS_REFCLK_FREQUENCY = 200, // was300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for the phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
`endif
// parameters for the sensor-synchronous clock PLL
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
......@@ -319,7 +368,16 @@ module sensor_channel#(
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else
`elsif BOSON
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
//IPCLK* will be used as PCLK*
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`elsif PAR12 // no LWIR
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
......@@ -329,21 +387,22 @@ module sensor_channel#(
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif
`ifdef LWIR
`else // all but LWIR
parameter BUF_IPCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
`endif
`ifdef HISPI
,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
......@@ -358,16 +417,39 @@ module sensor_channel#(
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`elsif BOSON
// ,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 3,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
// parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
// parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
// parameter HISPI_FIFO_DEPTH = 4,
// parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2
parameter DEBUG_CMD_LATENCY = 2,
`endif
// parameter real REFCLK_FREQUENCY = 200.0,
// parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENSOR_NUMBER = 0 // sensor number (0..3)
) (
`ifdef PCLK_MASTER // for Boson
output pclk,
output locked_pclk,
`else
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
`endif
// TODO: get rid of pclk2x in histograms by doubling memories (making 1 write port and 2 read ones)
// How to erase?
// Alternative: copy/erase to a separate buffer in the beginning/end of a frame?
......@@ -386,6 +468,13 @@ module sensor_channel#(
inout [7:4] sns_dn74,
input sns_clkp,
input sns_clkn,
`elsif BOSON
input [3:0] sns_dp,
input [3:0] sns_dn,
inout [7:4] sns_dp74,
inout [7:4] sns_dn74,
input sns_clkp,
input sns_clkn,
`elsif LWIR
inout [ 4:0] sns_dp40,
inout [ 4:0] sns_dn40,
......@@ -395,8 +484,7 @@ module sensor_channel#(
inout [ 7:6] sns_dn76,
input sns_clkp,
input sns_clkn,
`else
`elsif PAR12
inout [7:0] sns_dp,
inout [7:0] sns_dn,
inout sns_clkp,
......@@ -406,7 +494,11 @@ module sensor_channel#(
inout sns_sda,
`ifdef HISPI
output sns_ctl,
`else
`elsif BOSON
output sns_ctl,
`elsif LWIR
inout sns_ctl,
`elsif PAR12
inout sns_ctl,
`endif
inout sns_pg,
......@@ -445,10 +537,10 @@ module sensor_channel#(
,input ext_rst_in,
input ext_rstseq_in,
output ext_rst_out,
output ext_rstseq_out
`endif
output ext_rstseq_out,
// currently used only for LWIR
,input khz // 1 KHz 50% @mclk
input khz // 1 KHz 50% @mclk
`endif
`ifdef DEBUG_RING
......@@ -481,6 +573,12 @@ module sensor_channel#(
`ifdef MON_HISPI
localparam SENSOR_TIMING_STATUS_REG = (SENSOR_TIMING_STATUS_REG_BASE + SENSOR_NUMBER * SENSOR_TIMING_STATUS_REG_INC);
`endif
/*
`elsif BOSON
`ifdef MON_HISPI
localparam SENSOR_TIMING_STATUS_REG = (SENSOR_TIMING_STATUS_REG_BASE + SENSOR_NUMBER * SENSOR_TIMING_STATUS_REG_INC);
`endif
*/
`endif
localparam SENS_SYNC_ADDR = SENSOR_BASE_ADDR + SENS_SYNC_RADDR;
// parameter SENSOR_BASE_ADDR = 'h300; // sensor registers base address
......@@ -506,19 +604,33 @@ module sensor_channel#(
wire [7:0] sens_phys_status_ad;
wire sens_phys_status_rq;
wire sens_phys_status_start;
`ifndef HISPI
`ifndef LWIR
`ifdef PAR12
wire ipclk; // Use in FIFO
wire [11:0] pxd_to_fifo;
wire vact_to_fifo; // frame active @posedge ipclk
wire hact_to_fifo; // line active @posedge ipclk
`endif
`endif
// only used for Boson
`ifdef BOSON
wire extif_dav; // data byte available for external interface
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
wire [1:0] extif_sel; // interface type (0 - internal, 1 - uart, 2,3 - reserved)
wire [7:0] extif_byte; // data to external interface (first - extif_sa)
wire extif_ready;// acknowledges extif_dav
wire extif_rst; // reset interface from i2c modulet
`endif
// data from FIFO
`ifdef LWIR
wire [15:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
`else
`elsif BOSON
wire [15:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
`elsif HISPI
wire [11:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
`elsif PAR12
wire [11:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
`endif
wire hact; // line active @posedge ipclk
......@@ -608,18 +720,18 @@ module sensor_channel#(
`ifdef DEBUG_RING
`ifdef HISPI
`elsif BOSON
`elsif LWIR
`else
`elsif PAR12
reg vact_to_fifo_r;
`endif
`ifdef LWIR
`ifdef LWIR
// reg hact_to_fifo_r;
reg [15:0] debug_line_cntr = 0;
reg [15:0] debug_lines = 0;
reg [15:0] hact_cntr = 0;
// reg [15:0] vact_cntr;
`else
`else
reg hact_to_fifo_r;
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
......@@ -642,6 +754,23 @@ module sensor_channel#(
if (prst) vact_cntr <= 0;
else if (sof) vact_cntr <= vact_cntr + 1;
end
`elsif BOSON
always @(posedge pclk) begin
// vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact;
if (sof) debug_line_cntr <= 0;
else if (hact && !hact_to_fifo_r) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
if (prst) hact_cntr <= 0;
else if (hact && !hact_to_fifo_r) hact_cntr <= hact_cntr + 1;
if (prst) vact_cntr <= 0;
else if (sof) vact_cntr <= vact_cntr + 1;
end
`elsif LWIR
// Something here?
......@@ -683,6 +812,8 @@ module sensor_channel#(
12'b0,
`elsif LWIR
12'b0,
`elsif BOSON
12'b0,
`else
pxd_to_fifo[11:0],
`endif
......@@ -795,6 +926,8 @@ module sensor_channel#(
.SENSI2C_TBL_NABRD (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
.SENSI2C_TBL_DLY (SENSI2C_TBL_DLY), // bit delay (number of mclk periods in 1/4 of SCL period)
.SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS),
.SENSI2C_TBL_EXTIF (SENSI2C_TBL_EXTIF),
.SENSI2C_TBL_EXTIF_BITS (SENSI2C_TBL_EXTIF_BITS),
.SENSI2C_DRIVE (SENSI2C_DRIVE),
.SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
......@@ -813,13 +946,30 @@ module sensor_channel#(
// division as in sof_out_mclk
.frame_num_seq (frame_num_seq), // input[3:0]
.scl (sns_scl), // inout
.sda (sns_sda) // inout
.sda (sns_sda), // inout
// interface for uart in write-only mode for short commands
`ifdef BOSON
.extif_dav (extif_dav), // output
// .extif_last (extif_last), // output
.extif_sel (extif_sel), // output[1:0]
.extif_byte (extif_byte), // output[7:0]
.extif_ready (extif_ready), // input
.extif_rst (extif_rst) // output
`else
.extif_dav (), // output
// .extif_last (), // output
.extif_sel (), // output[1:0]
.extif_byte (), // output[7:0]
.extif_ready (1'b0), // input
.extif_rst () // output
`endif
);
// debug_hist_mclk is never active, alive_hist0_rq == 0
// assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
// assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, debug_hist_mclk[0], alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
`ifndef HISPI
`ifndef HISPI
`ifndef BOSON
localparam STATUS_ALIVE_WIDTH = 8;
`ifndef LWIR
reg hact_r; // hact delayed by 1 cycle to generate start pulse
......@@ -893,7 +1043,8 @@ module sensor_channel#(
.busy() // output
);
`endif
`endif
`endif // `ifndef BOSON
`endif // `ifndef HISPI
//`ifndef LWIR
pulse_cross_clock pulse_cross_clock_eof_mclk_i (
......@@ -916,14 +1067,14 @@ module sensor_channel#(
.SENSIO_JTAG (SENSIO_JTAG),
.SENSIO_DELAYS (SENSIO_DELAYS),
.SENSIO_STATUS_REG (SENSIO_STATUS_REG),
`ifdef MON_HISPI
`ifdef MON_HISPI
.SENSOR_TIMING_BITS (SENSOR_TIMING_BITS),
.TIM_START (SENSOR_TIMING_START),
.TIM_LANE (SENSOR_TIMING_LANE),
.TIM_FROM (SENSOR_TIMING_FROM),
.TIM_TO (SENSOR_TIMING_TO),
.SENSOR_TIMING_STATUS_REG(SENSOR_TIMING_STATUS_REG), // localparam
`endif
`endif
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK),
......@@ -1012,6 +1163,109 @@ module sensor_channel#(
.sof (sof), // output
.eof (eof) // output
);
`elsif BOSON
wire vsync;
wire dvalid;
sens_103993 #(
.SENSIO_ADDR (SENSIO_ADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
.SENSIO_CTRL (SENSIO_CTRL),
.SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_DELAYS (SENSIO_DELAYS),
.SENSIO_STATUS_REG (SENSIO_STATUS_REG),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.PCLK_PHASE (IPCLK_PHASE), // use IPCLK* for PCLK*
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_PCLK (BUF_IPCLK), // use IPCLK* for PCLK*
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.NUMLANES (HISPI_NUMLANES),
.LVDS_DELAY_CLK (HISPI_DELAY_CLK),
.LVDS_MMCM (HISPI_MMCM),
.LVDS_CAPACITANCE (HISPI_CAPACITANCE),
.LVDS_DIFF_TERM (HISPI_DIFF_TERM),
.LVDS_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.LVDS_DQS_BIAS (HISPI_DQS_BIAS),
.LVDS_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.LVDS_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.LVDS_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.LVDS_IOSTANDARD (HISPI_IOSTANDARD),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.PXD_CAPACITANCE (PXD_CAPACITANCE)
) sens_103993_i (
.pclk (pclk), // output
.locked_pclk (locked_pclk), // output
.prst (prst), // input
.prsts (prsts), // output
.mclk (mclk), // input
.mrst (mrst), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (sens_phys_status_ad), // output[7:0]
.status_rq (sens_phys_status_rq), // output
.status_start (sens_phys_status_start), // input
// .trigger_mode (trigger_mode), // input
.ext_sync (trig), // input
.sns_dp (sns_dp[2:0]), // input[2:0]
.sns_dn (sns_dn[2:0]), // input[2:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.sns_gp2 (sns_dn74[6]), // inout
.sns_pgm (sns_pg), // inout
.sns_ext_sync (sns_ctl), // output
.sns_mrst (sns_dp74[7]), // output
.sns_gp3 (sns_dn74[7]), // output
.sns_gp0 (sns_dp74[5]), // output
.sns_gp1 (sns_dn74[5]), // output
.sns_txd (sns_dp74[4]), // input
.sns_rxd (sns_dn74[4]), // input
.pxd (pxd), // output[11:0]
.vsync (vsync), // output
.hsync (), // hsync), // output
.dvalid (dvalid), // output
// interface for uart in write-only mode for short commands
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
.extif_dav (extif_dav), // input
.extif_sel (extif_sel), // input[1:0]
.extif_byte (extif_byte), // input[7:0]
.extif_ready (extif_ready), // output
.extif_rst (extif_rst) // input
);
reg vsync_d;
always @(posedge pclk) begin
vsync_d <= vsync;
end
assign sof = vsync && !vsync_d;
assign eof = !vsync && vsync_d;
assign hact = dvalid;
`elsif LWIR
sens_lepton3 #(
.SENSIO_ADDR (SENSIO_ADDR),
......@@ -1099,9 +1353,9 @@ module sensor_channel#(
.dn2 (sns_dn40[2]), // input reserved
.dn6 (sns_dn76[6]), // input reserved
// reset synchronization
.ext_rst_in (ext_rst_in), // input
.ext_rstseq_in (ext_rstseq_in), // input
.ext_rst_out (ext_rst_out), // output
.ext_rst_in (ext_rst_in), // input
.ext_rstseq_in (ext_rstseq_in), // input
.ext_rst_out (ext_rst_out), // output
.ext_rstseq_out (ext_rstseq_out), // output
.khz (khz) // input 1 KHz 50% duty @ mclk
);
......@@ -1133,11 +1387,11 @@ module sensor_channel#(
.SENS_CTRL_ODD (SENS_CTRL_ODD),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
......@@ -1190,7 +1444,7 @@ module sensor_channel#(
.status_start (sens_phys_status_start) // input
);
// TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
// TODO NC393: This delay may be too long for serial sensors. Make them always start to fill the
// first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive -
// just continue.
......
sensor/sensor_i2c.v
View file @ 043d4849
......@@ -74,6 +74,8 @@ module sensor_i2c#(
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2,
parameter NUM_FRAME_BITS = 4
)(
input mrst, // @ posedge mclk
......@@ -95,10 +97,14 @@ module sensor_i2c#(
output scl_out, // i2c SCL output
output sda_out, // i2c SDA output
output scl_en, // i2c SCL enable
output sda_en // i2c SDA enable
// output busy,
// output [3:0] frame_num
output sda_en, // i2c SDA enable
// interface for uart in write-only mode for short commands
output extif_dav, // data byte available for external interface
// output extif_last, // last byte for external interface (with extif_dav)
output [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
output [7:0] extif_byte, // data to external interface (first - extif_sa)
input extif_ready, // acknowledges extif_dav
output extif_rst
);
// TODO: Make sure that using more than 64 commands will just send them during next frame, not loose?
// 0x0..0xf write directly to the frame number [3:0] modulo 16, except if you write to the frame
......@@ -116,12 +122,12 @@ module sensor_i2c#(
// [8] - set duration of quarter i2c cycle in system clock cycles - nominal value 100 (0x64)
// [7:0] - duration of quater i2c cycle (applied if [8] is set)
wire we_abs;
wire we_rel;
wire we_cmd;
wire wen;
wire [31:0] di;
wire [3:0] wa;
wire we_abs;
wire we_rel;
wire we_cmd;
wire wen;
wire [31:0] di;
wire [3:0] wa;
reg [31:0] di_r; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long
reg [3:0] wpage0; // FIFO page where ASAP writes go
reg [3:0] wpage_prev; // unused page, currently being cleared
......@@ -230,7 +236,7 @@ module sensor_i2c#(
assign sda_out = i2c_enrun? sda_hard: sda_soft ;
assign sda_en = i2c_enrun? sda_en_hard: sda_en_soft ;
assign fifo_wr_pointers_next = wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
assign extif_rst = reset_cmd;
/*
reg alive_fs;
......@@ -451,7 +457,9 @@ module sensor_i2c#(
.SENSI2C_TBL_NBRD_BITS (SENSI2C_TBL_NBRD_BITS),
.SENSI2C_TBL_NABRD (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
.SENSI2C_TBL_DLY (SENSI2C_TBL_DLY), // bit delay (number of mclk periods in 1/4 of SCL period)
.SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS)
.SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS),
.SENSI2C_TBL_EXTIF (SENSI2C_TBL_EXTIF),
.SENSI2C_TBL_EXTIF_BITS (SENSI2C_TBL_EXTIF_BITS)
) sensor_i2c_prot_i(
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -460,7 +468,8 @@ module sensor_i2c#(
.active_sda (active_sda), // input
.early_release_0 (early_release_0), // input
.tand (di_r[SENSI2C_CMD_TAND]), // input
.td (di_r[SENSI2C_CMD_TAND-1:0]), // input[27:0]
// .td (di_r[SENSI2C_CMD_TAND-1:0]), // input[27:0]
.td (di_r), // input[27:0]
.twe (twe), // input
.sda_in (sda_in), // input
.sda (sda_hard), // output
......@@ -472,7 +481,13 @@ module sensor_i2c#(
.seq_mem_re (seq_mem_re), // output[1:0]
.seq_rd (i2c_data), // input[7:0]
.rdata (i2c_rdata), // output[7:0]
.rvalid (i2c_rvalid) // output
.rvalid (i2c_rvalid), // output
// interface for uart in write-only mode for short commands
.extif_dav (extif_dav), // output
// .extif_last (extif_last), // output
.extif_sel (extif_sel), // output[1:0]
.extif_byte (extif_byte), // output[7:0]
.extif_ready (extif_ready) // input
);
......
sensor/sensor_i2c_io.v
View file @ 043d4849
......@@ -73,6 +73,8 @@ module sensor_i2c_io#(
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2,
// I/O parameters
parameter integer SENSI2C_DRIVE = 12,
parameter SENSI2C_IBUF_LOW_PWR = "TRUE",
......@@ -95,7 +97,14 @@ module sensor_i2c_io#(
input eof_mclk, // End of frame for i2c sequencer (will not work for linescan mode: either disable or make division upsteram
input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer (to sync i2c)
inout scl,
inout sda
inout sda,
// interface for uart in write-only mode for short commands
output extif_dav, // data byte available for external interface
// output extif_last, // last byte for external interface (with extif_dav)
output [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
output [7:0] extif_byte, // data to external interface (first - extif_sa)
input extif_ready, // acknowledges extif_dav
output extif_rst // reset external interface from i2c command
);
wire scl_in;
wire sda_in;
......@@ -137,6 +146,8 @@ module sensor_i2c_io#(
.SENSI2C_TBL_NABRD (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
.SENSI2C_TBL_DLY (SENSI2C_TBL_DLY), // bit delay (number of mclk periods in 1/4 of SCL period)
.SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS),
.SENSI2C_TBL_EXTIF (SENSI2C_TBL_EXTIF),
.SENSI2C_TBL_EXTIF_BITS (SENSI2C_TBL_EXTIF_BITS),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sensor_i2c_i (
.mrst (mrst), // input
......@@ -154,7 +165,14 @@ module sensor_i2c_io#(
.scl_out (scl_out), // output
.sda_out (sda_out), // output
.scl_en (scl_en), // output
.sda_en (sda_en) // output
.sda_en (sda_en), // output
// interface for uart in write-only mode for short commands
.extif_dav (extif_dav), // output
// .extif_last (extif_last), // output
.extif_sel (extif_sel), // output[1:0]
.extif_byte (extif_byte), // output[7:0]
.extif_ready (extif_ready), // input
.extif_rst (extif_rst) // output
);
iobuf #(
......
sensor/sensor_i2c_prot.v
View file @ 043d4849
......@@ -50,7 +50,9 @@ module sensor_i2c_prot#(
parameter SENSI2C_TBL_NBRD_BITS = 3,
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8
parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2
)(
input mrst, // @ posedge mclk
input mclk, // global clock
......@@ -60,7 +62,8 @@ module sensor_i2c_prot#(
input early_release_0,// global config bit: release SDA immediately after end of SCL if next bit is 1 (for ACKN). Data hold time by slow 0->1
// setup LUT to translate address page into SA, actual address MSB and number of bytes to write (second word bypasses translation)
input tand, // table address/not data
input [27:0] td, // table address/data in
// input [27:0] td, // table address/data in
input [31:0] td, // table address/data in
input twe, // table write enable
input sda_in, // data from sda pad
output sda,
......@@ -72,7 +75,15 @@ module sensor_i2c_prot#(
output [ 1:0] seq_mem_re, // [0] - re, [1] - regen to the sequencer memory
input [ 7:0] seq_rd, // data from the sequencer memory
output [ 7:0] rdata,
output rvalid
output rvalid,
// interface for uart in write-only mode for short commands
// output extif_rst, // reset external uinterface - use i2c_rst
output extif_dav, // data byte available for external interface
// output extif_last, // last byte for external interface (with extif_dav)
output [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
// output [6:0] extif_sa, // "slave address" - used as extra attributes (data width) - valid during extif_run
output [7:0] extif_byte, // data to external interface (first - extif_sa)
input extif_ready // acknowledges extif_dav
);
/*
Sequencer provides 4 bytes per command, read one byte at a time as seq_rd[7:0] with byte address provided by seq_mem_ra[1:0],
......@@ -111,27 +122,21 @@ module sensor_i2c_prot#(
reg [ 6:0] run_reg_wr; // run register write [6] - start, [5] - send sa, [4] - send high byte (from table),..[0] - send stop
reg [ 4:0] run_extra_wr; // continue register write (if more than sa + 4bytes) [4] - byte 3, .. [1]- byte0, [0] - stop
reg [ 7:0] run_reg_rd; // [7] - start, [6] SA (byte 3), [5] (optional) - RA_msb, [4] - RA_lsb, [3] - restart, [2] - SA, [1] - read bytes, [0] - stop
reg [ 4:0] run_reg_ext_wr; // [4] - SA (attr), [3] - RA_msb (module) [2] - RA_lsb (func), [1] - DH, [0] - DL (DH, DL - optional)?
reg run_extra_wr_d; // any of run_extra_wr bits, delayed by 1
reg run_any_d; // any of command states, delayed by 1
reg [1:0] pre_cmd; // from i2c_start until run_any_d will be active
reg first_mem_re;
// reg i2c_done;
// wire i2c_next_byte;
reg [ 2:0] mem_re;
reg mem_valid;
reg [ 2:0] table_re;
// reg read_mem_msb;
// wire decode_reg_rd = &seq_rd[7:4];
// wire start_wr_seq_w = !run_extra_wr_d && !decode_reg_rd && read_mem_msb;
wire start_wr_seq_w = table_re[2] && !tdout[SENSI2C_TBL_RNWREG];
wire start_rd_seq_w = table_re[2] && tdout[SENSI2C_TBL_RNWREG];
wire is_extif = (|tdout[SENSI2C_TBL_EXTIF +: SENSI2C_TBL_EXTIF_BITS]);
wire start_wr_seq_w = table_re[2] && !is_extif && !tdout[SENSI2C_TBL_RNWREG]; // [8]
wire start_rd_seq_w = table_re[2] && !is_extif && tdout[SENSI2C_TBL_RNWREG]; // [8]
wire start_extra_seq_w = i2c_start && (bytes_left_send !=0);
wire start_extif_w = table_re[2] && (is_extif);
// wire snd_start_w = run_reg_wr[6] || 1'b0; // add start & restart of read
// wire snd_stop_w = run_reg_wr[0] || 1'b0; // add stop of read
// wire snd9_w = (|run_reg_wr[5:1]) || 1'b0; // add for read and extra write;
reg snd_start;
reg snd_stop;
reg snd9;
......@@ -152,7 +157,14 @@ module sensor_i2c_prot#(
reg next_cmd; // i2c command (start/stop/data) accepted, proceed to the next stage
reg next_cmd_d; // next cycle after next_cmd (first at new state)
wire pre_next_cmd = (snd_start || snd_stop || snd9) && i2c_rdy;
reg next_byte_wr;
wire next_byte_wr_w;
// reg next_byte_wr;
reg next_byte_wr_or_ext; // write byte or extrenal command
reg extif_dav_r;
reg extif_run;
wire extif_next_w;
// reg extif_ackn;
wire pre_next_extif = extif_run && extif_ready && extif_dav && !next_cmd && !next_cmd_d; // TODO: Verify last terms
reg read_address_bytes; // 0 - single-byte register adderss, 1 - two-byte register address
reg [ 2:0] read_data_bytes; // 1..8 bytes to read from the i2c slave (0 is 8!)
......@@ -163,59 +175,94 @@ module sensor_i2c_prot#(
wire pre_table_re = !run_extra_wr_d && first_mem_re && mem_re[1];
reg rnw; // last command was read (not write) - do not increment bytes_left_send
// wire dout_stb; // rvalid
// reg [ 6:0] extif_sa_r;
reg [ 7:0] extif_byte_r;
reg [ 1:0] extif_sel_r;
wire extif_last;
assign seq_mem_re = mem_re[1:0];
// assign rvalid = dout_stb && run_reg_rd[1];
assign seq_mem_re = mem_re[1:0];
assign next_byte_wr_w = snd9 && i2c_rdy && !run_reg_wr[5] && !rnw;
assign extif_dav = extif_dav_r;
assign extif_next_w = |run_reg_ext_wr[3:0];
// assign extif_sa = extif_sa_r;
assign extif_byte = extif_byte_r;
assign extif_sel = extif_sel_r;
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
assign extif_last = bytes_left_send == 0;
// assign extif_last = extif_last_w;
always @ (posedge mclk) begin
if (mrst || i2c_rst || start_wr_seq_w) rnw <= 0;
else if (start_rd_seq_w) rnw <= 1;
run_extra_wr_d <= |run_extra_wr;
run_any_d <= (|run_reg_wr) || (|run_extra_wr) || (|run_reg_rd);
run_any_d <= (|run_reg_wr) || (|run_extra_wr) || (|run_reg_rd) || extif_run; // includes external interface
if (mrst || i2c_rst) first_mem_re <= 0;
else if (i2c_start) first_mem_re <= 1;
else if (mem_re[2]) first_mem_re <= 0;
if (mrst || i2c_rst) pre_cmd <= 0;
else if (i2c_start) pre_cmd <= 1;
else if (i2c_start) pre_cmd <= 1; // extif also
else if (run_any_d) pre_cmd <= 0;
if (mrst || i2c_rst) i2c_run <= 0;
else i2c_run <= i2c_start || pre_cmd || run_any_d;
if (mrst || i2c_rst) i2c_busy <= 0;
else i2c_busy <= i2c_start || pre_cmd || run_any_d || bus_busy || bus_open;
else i2c_busy <= i2c_start || pre_cmd || run_any_d || bus_busy || bus_open; // includes external interface
table_re <= {table_re[1:0], pre_table_re}; // start_wr_seq_w};
if (table_re[2]) begin
reg_ah <= tdout[SENSI2C_TBL_RAH +: SENSI2C_TBL_RAH_BITS]; //[ 7:0]; // MSB of the register address (instead of the byte 2)
reg_ah <= tdout[SENSI2C_TBL_RAH +: SENSI2C_TBL_RAH_BITS]; // [ 7:0]; // MSB of the register address (instead of the byte 2)
num_bytes_send <= tdout[SENSI2C_TBL_NBWR +: SENSI2C_TBL_NBWR_BITS] ; // [19:16]; // number of bytes to send (if more than 4 will skip stop and continue with next data
i2c_dly <= tdout[SENSI2C_TBL_DLY +: SENSI2C_TBL_DLY_BITS]; //[27:20];
i2c_dly <= tdout[SENSI2C_TBL_DLY +: SENSI2C_TBL_DLY_BITS]; // [27:20];
extif_sel_r <= tdout[SENSI2C_TBL_EXTIF +: SENSI2C_TBL_EXTIF_BITS]; // [30:31]
end
if (table_re[2]) slave_a_rah <= {tdout[SENSI2C_TBL_SA +: SENSI2C_TBL_SA_BITS], 1'b0}; // {tdout[15:9], 1'b0};
else if (next_cmd && run_reg_wr[5]) slave_a_rah <= reg_ah; // will copy even if not used
// wire pre_next_cmd = (snd_start || snd_stop || snd9) && i2c_rdy;
next_cmd <= pre_next_cmd;
// if (table_re[2]) extif_sa_r <= tdout[SENSI2C_TBL_SA +: SENSI2C_TBL_SA_BITS];
if (table_re[2]) extif_byte_r <= {1'b0, tdout[SENSI2C_TBL_SA +: SENSI2C_TBL_SA_BITS]};
else if (next_cmd && extif_run) extif_byte_r <= run_reg_ext_wr[4]? reg_ah : seq_rd;
next_cmd <= pre_next_cmd || pre_next_extif;
next_cmd_d <= next_cmd;
next_byte_wr <= snd9 && i2c_rdy && !run_reg_wr[5] && !rnw; // (|run_reg_rd); // same time as next_cmd, no pulse when sending SA during write
// snd_start <= snd_start_w; // add & i2c_ready? Not really needed as any i2c stage will be busy for long enough
// snd_stop <= snd_stop_w;
// snd9 <= snd9_w;
// same time as next_cmd, no pulse when sending SA during write
// next_byte_wr <= next_byte_wr_w; // snd9 && i2c_rdy && !run_reg_wr[5] && !rnw; // (|run_reg_rd); // same time as next_cmd, no pulse when sending SA during write
next_byte_wr_or_ext <= next_byte_wr_w || extif_next_w;
// counting bytes (and address) in extif mode also
if (mrst || i2c_rst) bytes_left_send <= 0;
else if (start_wr_seq_w) bytes_left_send <= tdout[SENSI2C_TBL_NBWR +: SENSI2C_TBL_NBWR_BITS]; // num_bytes_send;
else if (next_byte_wr) bytes_left_send <= bytes_left_send - 1;
else if (start_wr_seq_w || start_extif_w) bytes_left_send <= tdout[SENSI2C_TBL_NBWR +: SENSI2C_TBL_NBWR_BITS]; // num_bytes_send;
/// else if (next_byte_wr) bytes_left_send <= bytes_left_send - 1;
else if (next_byte_wr_or_ext) bytes_left_send <= bytes_left_send - 1;
// extif_ackn <= !i2c_rst && extif_ready && extif_dav;
if (mrst || i2c_rst) extif_run <= 0;
else if (start_extif_w) extif_run <= 1;
else if (extif_ready && extif_dav && extif_last) extif_run <= 0;
if (mrst || i2c_rst) extif_dav_r <= 0;
else if (start_extif_w || (extif_run && mem_re[2]) || (run_reg_ext_wr[3] && next_cmd_d)) extif_dav_r <= 1;
else if (next_cmd) extif_dav_r <= 0;
// calculate stages for each type of commands
// start and write sa and some bytes, stop if number of bytes <= 4 at the end
if (mrst || i2c_rst) run_reg_ext_wr <= 0;
else if (start_extif_w) run_reg_ext_wr <= 5'h10;
else if (next_cmd) run_reg_ext_wr <= {1'b0, // SA (attr)
run_reg_ext_wr[4], // RA_msb (module) - always after SA (attr)
run_reg_ext_wr[3], // RA_lsb (func)
run_reg_ext_wr[2] & (num_bytes_send == 4'h2), // DH
run_reg_ext_wr[1] | (run_reg_ext_wr[2] & (num_bytes_send == 4'h1)) // DL
};
if (mrst || i2c_rst) run_reg_wr <= 0;
else if (start_wr_seq_w) run_reg_wr <= 7'h40;
else if (next_cmd) run_reg_wr <= {1'b0, // first "start"
......@@ -226,6 +273,8 @@ module sensor_i2c_prot#(
run_reg_wr[2] | (run_reg_wr[5] & (num_bytes_send == 4'h1)), // byte 0 (from input)
run_reg_wr[1] & (bytes_left_send == 4'h1)
};
// send just bytes (up to 4), stop if nothing left
if (mrst || i2c_rst) run_extra_wr <= 0;
else if (start_extra_seq_w) run_extra_wr <= {
......@@ -243,18 +292,13 @@ module sensor_i2c_prot#(
run_extra_wr[1] & (bytes_left_send == 4'h1)
};
// reg [ 7:0] run_reg_rd; // [7] - start, [6] SA (byte 3), [5] (optional) - RA_msb, [4] - RA_lsb, [3] - restart, [2] - SA, [1] - read bytes, [0] - stop
// if (table_re[2] && tdout[8]) read_address_bytes <= tdout[19];
if (table_re[2] && tdout[SENSI2C_TBL_RNWREG]) read_address_bytes <= tdout[SENSI2C_TBL_NABRD]; // [19];
// if (table_re[2] && tdout[8]) read_data_bytes <= tdout[18:16];
if (table_re[2] && tdout[SENSI2C_TBL_RNWREG]) read_data_bytes <= tdout[SENSI2C_TBL_NBRD +: SENSI2C_TBL_NBRD_BITS];
else if (run_reg_rd[1] && next_cmd) read_data_bytes <= read_data_bytes - 1;
// read i2c data
if (mrst || i2c_rst) run_reg_rd <= 0;
// else if (!run_extra_wr_d && decode_reg_rd && read_mem_msb) run_reg_rd <= 8'h80;
else if (start_rd_seq_w) run_reg_rd <= 8'h80;
else if (next_cmd) run_reg_rd <= {1'b0, // first "start"
run_reg_rd[7], // slave_addr - always after start (bit0 = 0)
......@@ -267,13 +311,14 @@ module sensor_i2c_prot#(
};
// read sequencer memory byte (for the current word)
mem_re <= {mem_re[1:0], i2c_start | next_cmd_d & (
(~extif_last & (|run_reg_ext_wr[3:0])) |
(|run_reg_wr[3:1]) |
(|run_extra_wr[4:1]) |
(|run_reg_rd[6:4]))};
initial_address <= initial_address_w[1:0]; // if bytes left to send is 0 mod 4 - will be 3 (read MSB)
seq_mem_ra <= i2c_start ? initial_address : { // run_extra_wr[4] is not needed - it will be read by i2c_start
run_reg_wr[3] | run_extra_wr[3] | run_reg_rd[6],
run_reg_wr[2] | run_extra_wr[2] | run_reg_rd[5]
run_reg_wr[3] | run_extra_wr[3] | run_reg_rd[6] | run_reg_ext_wr[3], //?
run_reg_wr[2] | run_extra_wr[2] | run_reg_rd[5] | run_reg_ext_wr[1] //?
};
if (mrst || i2c_rst || i2c_start || next_cmd ) mem_valid <= 0;
else if (mem_re[2]) mem_valid <= 1;
......@@ -302,6 +347,8 @@ module sensor_i2c_prot#(
2'h3: sr_in <= {8'hff,(read_data_bytes == 3'h1)};
endcase
end
sensor_i2c_scl_sda sensor_i2c_scl_sda_i (
......@@ -349,7 +396,8 @@ module sensor_i2c_prot#(
.waddr ({1'b0, twa}), // input[8:0]
.we (twe && !tand), // input
.web (4'hf), // input[3:0]
.data_in ({4'b0, td}) // input[31:0]
// .data_in ({4'b0, td}) // input[31:0]
.data_in (td) // input[31:0]
);
......
sensor/sensors393.v
View file @ 043d4849
......@@ -7,7 +7,7 @@
* @brief 4-channel sensor subsystem
* Uniform, assuming the same sensors/multiplexers, common pixel clock
*
* @copyright Copyright (c) 2015 Elphel, Inc .
* @copyright Copyright (c) 2015-2020 Elphel, Inc .
*
* <b>License:</b>
*
......@@ -41,8 +41,9 @@
module sensors393 #(
// parameters, individual to sensor channels and those likely to be modified
parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
// moving to the end to be always present
// parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
// parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locations) relative to SENSOR_GROUP_ADDR
......@@ -162,18 +163,34 @@ module sensors393 #(
// sens_parallel12 registers
parameter SENSIO_CTRL = 'h0,
parameter SENS_CTRL_MRST = 0, // 1: 0
`ifndef BOSON
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
`endif
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
`ifdef HISPI
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
`elsif BOSON
// ???
`else
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
`elsif BOSON
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7
`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
......@@ -181,15 +198,20 @@ module sensors393 #(
parameter SENS_CTRL_QUADRANTS_EN = 20, // 18:12, enable - 20 (1 bits reserved)
`endif
parameter SENSIO_STATUS = 'h1,
`ifndef BOSON
parameter SENSIO_JTAG = 'h2,
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
`ifndef HISPI
`endif
`ifdef HISPI
`elsif BOSON
`else
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
`endif
`endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
`endif // `ifdef LWIR
......@@ -204,6 +226,18 @@ module sensors393 #(
parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif
`elsif BOSON
/*
`ifdef MON_HISPI
parameter SENSOR_TIMING_STATUS_REG_BASE = 'h40, // 4 locations" x40, x41, x42, x43
parameter SENSOR_TIMING_STATUS_REG_INC = 1, // increment to the next sensor
parameter SENSOR_TIMING_BITS = 24, // increment to the next sensor
parameter SENSOR_TIMING_START = 16, // bit # in JTAB control word to start timing measurement (now f = 660/4 = 165)
parameter SENSOR_TIMING_LANE = 14, // 15:14 - select lane
parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif
*/
`endif
// 4 of 8-bit delays per register
......@@ -229,6 +263,7 @@ module sensors393 #(
parameter SENSI2C_SLEW = "SLOW",
`ifdef HISPI
`elsif BOSON
`elsif LWIR
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
......@@ -297,63 +332,67 @@ module sensors393 #(
parameter SENS_SYNC_LBITS = 16, // number of bits in a line counter for sof_late output (limited by eof)
parameter SENS_SYNC_LATE_DFLT = 4, // 15, // number of lines to delay late frame sync
parameter SENS_SYNC_MINBITS = 8, // number of bits to enforce minimal frame period
parameter SENS_SYNC_MINPER = 130 // minimal frame period (in pclk/mclk?)
parameter SENS_SYNC_MINPER = 130, // minimal frame period (in pclk/mclk?)
// sens_parallel12 other parameters
// parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
// start with comma
`ifdef LWIR
`else
,parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE"
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 200, // was 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
`endif
// start with comma
`ifdef HISPI
,parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4
parameter PXD_CLK_DIV_BITS = 4,
`elsif BOSON
parameter PXD_CAPACITANCE = "DONT_CARE",
`endif
// start with comma
`ifdef LWIR
`else
.parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED" //"OPTIMIZED", "HIGH","LOW"
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
`endif
// start with comma
`ifdef LWIR
,parameter SENSI2C_IOSTANDARD = "LVCMOS18"
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`elsif HISPI
,parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18"
`else
,parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`elsif BOSON
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`elsif PAR12
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25"
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif
// start with comma
`ifdef LWIR
`else
,parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
......@@ -366,12 +405,12 @@ module sensors393 #(
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
`endif
`ifdef HISPI
,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK0= "FALSE",
parameter HISPI_DELAY_CLK1= "FALSE",
......@@ -392,24 +431,61 @@ module sensors393 #(
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`elsif BOSON
// parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 3,
parameter HISPI_DELAY_CLK0= "FALSE",
parameter HISPI_DELAY_CLK1= "FALSE",
parameter HISPI_DELAY_CLK2= "FALSE",
parameter HISPI_DELAY_CLK3= "FALSE",
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "TRUE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "TRUE",
// parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
// parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
// parameter HISPI_FIFO_DEPTH = 4,
// parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2
parameter DEBUG_CMD_LATENCY = 2,
`endif
// parameter real REFCLK_FREQUENCY = 200.0,
// parameter HIGH_PERFORMANCE_MODE = "FALSE"
parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
parameter SENSOR_BASE_INC = 'h040 // increment for sesor channel
) (
// input rst,
// will generate it here
`ifdef PCLK_MASTER
output [3:0] pclk,
output [3:0] locked_pclk,
`else
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
`endif
`ifdef USE_PCLK2X
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
`endif
input ref_clk, // IODELAY calibration
input dly_rst,
input mrst, // @posedge mclk, sync reset
`ifdef PCLK_MASTER
input [3:0] prst,
`else
input prst, // @posedge pclk, sync reset
`endif
input arst, // @posedge aclk, sync reset
// programming interface
......@@ -419,7 +495,6 @@ module sensors393 #(
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
// I/O pads, pin names match circuit diagram (each sensor)
`ifdef HISPI
input [15:0] sns_dp,
......@@ -428,6 +503,13 @@ module sensors393 #(
inout [15:0] sns_dn74, // SuppressThisWarning all - unused yet
input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
`elsif BOSON
input [15:0] sns_dp,
input [15:0] sns_dn,
inout [15:0] sns_dp74, // SuppressThisWarning all - unused yet
inout [15:0] sns_dn74, // SuppressThisWarning all - unused yet
input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
`elsif LWIR
inout [19:0] sns_dp40,
inout [19:0] sns_dn40,
......@@ -448,6 +530,8 @@ module sensors393 #(
`ifdef HISPI
inout [3:0] sns_ctl, // SuppressThisWarning all - output-only in HiSPi mode
`elsif BOSON
inout [3:0] sns_ctl, // SuppressThisWarning all - output-only in HiSPi mode
`else
inout [3:0] sns_ctl,
`endif
......@@ -507,8 +591,10 @@ module sensors393 #(
`ifdef DEBUG_SENS_MEM_PAGES
,output [2 * 4 - 1 : 0] dbg_rpage
,output [2 * 4 - 1 : 0] dbg_wpage
`endif
`endif
`ifdef LWIR
,input khz // 1 KHz 50% @mclk
`endif
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
......@@ -545,7 +631,8 @@ module sensors393 #(
wire [4*NUM_FRAME_BITS-1:0] frame_num = {frame_num3, frame_num2, frame_num1, frame_num0};
wire [4*NUM_FRAME_BITS-1:0] hist_frame; // frame numbers of the histogram outputs
`ifdef LWIR
wire ext_rst_in;
wire ext_rstseq_in;
wire [3:0] ext_rst_out;
......@@ -553,6 +640,7 @@ module sensors393 #(
assign ext_rst_in = |ext_rst_out;
assign ext_rstseq_in = |ext_rstseq_out;
`endif
always @ (posedge mclk) begin
cmd_ad <= cmd_ad_in;
......@@ -563,7 +651,8 @@ module sensors393 #(
genvar i;
for (i=0; i < 4; i=i+1) begin: sensor_channel_block
sensor_channel #(
.SENSOR_NUMBER (i),
// moving to the end to be always present
// .SENSOR_NUMBER (i),
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
.SENSOR_BASE_INC (SENSOR_BASE_INC),
.SENSI2C_STATUS_REG_BASE (SENSI2C_STATUS_REG_BASE),
......@@ -662,11 +751,16 @@ module sensors393 #(
`else
.SENSIO_CTRL (SENSIO_CTRL),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`ifndef BOSON
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`endif
`ifdef HISPI
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
`elsif BOSON
// Anything for BOSON?
`else
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
`endif
......@@ -674,6 +768,16 @@ module sensors393 #(
`ifdef HISPI
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
`elsif BOSON
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
`else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD),
......@@ -681,13 +785,17 @@ module sensors393 #(
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
`endif
.SENSIO_STATUS (SENSIO_STATUS),
`ifndef BOSON
.SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
`ifndef HISPI
`endif
`ifdef HISPI
`elsif BOSON
`else
.SENSIO_WIDTH (SENSIO_WIDTH),
`endif
.SENSIO_DELAYS (SENSIO_DELAYS),
......@@ -703,7 +811,19 @@ module sensors393 #(
.SENSOR_TIMING_FROM (SENSOR_TIMING_FROM),
.SENSOR_TIMING_TO (SENSOR_TIMING_TO),
`endif
`endif
`elsif BOSON
/*
`ifdef MON_HISPI
.SENSOR_TIMING_STATUS_REG_BASE (SENSOR_TIMING_STATUS_REG_BASE),
.SENSOR_TIMING_STATUS_REG_INC (SENSOR_TIMING_STATUS_REG_INC),
.SENSOR_TIMING_BITS (SENSOR_TIMING_BITS),
.SENSOR_TIMING_START (SENSOR_TIMING_START),
.SENSOR_TIMING_LANE (SENSOR_TIMING_LANE),
.SENSOR_TIMING_FROM (SENSOR_TIMING_FROM),
.SENSOR_TIMING_TO (SENSOR_TIMING_TO),
`endif
*/
`endif
.SENSI2C_ABS_RADDR (SENSI2C_ABS_RADDR),
.SENSI2C_REL_RADDR (SENSI2C_REL_RADDR),
.SENSI2C_ADDR_MASK (SENSI2C_ADDR_MASK),
......@@ -721,6 +841,11 @@ module sensors393 #(
.SENSI2C_SLEW (SENSI2C_SLEW),
.NUM_FRAME_BITS (NUM_FRAME_BITS),
`ifdef HISPI
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`elsif BOSON
.PXD_CAPACITANCE (PXD_CAPACITANCE),
`elsif LWIR
.VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
......@@ -766,37 +891,23 @@ module sensors393 #(
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap)
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS) // 185
`else
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS), // 185
`else // parallel only
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY)
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
`endif
// start with comma
`ifdef LWIR
`else
,.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
// aLL SENSORS
.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
`endif
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
// start with comma
`ifdef LWIR
`elsif HISPI
,.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`endif
// start with comma
`ifdef LWIR
`else
,.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
......@@ -810,11 +921,9 @@ module sensors393 #(
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
`endif
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
`ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK ((i & 2) ? ((i & 1) ? HISPI_DELAY_CLK3 : HISPI_DELAY_CLK2) : ((i & 1) ?HISPI_DELAY_CLK1 : HISPI_DELAY_CLK0 )),
......@@ -830,19 +939,51 @@ module sensors393 #(
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
.HISPI_IOSTANDARD (HISPI_IOSTANDARD),
`elsif BOSON
// .HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK ((i & 2) ? ((i & 1) ? HISPI_DELAY_CLK3 : HISPI_DELAY_CLK2) : ((i & 1) ?HISPI_DELAY_CLK1 : HISPI_DELAY_CLK0 )),
.HISPI_MMCM ((i & 2) ? ((i & 1) ? HISPI_MMCM3 : HISPI_MMCM2) : ((i & 1) ?HISPI_MMCM1 : HISPI_MMCM0 )),
// .HISPI_KEEP_IRST (HISPI_KEEP_IRST),
// .HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
// .HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
// .HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD),
`endif
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY),
`endif
// .REFCLK_FREQUENCY (REFCLK_FREQUENCY), // 200.0,
// .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), // = "FALSE"
.SENSOR_NUMBER (i)
) sensor_channel_i (
`ifdef PCLK_MASTER
.pclk (pclk[i]), // input
.locked_pclk (locked_pclk[i]), // input
`else
.pclk (pclk), // input
`endif
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // input
`endif
.mrst (mrst), // input
`ifdef PCLK_MASTER
.prst (prst[i]), // input
`else
.prst (prst), // input
`endif
`ifdef HISPI
.sns_dp (sns_dp[i * 4 +: 4]), // input[3:0]
.sns_dn (sns_dn[i * 4 +: 4]), // input[3:0]
......@@ -850,6 +991,13 @@ module sensors393 #(
.sns_dn74 (sns_dn74[i * 4 +: 4]), // input[3:0]
.sns_clkp (sns_clkp[i]), // input
.sns_clkn (sns_clkn[i]), // input
`elsif BOSON
.sns_dp (sns_dp[i * 4 +: 4]), // input[3:0]
.sns_dn (sns_dn[i * 4 +: 4]), // input[3:0]
.sns_dp74 (sns_dp74[i * 4 +: 4]), // input[3:0]
.sns_dn74 (sns_dn74[i * 4 +: 4]), // input[3:0]
.sns_clkp (sns_clkp[i]), // input
.sns_clkn (sns_clkn[i]), // input
`elsif LWIR
.sns_dp40 (sns_dp40[i * 5 +: 5]), // input[4:0]
.sns_dn40 (sns_dn40[i * 5 +: 5]), // input[4:0]
......@@ -898,8 +1046,8 @@ module sensors393 #(
.ext_rstseq_in (ext_rstseq_in), // input
.ext_rst_out (ext_rst_out[i]), // output
.ext_rstseq_out (ext_rstseq_out[i]) // output
`endif
,.khz (khz) // input 1 KHz 50% duty
`endif
`ifdef DEBUG_RING
,.debug_do (debug_ring[i]), // output
......@@ -911,8 +1059,13 @@ module sensors393 #(
sensor_membuf #(
.WADDR_WIDTH(9)
) sensor_membuf_i (
`ifdef PCLK_MASTER
.pclk (pclk[i]), // input
.prst (prst[i]), // input
`else
.pclk (pclk), // input
.prst (prst), // input
`endif
.mrst (mrst), // input
.frame_run_mclk(frame_run_mclk[i]), // input @mclk - memory channel is ready to accept data from the sensor
.px_data (px_data[16 * i +: 16]), // input[15:0]
......
sensor/serial_103993.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> serial_103993
* @file serial_103993.v
* @date 2020-12-18
* @author eyesis
*
* @brief Serial interface to communicate with Boson (software r/w any, sequencer - short writes)
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* serial_103993.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* serial_103993.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module serial_103993#(
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
parameter REPLACED_START_FRAME_BYTE = 'h81,
parameter REPLACED_END_FRAME_BYTE = 'hA1,
parameter REPLACED_ESCAPE_BYTE = 'h91,
parameter INITIAL_CRC16 = 16'h1d0f,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60,
parameter EXTIF_MODE = 1 // 1,2 or 3 if there are several different extif
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output txd, // serial data out
input rxd, // serial data in
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
// interface for uart in write-only mode for short commands
// 1-st byte - SA (use 2 LSB to select 0,1,2 data bytes
// 2-nd byte module
// 3-rd byte function
// 4 (optional) data[15:8] or data[7:0] if last
// 5 (optional) data[7:0]
input extif_dav, // data byte available for external interface
// input extif_last, // last byte for external interface (with extif_dav)
input [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
input [7:0] extif_byte, // data to external interface (first - extif_sa)
output extif_ready, // acknowledges extif_dav
input extif_rst, // reset seq xmit and sequence number
// software interface (byte R/W)
input extif_en, // enable transmission from the sequencer
input xmit_rst, // reset (soft xmit only)
input xmit_start, // all in programmatic FIFO
input [7:0] xmit_data, // write data byte
input xmit_stb, // write data strobe
output xmit_busy,
input recv_rst, // reset read uart FIFO
input recv_next,
output recv_prgrs, // read in progress
output recv_dav, // read byte available
output [7:0] recv_data
);
wire [ 7:0] xmit_fifo_out;
wire [ 1:0] xmit_fifo_re_regen;
wire [10:0] xmit_fifo_waddr;
wire [10:0] xmit_fifo_raddr;
// wire [11:0] xmit_fifo_fill;
// reg xmit_fifo_rd;
wire xmit_fifo_nempty;
wire recv_fifo_wr;
wire [ 1:0] recv_fifo_re_regen;
wire [10:0] recv_fifo_waddr;
wire [10:0] recv_fifo_raddr;
// wire [11:0] recv_fifo_fill;
wire [ 7:0] recv_fifo_din;
reg xmit_pend; // initiated soft xmit
reg xmit_run; // runing soft xmit
reg xmit_run_d; // runing soft xmit, delayed
reg extif_run; // running xmit from the sequencer
reg extif_run_d; // running xmit from the sequencer
wire [ 7:0] xmit_extif_data; // data byte to transmit from the sequencer
reg xmit_stb_fifo;
reg xmit_stb_seq;
reg xmit_over_fifo;
reg xmit_over_seq;
reg xmit_stb_d;
reg xmit_over_d;
reg stuffer_busy_d;
reg xmit_busy_r;
wire xmit_start_out_fifo;
wire xmit_start_out_seq;
wire xmit_start_out;
reg xmit_done; // any mode - soft or seq;
wire extif_rq_w;
wire [ 7:0] xmit_any_data;
wire xmit_stb_any;
wire xmit_over;
wire tx_rdy; // transmit IF ready to accept byte
wire pre_tx_stb;
wire stuffer_busy; // output processing packet (not including UART)
wire uart_tx_busy; // output UART busy ('or' with stuffer_busy?)
// // soft seq number may always use >0xffff to distinguish
wire packet_ready_seq;
wire packet_over_seq;
// wire packet_sent;
assign extif_rq_w = packet_ready_seq && !extif_run && !packet_over_seq;
assign xmit_any_data = extif_run ? xmit_extif_data : xmit_fifo_out;
assign xmit_stb_any = extif_run ? xmit_stb_seq : xmit_stb_fifo;
assign xmit_over = extif_run ? xmit_over_seq : xmit_over_fifo;
assign xmit_start_out_fifo = xmit_run && !xmit_run_d;
assign xmit_start_out_seq = extif_run && !extif_run_d;
assign xmit_start_out = xmit_start_out_fifo || xmit_start_out_seq;
assign pre_tx_stb = !xmit_stb_d && !xmit_over_d && !mrst && !xmit_rst && !extif_rst && xmit_run && tx_rdy;
assign xmit_busy = xmit_busy_r;
// assign packet_sent = xmit_over && !xmit_over_d;
always @(posedge mclk) begin
xmit_busy_r <= uart_tx_busy || stuffer_busy_d || xmit_pend || xmit_run || extif_run;
if (mrst || xmit_rst) xmit_pend <= 0;
else if (xmit_start) xmit_pend <= 1;
else if (xmit_start_out_fifo) xmit_pend <= 0;
if (mrst || xmit_rst) xmit_run <= 0;
else if (xmit_pend && !xmit_run && extif_run) xmit_run <= 1;
else if (xmit_done) xmit_run <= 0; // no need to condition with xmit_run
// else if (!stuffer_busy && !xmit_fifo_nempty) xmit_run <= 0; // no need to condition with xmit_run
xmit_run_d <= xmit_run && !mrst && !xmit_rst;
if (mrst || extif_rst) extif_run <= 0;
else if (!xmit_run && !xmit_pend && extif_rq_w) extif_run <= 1;
else if (xmit_done) extif_run <= 0; // no need to condition with xmit_run
extif_run_d <= extif_run && !mrst && !extif_rst;
xmit_stb_d <= xmit_stb_any;
xmit_over_d <= xmit_over;
stuffer_busy_d <= stuffer_busy;
xmit_done <= stuffer_busy_d && !stuffer_busy;
// transmit soft (from fifo) (FIFO should always be not empty until last byte (should nit be replenished)
xmit_stb_fifo <= pre_tx_stb && xmit_fifo_nempty; // also advances FIFO read
xmit_over_fifo <= pre_tx_stb && !xmit_fifo_nempty;
// Generate sequencer packet and transmit it
xmit_stb_seq <= pre_tx_stb && packet_ready_seq;
xmit_over_seq <= pre_tx_stb && packet_over_seq;
end
/* Instance template for module serial_103993_extif */
serial_103993_extif #(
.EXTIF_MODE (EXTIF_MODE) // 1)
) serial_103993_extif_i (
.mclk (mclk), // input
.mrst (mrst), // input
.extif_en (extif_en), // input
.extif_dav (extif_dav), // input
.extif_sel (extif_sel), // input[1:0]
.extif_byte (extif_byte), // input[7:0]
.extif_ready (extif_ready), // output
.extif_rst (extif_rst), // input
.packet_ready (packet_ready_seq), // output
.packet_byte (xmit_extif_data), // output[7:0]
.packet_byte_stb (xmit_stb_seq), // input
.packet_over (packet_over_seq), // output
.packet_sent (xmit_done) // input
);
serial_fslp #(
.START_FRAME_BYTE (START_FRAME_BYTE), // 'h8E),
.END_FRAME_BYTE (END_FRAME_BYTE), // 'hAE),
.ESCAPE_BYTE (ESCAPE_BYTE), // 'h9E),
.REPLACED_START_FRAME_BYTE (REPLACED_START_FRAME_BYTE), // 'h81),
.REPLACED_END_FRAME_BYTE (REPLACED_END_FRAME_BYTE), // 'hA1),
.REPLACED_ESCAPE_BYTE (REPLACED_ESCAPE_BYTE), // 'h91),
.INITIAL_CRC16 (INITIAL_CRC16), // 16'h1d0f),
.CLK_DIV (CLK_DIV), // 217),
.RX_DEBOUNCE (RX_DEBOUNCE) // 60)
) serial_fslp_i (
.mrst (mrst), // input
.mclk (mclk), // input
.txd (txd), // output serial data out
.rxd (rxd), // input serial data in
.tx_start (xmit_start_out), // input start transmit packet
.tx_done (xmit_over), // input end transmit packet
.tx_stb (xmit_stb_any), // input transmit byte strobe
.tx_byte (xmit_any_data), // input[7:0] transmit byte input
.tx_rdy (tx_rdy), // output crc16 ready to accept tx_in_stb
.stuffer_busy (stuffer_busy), // output processing packet (not including UART)
.uart_tx_busy (uart_tx_busy), // output UART busy ('or' with stuffer_busy?)
.rx_byte (recv_fifo_din), // output[7:0] received byte output
.rx_stb (recv_fifo_wr), // output received byte strobe
.rx_packet_run (recv_prgrs), // output run received packet
.rx_packet_done () // output finished receiving packet (last 2 bytes - crc16)
);
fifo_sameclock_control #(
.WIDTH(11)
) fifo_xmit_control_i (
.clk (mclk), // input
.rst (mrst || xmit_rst), // input
.wr (xmit_stb), // input
.rd (xmit_stb_fifo), // input
.nempty (xmit_fifo_nempty), // output
.fill_in (), // output[11:0]
.mem_wa (xmit_fifo_waddr), // output[10:0] reg
.mem_ra (xmit_fifo_raddr), // output[10:0] reg
.mem_re (xmit_fifo_re_regen[0]), // output
.mem_regen(xmit_fifo_re_regen[1]), // output
.over (), // output reg
.under () //h2d_under) // output reg
);
ram18_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (3),
.LOG2WIDTH_RD (3)
) fifo_xmit_i (
.rclk (mclk), // input
.raddr (xmit_fifo_raddr), // input[10:0]
.ren (xmit_fifo_re_regen[0]), // input
.regen (xmit_fifo_re_regen[1]), // input
.data_out (xmit_fifo_out), // output[7:0]
.wclk (mclk), // input
.waddr (xmit_fifo_waddr), // input[10:0]
.we (xmit_stb), // input
.web (4'hf), // input[3:0]
.data_in (xmit_data) // input[7:0]
);
fifo_sameclock_control #(
.WIDTH(11)
) fifo_recv_control_i (
.clk (mclk), // input
.rst (mrst || recv_rst), // input
.wr (recv_fifo_wr), // input
.rd (recv_next), // input
.nempty (recv_dav), // output
.fill_in (), // recv_fifo_fill), // output[11:0]
.mem_wa (recv_fifo_waddr), // output[10:0] reg
.mem_ra (recv_fifo_raddr), // output[10:0] reg
.mem_re (recv_fifo_re_regen[0]), // output
.mem_regen(recv_fifo_re_regen[1]), // output
.over (), // output reg
.under () //h2d_under) // output reg
);
ram18_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (3),
.LOG2WIDTH_RD (3)
) fifo_recv_i (
.rclk (mclk), // input
.raddr (recv_fifo_raddr), // input[10:0]
.ren (recv_fifo_re_regen[0]), // input
.regen (recv_fifo_re_regen[1]), // input
.data_out (recv_data), // output[7:0]
.wclk (mclk), // input
.waddr (recv_fifo_waddr), // input[10:0]
.we (recv_fifo_wr), // input
.web (4'hf), // input[3:0]
.data_in (recv_fifo_din) // input[7:0]
);
endmodule
sensor/serial_103993_extif.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> serial_103993_extif
* @file serial_103993_extif.v
* @date 2020-12-19
* @author eyesis
*
* @brief convert sequencer data to 103993 serial packet data
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* serial_103993_extif.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* serial_103993_extif.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module serial_103993_extif #(
parameter EXTIF_MODE = 1 // 1,2 or 3 if there are several different extif
)(
input mclk,
input mrst,
// sequencer interface
// sequencer always provides 4 payload bytes (5 total)
// interface for uart in write-only mode for short commands
// 1-st byte - SA (use 2 LSB to select 0,1,2 data bytes
// 2-nd byte module
// 3-rd byte function
// 4 (optional) data[15:8] or data[7:0] if last
// 5 (optional) data[7:0]
input extif_en, // enable receiving new packet data
input extif_dav, // data byte available for external interface
// input extif_last, // last byte for external interface (with extif_dav)
input [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
input [7:0] extif_byte, // data to external interface (first - extif_sa)
output extif_ready, // acknowledges extif_dav
input extif_rst, // reset seq xmit and sequence number
output packet_ready,// packet ready, later next packet byte ready
output [7:0] packet_byte,
input packet_byte_stb, // packet byte read out - should be >2(?) cycles apart
// output packet_byte_rdy, // packet byte ready
output packet_over,
input packet_sent
);
reg [3:0] packet_mode; // 1 - zero bytes, 2 - 1 byte, 4 - 2 bytes, 8 - 4 bytes
reg packet_nempty_r; // ~ready to receive packet
// reg packet_ready_r;
reg [2:0] in_bytes;
// reg packet_in; // receiving packet bytes (after mode)
reg extif_ready_r;
reg [7:0] payload_ram [0:3]; // module (1 byte), function (1 byte) , data[15:8], data[7:0]
wire recv_start; // receive first byte - mode
wire recv_next; // receive next byte
wire reset_in_bytes;
reg [17:0] packet_gen_state;
reg inc_ra;
reg [1:0] ra;
reg [7:0] payload_r; // registered payload byte
reg use_mem; // output payload from memory
reg use_ff; // 0xff byte
reg [15:0] seq_num; // 16-bit sequence number
reg [7:0] packet_byte_r;
reg [1:0] packet_byte_stb_d;
assign packet_ready = in_bytes[2] && !packet_byte_stb_d[0] && !packet_byte_stb_d[1]; //
assign recv_start = !packet_nempty_r && extif_en && extif_dav && (extif_sel == EXTIF_MODE) && extif_ready_r;
assign recv_next = packet_nempty_r && extif_dav && !extif_ready_r;
assign reset_in_bytes = mrst || extif_rst || !packet_nempty_r;
assign packet_byte = packet_byte_r;
assign extif_ready = extif_ready_r;
assign packet_over = packet_gen_state[17];
always @(posedge mclk) begin
if (mrst || extif_rst) packet_byte_stb_d <= 0;
else packet_byte_stb_d <= {packet_byte_stb_d[0], packet_byte_stb};
if (mrst || extif_rst || !extif_dav) extif_ready_r <= 0;
else if (recv_start || recv_next) extif_ready_r <= 1;
if (mrst || extif_rst) packet_nempty_r <= 0;
else if (recv_start) packet_nempty_r <= 1;
else if (packet_sent) packet_nempty_r <= 0;
if (recv_start) packet_mode <= {
extif_byte[1] & extif_byte[0], // 3 - 4 bytes
extif_byte[1] & ~extif_byte[0], // 2 - 2 bytes
~extif_byte[1] & extif_byte[0], // 1 - 1 byte
~extif_byte[1] & ~extif_byte[0]};// 0 - 0 bytes
// if (reset_in_bytes) packet_in <= 0;
if (reset_in_bytes) in_bytes <= 0;
else if (recv_next) in_bytes <= in_bytes + 1;
if (recv_next) payload_ram[in_bytes] <= extif_byte;
payload_r <= payload_ram[ra];
// Generating packet
if (!in_bytes[2]) packet_gen_state <= 1;
else if (packet_byte_stb) packet_gen_state <= {
(packet_gen_state[12] & packet_mode[0]) | packet_gen_state[16], // 17
(packet_gen_state[12] & packet_mode[1]) | packet_gen_state[15], // 16
(packet_gen_state[12] & packet_mode[2]) | packet_gen_state[14], // 15
packet_gen_state[13], // 14
packet_gen_state[12] & packet_mode[3], // 13
packet_gen_state[11:0], // 1..12
1'b0}; // 0
inc_ra <= packet_byte_stb & (
packet_gen_state[6] | packet_gen_state[8] | packet_gen_state[15] | ( | packet_gen_state[9] & packet_mode[1]));
if (!in_bytes[2]) ra <= 0;
else if (inc_ra) ra <= ra + 1;
if (mrst || extif_rst) seq_num <= 0;
else if (packet_sent) seq_num <= seq_num + 1;
use_mem <= packet_gen_state[6] | packet_gen_state[8] | packet_gen_state[15] | packet_gen_state[16];
use_ff <= packet_gen_state[9] | packet_gen_state[10] | packet_gen_state[11] | packet_gen_state[12];
packet_byte_r <= (
{8{use_mem}} & payload_r) |
{8{use_ff}} |
({8{packet_gen_state[3]}} & seq_num[15:8]) |
({8{packet_gen_state[4]}} & seq_num[ 7:0]);
end
/*
reg [7:0] payload_r; // registered payload byte
reg use_mem; // output payload from memory
reg use_ff; // 0xff byte
reg [15:0] seq_num; // 16-bit sequence number
reg use_mem;
reg use_ff;
fifo_same_clock #(
.DATA_WIDTH(8),
.DATA_DEPTH(4)
) fifo_same_clock_i2c_rdata_i (
.rst (1'b0), // input
.clk (mclk), // input
.sync_rst (mrst | extif_rst), // input
.we (i2c_rvalid), // input
.re (i2c_fifo_rd), // input
.data_in (i2c_rdata), // input[15:0]
.data_out (i2c_fifo_dout), // output[15:0]
.nempty (i2c_fifo_nempty), // output
.half_full () // output reg
);
*/
endmodule
sensor/serial_destuffer.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> serial_destuffer
* @file serial_destuffer.v
* @date 2020-12-13
* @author eyesis
*
* @brief unwrap serial packet from fslp
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* serial_destuffer.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* serial_destuffer.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module serial_destuffer#(
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
parameter REPLACED_START_FRAME_BYTE = 'h81,
parameter REPLACED_END_FRAME_BYTE = 'hA1,
parameter REPLACED_ESCAPE_BYTE = 'h91
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input [7:0] rxd_in, // data byte from uart
input rx_in_stb, // data strob from uart
output [7:0] rxd_out, // destuffed payload (including channel and CRC, excluding START/END
output rx_stb, // output data strobe
output packet_run, // receiving packet (debug output)
output packet_done // single-cycle packet end indicator
);
reg [1:0] packet_run_r;
reg packet_done_r;
reg payload;
reg [7:0] rxd_in_r;
reg [2:0] in_stb;
reg is_esc;
reg [7:0] rxd_r;
reg [2:0] replaced;
reg thru; // pass input data through
reg [1:0] out_stb;
wire flsp_start;
wire flsp_end;
wire is_esc_w;
wire [2:0] replaced_w;
assign flsp_start = in_stb[0] && (rxd_in_r == START_FRAME_BYTE);
assign flsp_end = in_stb[0] && (rxd_in_r == END_FRAME_BYTE);
assign is_esc_w = rxd_in_r == ESCAPE_BYTE;
assign replaced_w = {
(rxd_in_r == REPLACED_START_FRAME_BYTE) ? 1'b1: 1'b0,
(rxd_in_r == REPLACED_END_FRAME_BYTE) ? 1'b1: 1'b0,
(rxd_in_r == REPLACED_ESCAPE_BYTE) ? 1'b1: 1'b0};
assign packet_run = packet_run_r[0];
assign rxd_out = rxd_r;
assign rx_stb = out_stb[1];
assign packet_done = packet_done_r;
always @(posedge mclk) begin
if (mrst) in_stb <= 0;
else in_stb <= {in_stb[1:0], rx_in_stb};
if (mrst) rxd_in_r <= 0;
else if (rx_in_stb) rxd_in_r <= rxd_in;
if (mrst) packet_run_r[0] <= 0;
else if (flsp_start) packet_run_r[0] <= 1;
else if (flsp_end) packet_run_r[0] <= 0;
packet_run_r[1] <= packet_run_r[0];
if (!packet_run || flsp_end) payload <= 0;
else if (in_stb[0]) payload <= 1;
if (mrst) is_esc <= 0;
else if (in_stb[0]) is_esc <= is_esc_w;
if (mrst) replaced <= 0;
else if (in_stb[0]) replaced <= {3{is_esc}} & replaced_w;
if (in_stb[0]) thru <= !is_esc_w && !is_esc;
if (mrst) out_stb <= 0;
else out_stb <= {out_stb[0], in_stb[1] & payload & ~is_esc};
if (out_stb[0]) rxd_r <=
({8{thru}} & rxd_in_r) |
({8{replaced[0]}} & START_FRAME_BYTE) |
({8{replaced[1]}} & END_FRAME_BYTE) |
({8{replaced[2]}} & ESCAPE_BYTE);
packet_done_r <= !packet_run_r[0] && packet_run_r[1];
end
endmodule
sensor/serial_fslp.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> serial_fslp
* @file serial_fslp.v
* @date 2020-12-13
* @author eyesis
*
* @brief implementation of the FSLP for Boson
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* serial_fslp.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* serial_fslp.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module serial_fslp #(
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
parameter REPLACED_START_FRAME_BYTE = 'h81,
parameter REPLACED_END_FRAME_BYTE = 'hA1,
parameter REPLACED_ESCAPE_BYTE = 'h91,
parameter INITIAL_CRC16 = 16'h1d0f,
// parameter BOSON_BAUD = 921600,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output txd, // serial data out
input rxd, // serial data in
input tx_start, // start transmit packet
input tx_done, // end transmit packet
input tx_stb, // transmit byte strobe
input [7:0] tx_byte, // transmit byte input
output tx_rdy, // crc16 ready to accept tx_in_stb
output stuffer_busy, // processing packet (not including UART)
output uart_tx_busy, // UART busy ('or' with stuffer_busy?)
output [7:0] rx_byte, // received byte output
output rx_stb, // received byte strobe
output rx_packet_run, // run received packet
output rx_packet_done // finished receiving packet (last 2 bytes - crc16)
);
wire [7:0] uart_txd;
wire [7:0] uart_rxd;
wire uart_tx_stb;
wire uart_tx_rdy;
wire stuffer_rdy;
wire uart_rx_stb;
wire [7:0] crc16_txd;
wire crc16_stb;
wire crc16_busy;
boson_uart #(
.CLK_DIV (CLK_DIV),
.RX_DEBOUNCE (RX_DEBOUNCE)
) boson_uart_i (
.mrst (mrst), // input
.mclk (mclk), // input
.txd (txd), // output
.rxd (rxd), // input
.tx_byte (uart_txd[7:0]), // input[7:0]
.tx_stb (uart_tx_stb), // input
.tx_busy (uart_tx_busy), // output
.tx_rdy (uart_tx_rdy), // output
.rx_byte (uart_rxd[7:0]), // output[7:0]
.rx_stb (uart_rx_stb) // output
);
crc16_xmodem #(
.INITIAL_CRC16(INITIAL_CRC16)
) crc16_xmodem_i (
.mrst (mrst), // input
.mclk (mclk), // input
.tx_start (tx_start), // input
.txd_in (tx_byte[7:0]), // input[7:0]
.tx_in_stb (tx_stb), // input
.tx_over (tx_done), // input
.tx_rdy (stuffer_rdy), // input
.tx_in_rdy (tx_rdy), // output
.txd_out (crc16_txd[7:0]), // output[7:0]
.tx_out_stb (crc16_stb), // output
.tx_busy (crc16_busy) // output
);
serial_stuffer #(
.START_FRAME_BYTE (START_FRAME_BYTE),
.END_FRAME_BYTE (END_FRAME_BYTE),
.ESCAPE_BYTE (ESCAPE_BYTE),
.REPLACED_START_FRAME_BYTE (REPLACED_START_FRAME_BYTE),
.REPLACED_END_FRAME_BYTE (REPLACED_END_FRAME_BYTE),
.REPLACED_ESCAPE_BYTE (REPLACED_ESCAPE_BYTE)
) serial_stuffer_i (
.mrst (mrst), // input
.mclk (mclk), // input
.packet_run (crc16_busy), // input
.tx_in_stb (crc16_stb), // input
.txd_in (crc16_txd[7:0]), // input[7:0]
.stuffer_rdy (stuffer_rdy), // output
.uart_rdy (uart_tx_rdy), // input
.uart_stb (uart_tx_stb), // output
.uart_txd (uart_txd[7:0]), // output[7:0]
.stuffer_busy (stuffer_busy) // output
);
serial_destuffer #(
.START_FRAME_BYTE (START_FRAME_BYTE),
.END_FRAME_BYTE (END_FRAME_BYTE),
.ESCAPE_BYTE (ESCAPE_BYTE),
.REPLACED_START_FRAME_BYTE (REPLACED_START_FRAME_BYTE),
.REPLACED_END_FRAME_BYTE (REPLACED_END_FRAME_BYTE),
.REPLACED_ESCAPE_BYTE (REPLACED_ESCAPE_BYTE)
) serial_destuffer_i (
.mrst (mrst), // input
.mclk (mclk), // input
.rxd_in (uart_rxd[7:0]), // input[7:0]
.rx_in_stb (uart_rx_stb), // input
.rxd_out (rx_byte[7:0]), // output[7:0]
.rx_stb (rx_stb), // output
.packet_run (rx_packet_run), // output
.packet_done (rx_packet_done) // output
);
endmodule
sensor/serial_stuffer.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> serial_stuffer
* @file serial_stuffer.v
* @date 2020-12-13
* @author eyesis
*
* @brief wrap serial packet for fslp
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* serial_stuffer.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* serial_stuffer.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module serial_stuffer #(
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
parameter REPLACED_START_FRAME_BYTE = 'h81,
parameter REPLACED_END_FRAME_BYTE = 'hA1,
parameter REPLACED_ESCAPE_BYTE = 'h91
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input packet_run, // goes inactive after last txd_in_stb
input tx_in_stb,
input [7:0] txd_in,
output stuffer_rdy, // stuffer ready to accept tx_in_stb
input uart_rdy, // uart ready to accept byte
output uart_stb, // write byte to UART
output [7:0] uart_txd, // byte to uart
output stuffer_busy // processing packet (not including UART)
);
reg stuffer_busy_r;
reg [1:0] stuffer_start;
reg stuffer_finsh;
reg packet_trailer;
reg packet_header;
reg escape_cyc0;
reg [2:0] escape_cyc1;
reg uart_stb_r;
reg [7:0] txd_in_r;
reg [2:0] tx_in_stb_r;
reg [2:0] need_escape;
reg [1:0] byte_out_set; //
reg [7:0] uart_txd_r;
reg tx_dav;
reg copy_in_byte;
reg stuffer_rdy_r;
assign stuffer_busy = stuffer_busy_r;
assign uart_stb = uart_stb_r;
assign uart_txd = uart_txd_r;
assign stuffer_rdy = stuffer_rdy_r;
always @(posedge mclk) begin
stuffer_start <= {stuffer_start[0], ~stuffer_busy_r & packet_run};
if (mrst) stuffer_busy_r <= 0;
else if (stuffer_start[0]) stuffer_busy_r <= 1;
else if (packet_trailer && uart_stb_r) stuffer_busy_r <= 0;
if (mrst) stuffer_rdy_r <= 0;
else if (stuffer_start || tx_in_stb || stuffer_finsh) stuffer_rdy_r <= 0;
else if (byte_out_set[1] && (!escape_cyc0)) stuffer_rdy_r <= 1;
tx_in_stb_r <= {tx_in_stb_r[1:0],tx_in_stb};
if (tx_in_stb) txd_in_r <= txd_in;
if (tx_in_stb_r[0]) need_escape <= {
(txd_in_r == START_FRAME_BYTE)? 1'b1 : 1'b0,
(txd_in_r == END_FRAME_BYTE)? 1'b1 : 1'b0,
(txd_in_r == ESCAPE_BYTE)? 1'b1 : 1'b0};
if (mrst) escape_cyc0 <= 0;
else if (tx_in_stb_r[1]) escape_cyc0 <= |need_escape;
else if (uart_stb_r) escape_cyc0 <= 0;
if (mrst) escape_cyc1 <= 0;
else if (uart_stb_r) escape_cyc1 <= {3{escape_cyc0}} & need_escape;
if (mrst) byte_out_set <= 0;
else byte_out_set <= {byte_out_set[0], tx_in_stb_r[2] | stuffer_start[1] | stuffer_finsh};
if (mrst) packet_header <= 0;
else if (stuffer_start[1]) packet_header <= 1;
else if (byte_out_set[1]) packet_header <= 0;
if (!stuffer_busy_r) packet_trailer <= 0;
else if (!packet_run) packet_trailer <= 1;
stuffer_finsh <= stuffer_rdy_r && stuffer_busy_r && packet_trailer; // !packet_run
copy_in_byte <= !need_escape && !packet_header && !packet_trailer;
if (byte_out_set[1]) uart_txd_r <=
({8{packet_header}} & START_FRAME_BYTE) |
({8{packet_trailer}} & END_FRAME_BYTE) |
({8{escape_cyc0}} & ESCAPE_BYTE) |
({8{escape_cyc1[0]}} & REPLACED_START_FRAME_BYTE) |
({8{escape_cyc1[1]}} & REPLACED_END_FRAME_BYTE) |
({8{escape_cyc1[2]}} & REPLACED_ESCAPE_BYTE) |
({8{copy_in_byte}} & txd_in_r);
if (mrst) tx_dav <= 0;
else if (byte_out_set[1]) tx_dav <= 1;
else if (uart_stb_r) tx_dav <= 0;
if (mrst) uart_stb_r <= 0;
else uart_stb_r <= !uart_stb_r && tx_dav && uart_rdy;
end
endmodule
simulation_modules/simul_103993_serializer.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> simul_103993_serializer
* @file simul_103993_serializer.v
* @date 2020-12-23
* @author eyesis
*
* @brief Serializer for Boson640 output based on SN65LVDS301
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* simul_103993_serializer.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_103993_serializer.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module simul_103993_serializer#(
parameter PCLK_FREQ_MHZ = 27.0
)(
input [7:0] red,
input [7:0] green,
input [7:0] blue,
input hs,
input vs,
input de,
input pclk,
output [2:0] dp,
output [2:0] dn,
output clkp,
output clkn
);
localparam PERIOD = 1000.0/PCLK_FREQ_MHZ;
wire [9:0] dclocks;
assign #(PERIOD/20) dclocks[9:0] = ~{dclocks[8:0], pclk};
/*
assign #(PERIOD/20) dclocks[0] = pclk;
assign #(PERIOD/20) dclocks[1] = dclocks[0];
assign #(PERIOD/20) dclocks[2] = dclocks[1];
assign #(PERIOD/20) dclocks[3] = dclocks[2];
assign #(PERIOD/20) dclocks[4] = dclocks[3];
assign #(PERIOD/20) dclocks[5] = dclocks[4];
assign #(PERIOD/20) dclocks[6] = dclocks[5];
assign #(PERIOD/20) dclocks[7] = dclocks[6];
assign #(PERIOD/20) dclocks[8] = dclocks[7];
assign #(PERIOD/20) dclocks[9] = dclocks[8];
*/
wire clk10 = ^dclocks[9:0];
reg [9:0] r_red;
reg [9:0] r_green;
reg [9:0] r_blue;
reg [9:0] sr_red;
reg [9:0] sr_green;
reg [9:0] sr_blue;
reg [9:0] sr_clk;
reg [1:0] clk_r;
reg set_sr;
wire cp = (^red) ^ (^green) ^ (^blue) ^ vs ^ hs ^ de;
assign dp = {sr_blue[9],sr_green[9], sr_red[9]};
assign dn = ~{sr_blue[9],sr_green[9], sr_red[9]};
assign clkp = sr_clk [9];
assign clkn = ~sr_clk [9];
always @ (posedge pclk) begin
r_red <= {red, vs, cp};
r_green <= {green, hs, 1'b0};
r_blue <= {blue, de, 1'b0};
end
always @ (posedge clk10) begin
clk_r <= {clk_r[0], pclk};
set_sr <= clk_r[0] && !clk_r[0];
if (set_sr) begin
sr_red <= r_red;
sr_green <= r_green;
sr_blue <= r_blue;
sr_clk <= 10'b1111100000;
end else begin
sr_red <= {sr_red[8:0], 1'b0};
sr_green <= {sr_green[8:0], 1'b0};
sr_blue <= {sr_blue[8:0], 1'b0};
sr_clk <= {sr_clk[8:0], 1'b0};
end
end
endmodule
simulation_modules/simul_boson640.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> simul_boson640
* @file simul_boson640.v
* @date 2020-12-23
* @author eyesis
*
* @brief Simulating Boson640
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* simul_boson640.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_boson640.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module simul_boson640#(
parameter DATA_FILE = "/input_data/pattern_160_120_16.dat", //
parameter WIDTH = 640, // overwrite with 160
parameter HEIGHT = 513, // overwrite with 120
parameter OUT_BITS = 16,
parameter FPS = 60.0, // actual fps of the internal generator
parameter HSW = 8, // horizontal sync width
parameter FP_BP = 102,
parameter FP = 52, // FP_BP = 52+50
parameter VSW = 87 // with telemetry, in eows
)(
input mrst,
input single,
input ext_sync,
output [15:0] pxd,
output pclk,
output dvalid,
output vsync,
output hsync,
input uart_in,
output uart_out // will just copy when not reset;
);
`ifndef ROOTPATH
`include "IVERILOG_INCLUDE.v"// SuppressThisWarning VEditor - maybe not used
`ifndef ROOTPATH
`define ROOTPATH "."
`endif
`endif
localparam CLK_PER_FRAME = 450000;
localparam CLK_PERIOD = 1000000000.0/ (FPS * CLK_PER_FRAME); // ns
localparam BP = FP_BP - FP;
reg [OUT_BITS-1:0] sensor_data[0 : WIDTH * HEIGHT - 1]; // SuppressThisWarning VEditor - Will be assigned by $readmem
reg [OUT_BITS-1:0] pxd_r;
reg pclk_r = 0;
reg [1:0] frame_state; // 00 - reset, 01 vsync, 10 - out lines
// reg [1:0] frame_state_d; // previous state
reg [3:0] line_state;
reg ext_sync_d;
integer pix_cntr;
integer line_cntr;
integer frame_pixel;
wire last_in_line;
wire start_frame;
wire start_line;
wire last_line;
wire pre_dav;
reg dvalid_r;
localparam FSTATE_IDLE = 2'b00;
localparam FSTATE_VSYNC = 2'b01;
localparam FSTATE_OUT = 2'b10;
localparam LSTATE_IDLE = 4'b0000;
localparam LSTATE_HS = 4'b0001;
localparam LSTATE_FP = 4'b0010;
localparam LSTATE_OUT = 4'b0100;
localparam LSTATE_BP = 4'b1000;
assign pclk = ~pclk_r;
assign uart_out = uart_in && !mrst;
assign last_line = (frame_state == FSTATE_OUT) && (line_cntr == 0);
assign last_in_line = (line_state == LSTATE_BP) && (pix_cntr == 0);
assign start_frame = ((frame_state == FSTATE_IDLE) || (last_line && last_in_line)) && (!single | (ext_sync && !ext_sync_d));
assign start_line = start_frame || ((frame_state != FSTATE_IDLE) && !last_line && last_in_line);
assign pre_dav = (frame_state == FSTATE_OUT) && ((pix_cntr == 0)? (line_state == LSTATE_FP) : (line_state == LSTATE_OUT));
assign dvalid = dvalid_r;
assign pxd = pxd_r;
assign vsync = frame_state != FSTATE_VSYNC; // active low
assign hsync = line_state != LSTATE_HS; // active low
initial begin
$readmemh({`ROOTPATH,DATA_FILE},sensor_data);
end
always #(CLK_PERIOD/2) pclk_r <= mrst ? 1'b0: ~pclk_r;
always @ (posedge pclk_r) begin
dvalid_r <= pre_dav && !mrst;
if (mrst) ext_sync_d <= 0;
else ext_sync_d <= ext_sync;
// frame_state_d <=frame_state;
if (mrst) begin
frame_state <= FSTATE_IDLE;
end else begin
case (frame_state)
FSTATE_IDLE: begin
if (!single | (ext_sync && !ext_sync_d)) begin
frame_state <= FSTATE_VSYNC;
line_cntr <= VSW - 1;
end
end
FSTATE_VSYNC: if (last_in_line) begin
if (line_cntr == 0) begin
frame_state <= FSTATE_OUT;
line_cntr <= HEIGHT - 1;
end else begin
line_cntr <= line_cntr - 1;
end
end
FSTATE_OUT: if (last_in_line) begin
if (line_cntr == 0) begin
frame_state <= (!single | (ext_sync && !ext_sync_d)) ? FSTATE_VSYNC : FSTATE_IDLE;
line_cntr <= VSW - 1;
end else begin
line_cntr <= line_cntr - 1;
end
end
default: frame_state <= FSTATE_IDLE;
endcase
end
if (mrst) begin
line_state <= 0;
pix_cntr <= HSW - 1;
end else if (start_line) begin
line_state <= LSTATE_HS;
pix_cntr <= HSW - 1;
end else begin
case (line_state)
LSTATE_HS: begin
if (pix_cntr == 0) begin
line_state <= LSTATE_FP;
pix_cntr <= FP - 1;
end else begin
pix_cntr <= pix_cntr -1;
end
end
LSTATE_FP: begin
if (pix_cntr == 0) begin
line_state <= LSTATE_OUT;
pix_cntr <= WIDTH - 1;
end else begin
pix_cntr <= pix_cntr -1;
end
end
LSTATE_OUT: begin
if (pix_cntr == 0) begin
line_state <= LSTATE_BP;
pix_cntr <= BP - 1;
end else begin
pix_cntr <= pix_cntr -1;
end
end
LSTATE_BP: begin
if (pix_cntr == 0) begin
line_state <= LSTATE_IDLE;
end else begin
pix_cntr <= pix_cntr -1;
end
end
default: line_state <= LSTATE_IDLE;
endcase
end
if (start_frame) frame_pixel <= 0;
else if (pre_dav) frame_pixel <= frame_pixel + 1;
if (pre_dav) pxd_r <= sensor_data[frame_pixel];
end
endmodule
system_defines.vh
View file @ 043d4849
......@@ -64,8 +64,23 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define LWIR /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/
`define BOSON 1 /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/
// `define LWIR /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
`ifdef BOSON
`elsif LWIR
`elsif HISPI
`else
`define PAR12 // use default sensors interface
`endif
`ifdef BOSON
`define PCLK_MASTER /* pclk is generated by the sensors, no global pclk and prst!*/
`endif
`define MON_HISPI // Measure HISPI timing
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
......
util_modules/fifo_sameclock_control.v
View file @ 043d4849
......@@ -4,7 +4,7 @@
* @date 2016-01-20
* @author Andrey Filippov
*
* @brief BRAM-based fifo control, uses BARM output registers
* @brief BRAM-based fifo control, uses BRAM output registers
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
......
util_modules/status_read.v
View file @ 043d4849
......@@ -104,7 +104,8 @@ module status_read#(
ram [DATA_2DEPTH-1] = 1; //0 - parallel sensor, 1 - HiSPi sensor, 2 - LWIR 160x120 sensor
`elsif LWIR
ram [DATA_2DEPTH-1] = 2; //0 - parallel sensor, 1 - HiSPi sensor, 2 - LWIR 160x120 sensor
`elsif BOSON
ram [DATA_2DEPTH-1] = 3; //0 - parallel sensor, 1 - HiSPi sensor, 2 - LWIR 160x120 sensor 3- BOSON 640x512
`endif
end
always @ (posedge axi_clk) begin
......
x393.v
View file @ 043d4849
......@@ -87,6 +87,51 @@ module x393 #(
inout sns4_sda,
inout sns4_ctl,
inout sns4_pg,
`elsif BOSON
input [3:0] sns1_dp,
input [3:0] sns1_dn,
inout [7:4] sns1_dp74, // other non-diff signals
inout [7:4] sns1_dn74, // other non-diff signals
input sns1_clkp,
input sns1_clkn,
inout sns1_scl,
inout sns1_sda,
inout sns1_ctl,
inout sns1_pg,
input [3:0] sns2_dp,
input [3:0] sns2_dn,
inout [7:4] sns2_dp74, // other non-diff signals
inout [7:4] sns2_dn74, // other non-diff signals
input sns2_clkp,
input sns2_clkn,
inout sns2_scl,
inout sns2_sda,
inout sns2_ctl,
inout sns2_pg,
input [3:0] sns3_dp,
input [3:0] sns3_dn,
inout [7:4] sns3_dp74, // other non-diff signals
inout [7:4] sns3_dn74, // other non-diff signals
input sns3_clkp,
input sns3_clkn,
inout sns3_scl,
inout sns3_sda,
inout sns3_ctl,
inout sns3_pg,
input [3:0] sns4_dp,
input [3:0] sns4_dn,
inout [7:4] sns4_dp74, // other non-diff signals
inout [7:4] sns4_dn74, // other non-diff signals
input sns4_clkp,
input sns4_clkn,
inout sns4_scl,
inout sns4_sda,
inout sns4_ctl,
inout sns4_pg,
`elsif LWIR
inout [4:0] sns1_dp40,
inout [4:0] sns1_dn40,
......@@ -314,8 +359,16 @@ module x393 #(
// sensor pixel rate clock likely to originate from the external clock
//TODO: Create missing clocks
`ifdef PCLK_MASTER
wire [3:0] pclk; // global clock, sensor pixel rate (96 MHz)
wire [3:0] prst; // @ posedge pclk
wire [3:0] locked_pclk; // display all/any?
`else
wire pclk; // global clock, sensor pixel rate (96 MHz)
wire prst; // @ posedge pclk
wire locked_pclk;
`endif
`ifdef USE_PCLK2X
wire pclk2x; // global clock, sensor double pixel rate (192 MHz)
`endif
......@@ -330,7 +383,7 @@ module x393 #(
assign logger_clk = camsync_clk;
wire mrst; // @ posedge mclk
wire prst; // @ posedge pclk
// wire prst; // @ posedge pclk
wire xrst; // @ posedge xclk
wire crst; // @ posedge camsync_clk
wire lrst; // @ posedge logger_clk;
......@@ -339,7 +392,7 @@ module x393 #(
wire locked_sync_clk;
wire locked_xclk;
wire locked_pclk;
// wire locked_pclk;
wire locked_hclk;
wire idelay_ctrl_reset; // to reset idelay_cntrl
......@@ -614,8 +667,9 @@ module x393 #(
// Timestamp messages (@mclk) - combine to a single ts_data?
wire ts_pre_logger_stb; // input logger timestamp sync (@logger_clk)
wire [7:0] ts_logegr_data; // input[7:0] loger timestamp data (@logger_clk)
`ifdef LWIR
wire khz; // 1 KHz 50% duty
`endif
// Compressor signals for interrupts generation
wire [3:0] eof_written_mclk; // output // SuppressThisWarning VEditor - (yet) unused
wire [3:0] stuffer_done_mclk; // output// SuppressThisWarning VEditor - (yet) unused
......@@ -1702,8 +1756,9 @@ assign axi_grst = axi_rst_pre;
wire [ 1:0] saxi1_bresp;
sensors393 #(
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
.SENSOR_BASE_INC (SENSOR_BASE_INC),
// moving to the end to be always present
// .SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
// .SENSOR_BASE_INC (SENSOR_BASE_INC),
.HIST_SAXI_ADDR_REL (HIST_SAXI_ADDR_REL),
.HIST_SAXI_MODE_ADDR_REL (HIST_SAXI_MODE_ADDR_REL),
.SENSI2C_STATUS_REG_BASE (SENSI2C_STATUS_REG_BASE),
......@@ -1793,11 +1848,15 @@ assign axi_grst = axi_rst_pre;
`else
.SENSIO_CTRL (SENSIO_CTRL),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
`ifndef BOSON
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
`endif
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`ifdef HISPI
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
`elsif BOSON
//??
`else
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
`endif
......@@ -1805,6 +1864,16 @@ assign axi_grst = axi_rst_pre;
`ifdef HISPI
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
`elsif BOSON
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
`else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD),
......@@ -1812,13 +1881,17 @@ assign axi_grst = axi_rst_pre;
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
`endif
.SENSIO_STATUS (SENSIO_STATUS),
`ifndef BOSON
.SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
`ifndef HISPI
`endif
`ifdef HISPI
`elsif BOSON
`else
.SENSIO_WIDTH (SENSIO_WIDTH),
`endif
.SENSIO_DELAYS (SENSIO_DELAYS),
......@@ -1839,6 +1912,7 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW),
`ifdef HISPI
`elsif BOSON
`elsif LWIR
.VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
......@@ -1886,12 +1960,10 @@ assign axi_grst = axi_rst_pre;
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap)
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS), // 185
`else
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
`endif
.HIST_SAXI_ADDR_MASK (HIST_SAXI_ADDR_MASK),
.HIST_SAXI_MODE_WIDTH (HIST_SAXI_MODE_WIDTH),
......@@ -1905,30 +1977,27 @@ assign axi_grst = axi_rst_pre;
.SENS_SYNC_LBITS (SENS_SYNC_LBITS),
.SENS_SYNC_LATE_DFLT (SENS_SYNC_LATE_DFLT),
.SENS_SYNC_MINBITS (SENS_SYNC_MINBITS),
.SENS_SYNC_MINPER (SENS_SYNC_MINPER)
// start with comma
.SENS_SYNC_MINPER (SENS_SYNC_MINPER),
`ifdef LWIR
`else
,.IDELAY_VALUE (IDELAY_VALUE),
.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
`endif
// start with comma
`ifdef HISPI
,.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS)
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`endif
// start with comma
`ifdef LWIR
`else
,.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
......@@ -1949,12 +2018,10 @@ assign axi_grst = axi_rst_pre;
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
`endif
`ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK0 (HISPI_DELAY_CLK0),
.HISPI_DELAY_CLK1 (HISPI_DELAY_CLK1),
......@@ -1975,21 +2042,28 @@ assign axi_grst = axi_rst_pre;
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
.HISPI_IOSTANDARD (HISPI_IOSTANDARD),
`endif
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY),
`endif
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
.SENSOR_BASE_INC (SENSOR_BASE_INC)
) sensors393_i (
// .rst (axi_rst), // input
.pclk (pclk), // input
`ifdef PCLK_MASTER
.pclk (pclk), // output [3:0]
.locked_pclk (locked_pclk), // output [3:0]
`else
.pclk (pclk), // input / output [3:0]
`endif
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // input
`endif
.ref_clk (ref_clk), // input
.dly_rst (idelay_ctrl_reset), // input
.mrst (mrst), // input
.prst (prst), // input
.prst (prst), // input / input [3:0]
.arst (arst), // input
.mclk (mclk), // input
......@@ -2003,6 +2077,11 @@ assign axi_grst = axi_rst_pre;
.sns_dn ({sns4_dn, sns3_dn, sns2_dn, sns1_dn}), // input[3:0]
.sns_dp74 ({sns4_dp74, sns3_dp74, sns2_dp74, sns1_dp74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug
.sns_dn74 ({sns4_dn74, sns3_dn74, sns2_dn74, sns1_dn74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug
`elsif BOSON
.sns_dp ({sns4_dp, sns3_dp, sns2_dp, sns1_dp}), // input[3:0]
.sns_dn ({sns4_dn, sns3_dn, sns2_dn, sns1_dn}), // input[3:0]
.sns_dp74 ({sns4_dp74, sns3_dp74, sns2_dp74, sns1_dp74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug
.sns_dn74 ({sns4_dn74, sns3_dn74, sns2_dn74, sns1_dn74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug
`elsif LWIR
.sns_dp40 ({sns4_dp40, sns3_dp40, sns2_dp40, sns1_dp40}), // input[19:0]
.sns_dn40 ({sns4_dn40, sns3_dn40, sns2_dn40, sns1_dn40}), // input[19:0]
......@@ -2069,8 +2148,10 @@ assign axi_grst = axi_rst_pre;
`ifdef DEBUG_SENS_MEM_PAGES
,.dbg_rpage (dbg_rpage[7:0]) // output[7:0]
,.dbg_wpage (dbg_wpage[7:0]) // output[7:0]
`endif
`endif
`ifdef LWIR
,.khz (khz) // input 1 KHz 50% duty
`endif
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input
......@@ -2432,7 +2513,11 @@ assign axi_grst = axi_rst_pre;
.ts_logger_snap (logger_snap), // input
.ts_logger_stb (ts_pre_logger_stb), // output
.ts_logger_data (ts_logegr_data), // output[7:0]
`ifdef LWIR
.khz (khz) // output // 1 KHz 50% output
`else
.khz () // output // 1 KHz 50% output
`endif
);
event_logger #(
......@@ -2654,7 +2739,11 @@ assign axi_grst = axi_rst_pre;
.ffclk1n_pad (ffclk1n), // input
.aclk (axi_aclk), // output
.hclk (hclk), // output
`ifdef PCLK_MASTER
.pclk (), // output // generated by each sensor
`else
.pclk (pclk), // output
`endif
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // output
`endif
......@@ -2668,17 +2757,25 @@ assign axi_grst = axi_rst_pre;
.extra_status ({1'b0,idelay_ctrl_rdy}), // input[1:0]
.locked_sync_clk (locked_sync_clk), // output // always 1
.locked_xclk (locked_xclk), // output // always 1
`ifdef PCLK_MASTER
.locked_pclk (), // output
`else
.locked_pclk (locked_pclk), // output
`endif
.locked_hclk (locked_hclk) // output
);
sync_resets #(
.WIDTH(7),
`ifdef PCLK_MASTER
.WIDTH(10), // pclk[3:0], prst[3:0], locked_pclk[3:0]
`else
.WIDTH(7), // pclk, prst, locked_pclk
`endif
.REGISTER(4)
) sync_resets_i (
.arst (axi_rst_pre), // input
.locked ({locked_hclk, 1'b1, locked_sync_clk, locked_sync_clk, locked_xclk, locked_pclk, mcntrl_locked}), // input
.clk ({hclk, axi_aclk, logger_clk, camsync_clk, xclk, pclk, mclk}), // input[6:0]
.rst ({hrst, arst, lrst, crst, xrst, prst, mrst}) // output[6:0]
.rst ({hrst, arst, lrst, crst, xrst, prst, mrst}) // output[6:0]
);
// Changed aclk to master (it is the source of most orthers)
......
x393_global.tcl
View file @ 043d4849
......@@ -52,11 +52,23 @@ while { [gets $infile line] >= 0 } {
}
}
set BOSON 0
seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
set BOSON 1
break
}
}
close $infile
if { $LWIR} {
puts "x393_global.tcl: using LWIR sensors"
} elseif { $HISPI} {
puts "x393_global.tcl: using HISPI sensors"
} elseif { $BOSON} {
puts "x393_placement.tcl: using Boson640 sensors"
} else {
puts "x393_global.tcl: using parallel sensors"
}
......
x393_placement.tcl
View file @ 043d4849
......@@ -51,11 +51,23 @@ while { [gets $infile line] >= 0 } {
}
}
set BOSON 0
seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
set BOSON 1
break
}
}
close $infile
if { $LWIR} {
puts "x393_placement.tcl: using LWIR sensors"
} elseif { $HISPI} {
puts "x393_placement.tcl: using HISPI sensors"
} elseif { $BOSON} {
puts "x393_placement.tcl: using Boson640 sensors"
} else {
puts "x393_placement.tcl: using parallel sensors"
}
......@@ -139,7 +151,25 @@ set_property PACKAGE_PIN W13 [get_ports {ffclk1n}]
# ================= Sensor port 0 =================
if { $LWIR } {
# BOSON same as HISPI
if { $BOSON } {
set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
set_property PACKAGE_PIN AB9 [get_ports {sns1_dp74[4]}]
set_property PACKAGE_PIN AB8 [get_ports {sns1_dn74[4]}]
set_property PACKAGE_PIN AB13 [get_ports {sns1_dp74[5]}]
set_property PACKAGE_PIN AB12 [get_ports {sns1_dn74[5]}]
set_property PACKAGE_PIN AA12 [get_ports {sns1_dp74[6]}]
set_property PACKAGE_PIN AA11 [get_ports {sns1_dn74[6]}]
set_property PACKAGE_PIN W11 [get_ports {sns1_dp74[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN T10 [get_ports {sns1_dp40[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn40[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp40[1]}]
......@@ -200,7 +230,25 @@ set_property PACKAGE_PIN U8 [get_ports {sns1_pg}]
# ================= Sensor port 1 =================
if { $LWIR } {
# BOSON same as HISPI
if { $BOSON } {
set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
set_property PACKAGE_PIN AA17 [get_ports {sns2_dp74[4]}]
set_property PACKAGE_PIN AB17 [get_ports {sns2_dn74[4]}]
set_property PACKAGE_PIN AA15 [get_ports {sns2_dp74[5]}]
set_property PACKAGE_PIN AB15 [get_ports {sns2_dn74[5]}]
set_property PACKAGE_PIN AA14 [get_ports {sns2_dp74[6]}]
set_property PACKAGE_PIN AB14 [get_ports {sns2_dn74[6]}]
set_property PACKAGE_PIN Y14 [get_ports {sns2_dp74[7]}]
set_property PACKAGE_PIN Y13 [get_ports {sns2_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN U15 [get_ports {sns2_dp40[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn40[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp40[1]}]
......@@ -260,7 +308,25 @@ set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}]
set_property PACKAGE_PIN W16 [get_ports {sns2_pg}]
# ================= Sensor port 2 =================
if { $LWIR } {
# BOSON same as HISPI
if { $BOSON } {
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
set_property PACKAGE_PIN N21 [get_ports {sns3_dp74[4]}]
set_property PACKAGE_PIN N22 [get_ports {sns3_dn74[4]}]
set_property PACKAGE_PIN R22 [get_ports {sns3_dp74[5]}]
set_property PACKAGE_PIN T22 [get_ports {sns3_dn74[5]}]
set_property PACKAGE_PIN P21 [get_ports {sns3_dp74[6]}]
set_property PACKAGE_PIN R21 [get_ports {sns3_dn74[6]}]
set_property PACKAGE_PIN T20 [get_ports {sns3_dp74[7]}]
set_property PACKAGE_PIN U20 [get_ports {sns3_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp40[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn40[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp40[1]}]
......@@ -320,7 +386,24 @@ set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}]
set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}]
# ================= Sensor port 3 =================
if { $LWIR } {
if { $BOSON } {
set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
set_property PACKAGE_PIN P18 [get_ports {sns4_dp74[4]}]
set_property PACKAGE_PIN P19 [get_ports {sns4_dn74[4]}]
set_property PACKAGE_PIN N17 [get_ports {sns4_dp74[5]}]
set_property PACKAGE_PIN N18 [get_ports {sns4_dn74[5]}]
set_property PACKAGE_PIN N20 [get_ports {sns4_dp74[6]}]
set_property PACKAGE_PIN P20 [get_ports {sns4_dn74[6]}]
set_property PACKAGE_PIN R17 [get_ports {sns4_dp74[7]}]
set_property PACKAGE_PIN R18 [get_ports {sns4_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN V17 [get_ports {sns4_dp40[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn40[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp40[1]}]
......
x393_timing.tcl
View file @ 043d4849
......@@ -51,11 +51,23 @@ while { [gets $infile line] >= 0 } {
}
}
set BOSON 0
seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
set BOSON 1
break
}
}
close $infile
if { $LWIR} {
puts "x393_timing.tcl: using LWIR sensors"
} elseif { $HISPI} {
puts "x393_timing.tcl: using HISPI sensors"
} elseif { $BOSON} {
puts "x393_placement.tcl: using Boson640 sensors"
} else {
puts "x393_timing.tcl: using parallel sensors"
}
......@@ -77,7 +89,9 @@ create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
if { $LWIR} {
if { $BOSON} {
# Nothing here yet
} elseif { $LWIR} {
# Nothing here yet
} elseif {$HISPI} {
#WARNING: [Vivado 12-4777] Setting CLOCK_DEDICATED_ROUTE constraint on the PARENT net instead of the specified net segment (net name: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in). Placer only honors CLOCK_DEDICATED_ROUTE when set on the PARENT net, e.g. net segment directly connected to the driver. To eliminate this message, please update your constraint to specify the PARENT net instead. [/home/xilinx/vdt/x393/x393_timing.tcl:68]
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment