Commits · a5ab1c8b9f2ce4b5dc38b8be6614f61e9391cc2d · Elphel / eddr3

11 Jun, 2014 1 commit
- debugging hardware · 5450474d
  Andrey Filippov authored 10 years ago
  
  5450474d
01 Jun, 2014 2 commits
- bug fixes, implemented read pattern test, so all major DDR3 modes are tested:... · 01028931
  Andrey Filippov authored 10 years ago
```
bug fixes, implemented read pattern test, so all major DDR3 modes are tested: write and read leveling, write and read
```
  01028931
- added configuration for ISE, timing constraints for Vivado · 46cf253d
  Andrey Filippov authored 10 years ago
  
  46cf253d
22 May, 2014 1 commit
- added modules, simulating · c8904b67
  Andrey Filippov authored 10 years ago
  
  c8904b67
20 May, 2014 1 commit
- added modules to test ddrc phy over axi read/write · 5034058e
  Andrey Filippov authored 10 years ago
  
  5034058e
19 May, 2014 1 commit
- addint top level module to test pasrt of ddr controller · 03bce211
  Andrey Filippov authored 10 years ago
  
  03bce211
18 May, 2014 1 commit
- axi interface files added · f57364b8
  Andrey Filippov authored 10 years ago
  
  f57364b8