added configuration for ISE, timing constraints for Vivado (46cf253d) · Commits · Elphel / eddr3

.gitignore

+2 −0

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		@@ -3,3 +3,5 @@ glbl.v
		vivado_*
		syntax_*
		simulation/*
		ise_*

.project

+25 −15

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		@@ -43,80 +43,90 @@
		<nature>com.elphel.vdt.veditor.HdlNature</nature>
		</natures>
		<linkedResources>
		<link>
		<name>ise_logs/ISExst.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/ise_logs/ISExst-20140531140025056.log</location>
		</link>
		<link>
		<name>ise_state/eddr3-synth.tgz</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/ise_state/eddr3-synth-20140531140025056.tgz</location>
		</link>
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140531004107237.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140531175841733.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140531003924649.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140531175841733.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140531004107237.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140531175841733.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140531003924649.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140531175841733.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140531003924649.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140531175841733.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140531004107237.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140531175841733.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140531003924649.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140531175605664.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140531004107237.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140531180006073.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140531003924649.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140531175605664.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140531004107237.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140531175841733.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140531003924649.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140531175605664.log</location>
		</link>
		<link>
		<name>vivado_state/eddr3-opt-phys.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140531004107237.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140531175841733.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-place.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140531003924649.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140531175841733.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-route.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140531004107237.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140531175841733.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-synth.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140531003924649.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140531175605664.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

.settings/com.elphel.vdt.ISExst.prefs

0 → 100644

+3 −0

Original line number	Diff line number	Diff line
		ISExst_170_constraints=ddrc_test01.xcf
		com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->
		eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoSynthesis.prefs

+1 −1

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		VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->
		VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->ddrc_test01_timing.xdc<-@\#\#@->
		VivadoSynthesis_95_ShowInfo=false
		com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->
		eclipse.preferences.version=1

axi/axibram_read.v

+4 −4

Original line number	Diff line number	Diff line
		@@ -77,7 +77,7 @@ module axibram_read #(
		reg [ 1:0] rburst; // registered burst type
		reg [ 3:0] rlen; // registered burst type
		wire [ADDRESS_BITS-1:0] next_rd_address_w; // next transfer address;
		assign next_rd_address_w=
		assign next_rd_address_w= //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 13-bit target.
		rburst[1]?
		(rburst[0]? {ADDRESS_BITS{1'b0}}:((read_address[ADDRESS_BITS-1:0]+1) & {{(ADDRESS_BITS-4){1'b1}}, ~rlen[3:0]})):
		(rburst[0]? (read_address[ADDRESS_BITS-1:0]+1):(read_address[ADDRESS_BITS-1:0]));
		@@ -164,7 +164,7 @@ module axibram_read #(

		if (rst) read_left <= 0;
		else if (start_read_burst_w) read_left <= arlen_out[3:0]; // precedence over inc
		else if (bram_reg_re_w) read_left <= read_left-1;
		else if (bram_reg_re_w) read_left <= read_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.

		if (rst) read_address <= {ADDRESS_BITS{1'b0}};
		else if (start_read_burst_w) read_address <= araddr_out[ADDRESS_BITS-1:0]; // precedence over inc
		@@ -178,7 +178,7 @@ module axibram_read #(
		else if (last_in_burst_d_w) rlast <= 1'b1;
		else if (rready) rlast <= 1'b0;
		end
		always @ (posedge aclk) begin
		always @ (posedge aclk) begin //SuppressThisWarning ISExst Assignment to bram_reg_re_0 ignored, since the identifier is never used
		// bram_reg_re_0 <= read_in_progress_w && !pre_rvalid_w;

		bram_reg_re_0 <= (ar_nempty && !read_in_progress) \|\| (read_in_progress && !read_in_progress);
		@@ -230,7 +230,7 @@ fifo_same_clock #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))
		.we(arvalid && arready),
		.re(start_read_burst_w),
		.data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),
		.data_out({arid_out[11:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[ADDRESS_BITS-1:0]}),
		.data_out({arid_out[11:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to arsize ignored, since the identifier is never used
		.nempty(ar_nempty),
		.full(),
		.half_full(ar_half_full)