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</projectDescription>

        .data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),

        .data_out({arid_out[11:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to arsize ignored, since the identifier is never used

        .nempty(ar_nempty),

        .full(),

        .half_full(ar_half_full)

    );

endmodule

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *******************************************************************************/

`define DEBUG_FIFO 1 

module  axibram_write #(

    parameter ADDRESS_BITS = 10 // number of memory address bits

)(

   output        bram_wen,    // external memory wreite enable, (internally combined with registered dev_ready

   output  [3:0] bram_wstb, 

   output [31:0] bram_wdata

`ifdef DEBUG_FIFO

    ,

        output    waddr_under,

        output    wdata_under,

        output    wresp_under, 

        output    waddr_over,

        output    wdata_over,

        output    wresp_over,

        output [3:0]   waddr_wcount, 

        output [3:0]   waddr_rcount, 

        output [3:0]   waddr_num_in_fifo, 

        output [3:0]   wdata_wcount, 

        output [3:0]   wdata_rcount, 

        output [3:0]   wdata_num_in_fifo, 

        output [3:0]   wresp_wcount, 

        output [3:0]   wresp_rcount, 

        output [3:0]   wresp_num_in_fifo,

        output [3:0]   wleft,

        output [3:0]   wlength,

        output reg [3:0] wlen_in_dbg  

`endif   

);

//    wire rst=~aresetn;

// **** Write channel: ****

    wire [11:0] wid_out;

    reg         write_in_progress=0;

    reg  [ADDRESS_BITS-1:0] write_address;       // transfer address (not including lower bits 

    reg  [ 3:0] write_left;          // number of read transfers

    reg  [ 3:0] write_left;          // number of write transfers

// will ignore arsize - assuming always 32 bits  (a*size[2:0]==2)

    reg  [ 1:0] wburst;             // registered burst type

    reg  [ 3:0] wlen;               // registered awlen type (for wrapped over transfers)

        (wburst[0]? (write_address[ADDRESS_BITS-1:0]+1):(write_address[ADDRESS_BITS-1:0]));

    assign      bram_we_w=         w_nempty_ready &&  write_in_progress;

//    assign      bram_we_nonmasked= w_nempty &&  write_in_progress;

//    assign start_write_burst_w=aw_nempty && (!write_in_progress || (w_nempty && (write_left[3:0]==4'b0)));

//    assign start_write_burst_w=aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));

    assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));

//    assign write_in_progress_w=aw_nempty || (write_in_progress && !(w_nempty && (write_left[3:0]==4'b0))); 

    assign write_in_progress_w=aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0))); 

//    assign write_in_progress_w=                  aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0))); 

    assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0))); 

    always @ (posedge  aclk or posedge  rst) begin

      if   (rst)                    wburst[1:0] <= 0;

   assign  bram_wstb   = wstb_out[3:0]; 

   assign  bram_wdata = wdata_out[31:0];

 `ifdef DEBUG_FIFO

    assign wleft=write_left;

    assign wlength[3:0]=wlen[3:0];

    always @ (posedge aclk) begin

        wlen_in_dbg <= awlen[3:0];

    end

 `endif  

fifo_same_clock   #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))

    waddr_i (

        .rst       (rst),

        .data_in   ({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),

        .data_out  ({awid_out[11:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[ADDRESS_BITS-1:0]}),  //SuppressThisWarning ISExst Assignment to awsize_out ignored, since the identifier is never used

        .nempty    (aw_nempty),

        .full(),

        .half_full (aw_half_full)

`ifdef DEBUG_FIFO

        ,

        .under      (waddr_under), // output reg 

        .over       (waddr_over), // output reg

        .wcount     (waddr_wcount), // output[3:0] reg 

        .rcount     (waddr_rcount), // output[3:0] reg 

        .num_in_fifo(waddr_num_in_fifo) // output[3:0] 

`endif         

    );

fifo_same_clock   #( .DATA_WIDTH(49),.DATA_DEPTH(4))    

    wdata_i (

        .data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),

        .data_out({wid_out[11:0],wlast_out,wstb_out[3:0],wdata_out[31:0]}), //SuppressThisWarning ISExst Assignment to wlast ignored, since the identifier is never used

        .nempty(w_nempty),

        .full(),

        .half_full(w_half_full)

`ifdef DEBUG_FIFO

        ,

        .under      (wdata_under), // output reg 

        .over       (wdata_over), // output reg

        .wcount     (wdata_wcount), // output[3:0] reg 

        .rcount     (wdata_rcount), // output[3:0] reg 

        .num_in_fifo(wdata_num_in_fifo) // output[3:0] 

`endif

    );

//debugging - slow down bresp

reg was_bresp_re=0;

wire bresp_re;

assign bresp_re=bready && bvalid && !was_bresp_re;

always @ (posedge rst or posedge aclk) begin

    if (rst) was_bresp_re<=0;

    else was_bresp_re <= bresp_re;

end

fifo_same_clock  #( .DATA_WIDTH(14),.DATA_DEPTH(4))    

    wresp_i (

        .rst(rst),

        .clk(aclk),

        .we(bram_we_w),

        .re(bready && bvalid),

//        .re(bready && bvalid),

        .re(bresp_re), // not allowing RE next cycle after bvalid

        .data_in({wid_out[11:0],bresp_in[1:0]}),

        .data_out({bid[11:0],bresp[1:0]}),

        .nempty(bvalid),

        .full(),

        .half_full()

`ifdef DEBUG_FIFO

        ,

        .under      (wresp_under), // output reg 

        .over       (wresp_over), // output reg

        .wcount     (wresp_wcount), // output[3:0] reg 

        .rcount     (wresp_rcount), // output[3:0] reg 

        .num_in_fifo(wresp_num_in_fifo) // output[3:0] 

`endif

    );

endmodule

 *******************************************************************************/

`timescale 1ns/1ps

`define use200Mhz 1

`define DEBUG_FIFO 1 

module  ddrc_test01 #(

    parameter PHASE_WIDTH =     8,

    parameter SLEW_DQ =         "SLOW",

// AXI write interface signals

//(* keep = "true" *)

   wire           axi_aclk;    // clock - should be buffered

//   wire           axi_naclk;   // debugging

//   wire           axi_aresetn; // reset, active low

//(* dont_touch = "true" *)

   wire           axi_rst;     // reset, active high

BUFG bufg_axi_rst_i   (.O(axi_rst),.I(axi_rst_pre));

BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));

//BUFG bufg_axi_naclk_i (.O(axi_naclk),.I(~fclk[0]));

always @ (posedge axi_aclk) begin

   port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle

end

`ifdef DEBUG_FIFO

        wire    waddr_under, wdata_under, wresp_under; 

        wire    waddr_over, wdata_over, wresp_over;

        reg     waddr_under_r, wdata_under_r, wresp_under_r;

        reg     waddr_over_r, wdata_over_r, wresp_over_r;

        wire    fifo_rst= frst[2];

        wire [3:0]   waddr_wcount; 

        wire [3:0]   waddr_rcount; 

        wire [3:0]   waddr_num_in_fifo; 

        wire [3:0]   wdata_wcount; 

        wire [3:0]   wdata_rcount; 

        wire [3:0]   wdata_num_in_fifo; 

        wire [3:0]   wresp_wcount; 

        wire [3:0]   wresp_rcount; 

        wire [3:0]   wresp_num_in_fifo; 

        wire [3:0]   wleft;

        wire [3:0]   wlength; // output[3:0] 

        wire [3:0]   wlen_in_dbg; // output[3:0] reg 

    always @(posedge fifo_rst or posedge axi_aclk) begin

     if (fifo_rst) {waddr_under_r, wdata_under_r, wresp_under_r,waddr_over_r, wdata_over_r, wresp_over_r} <= 0;

     else {waddr_under_r, wdata_under_r, wresp_under_r, waddr_over_r, wdata_over_r, wresp_over_r} <=

          {waddr_under_r, wdata_under_r, wresp_under_r, waddr_over_r, wdata_over_r, wresp_over_r} | 

          {waddr_under,   wdata_under,   wresp_under,   waddr_over,   wdata_over,   wresp_over};

    end         

`endif

/*

    dly_addr[1],

    dly_addr[0],

//MEMCLK

wire [63:0] gpio_in;

assign gpio_in={

frst[3]?{

16'b0,

    1'b1,              // 1

    MEMCLK,            // 1/0? - external clock

                       //    dly_addr[0],        0

                       //    clkin_stopped_mmcm, 0 

                       //    clkfb_stopped_mmcm, 0

    tmp_debug[3:0],     // 4'b1100 -> 4'bxx00

                       //    ddr_rst, 1 1 4000609c -> 0 , 40006098 -> 1

                       //    rst_in,  0 0

                       //    dci_rst, 0 1

                       //    dly_rst  0 1

    phy_locked_mmcm,   //  1 1

    phy_locked_pll,    //  1 1

    phy_dci_ready,     //  1 0

    locked_mmcm,       //  1 1

    locked_pll,        //  1 1

    dci_ready,         //  1 0

    dly_ready,         //  1 0

    dly_ready         //  1 0

    }:{

        waddr_wcount[3:0], 

        waddr_rcount[3:0], 

        waddr_num_in_fifo[3:0], 

        wdata_wcount[3:0], 

        wdata_rcount[3:0], 

        wdata_num_in_fifo[3:0], 

        wresp_wcount[3:0], 

        wresp_rcount[3:0], 

        wresp_num_in_fifo[3:0],

        wleft[3:0],

        wlength[3:0], 

        wlen_in_dbg[3:0] 

    },

    ps_out[7:4],       // 4'b0 input[7:0] 4'b0

    ps_out[3:0],       // 4'b0 input[7:0] 4'b0

    //ps_out[7:4],       // 4'b0 input[7:0] 4'b0

    //ps_out[3:0],       // 4'b0 input[7:0] 4'b0

    1'b0,

    waddr_under_r,

    wdata_under_r,

    wresp_under_r,

    1'b0, 

    waddr_over_r,

    wdata_over_r,

    wresp_over_r, // ???

    run_busy, // input // 0 

    locked, // input   // 1

    axi_arready,       // 1

    axi_awready,       // 1

    axi_wready,        // 1 

    fclk[0],           // 0/1 

    axi_wready,        // 1  - sometimes gets stuck with 0 (axi_awready==1) ? TODO: Add timeout 

    fifo_rst,   // fclk[0],          // 0/1 

    axi_rst_pre //axi_rst            // 0

};

        .bram_wen    (axiwr_bram_wen), // output

        .bram_wstb   (axiwr_bram_wstb[3:0]), // output[3:0] //SuppressThisWarning ISExst Assignment to axiwr_bram_wstb ignored, since the identifier is never used

        .bram_wdata  (axiwr_bram_wdata[31:0]) // output[31:0]

`ifdef DEBUG_FIFO

        ,

        .waddr_under (waddr_under), // output

        .wdata_under (wdata_under), // output

        .wresp_under (wresp_under), // output

        .waddr_over  (waddr_over),  // output

        .wdata_over  (wdata_over),  // output

        .wresp_over  (wresp_over),   // output

        .waddr_wcount(waddr_wcount), // output[3:0] 

        .waddr_rcount(waddr_rcount), // output[3:0] 

        .waddr_num_in_fifo(waddr_num_in_fifo), // output[3:0] 

        .wdata_wcount(wdata_wcount), // output[3:0] 

        .wdata_rcount(wdata_rcount), // output[3:0] 

        .wdata_num_in_fifo(wdata_num_in_fifo), // output[3:0] 

        .wresp_wcount(wresp_wcount), // output[3:0] 

        .wresp_rcount(wresp_rcount), // output[3:0] 

        .wresp_num_in_fifo(wresp_num_in_fifo), // output[3:0]

        .wleft       (wleft[3:0]),

        .wlength     (wlength[3:0]), // output[3:0] 

        .wlen_in_dbg (wlen_in_dbg[3:0]) // output[3:0] reg 

`endif         

    );

    /* Instance template for module axibram_read */

    .FPGAIDLEN(1'b1),             //Idle PL AXI interfaces (active low), input

// AXI PS Master GP0    

// AXI PS Master GP0: Clock, Reset

//    .MAXIGP0ACLK(axi_aclk),       // AXI PS Master GP0 Clock , input

    .MAXIGP0ACLK(fclk[0]),       // AXI PS Master GP0 Clock , input

    .MAXIGP0ACLK(axi_aclk),       // AXI PS Master GP0 Clock , input

//    .MAXIGP0ACLK(fclk[0]),       // AXI PS Master GP0 Clock , input

//      .MAXIGP0ACLK(~fclk[0]),       // AXI PS Master GP0 Clock , input

//      .MAXIGP0ACLK(axi_naclk),       // AXI PS Master GP0 Clock , input

    //

    .MAXIGP0ARESETN(),            // AXI PS Master GP0 Reset, output

// AXI PS Master GP0: Read Address