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Commit 5450474d authored by Andrey Filippov's avatar Andrey Filippov
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debugging hardware

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.project
View file @ 5450474d
......@@ -62,77 +62,77 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140607175804607.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140610171311514.log</location>
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<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140607175804607.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140610171311514.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140607175804607.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140610171311514.log</location>
</link>
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<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140607175804607.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140610171311514.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140607175804607.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140610171311514.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140607175804607.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140610171311514.log</location>
</link>
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<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140607173533434.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140610171153284.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140607175804607.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140610171311514.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140607173533434.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140610171311514.log</location>
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<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140607175804607.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140610171311514.log</location>
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<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140607173533434.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140610171311514.log</location>
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<name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140607175804607.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140610171311514.dcp</location>
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<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140607175804607.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140610171311514.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-route.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140607175804607.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140610171311514.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-synth.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140607173533434.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140610113942407.dcp</location>
</link>
</linkedResources>
</projectDescription>
axi/axibram_read.v
View file @ 5450474d
......@@ -232,7 +232,6 @@ fifo_same_clock #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))
.data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),
.data_out({arid_out[11:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to arsize ignored, since the identifier is never used
.nempty(ar_nempty),
.full(),
.half_full(ar_half_full)
);
endmodule
axi/axibram_write.v
View file @ 5450474d
......@@ -19,6 +19,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`define DEBUG_FIFO 1
module axibram_write #(
parameter ADDRESS_BITS = 10 // number of memory address bits
)(
......@@ -61,6 +62,33 @@ module axibram_write #(
output bram_wen, // external memory wreite enable, (internally combined with registered dev_ready
output [3:0] bram_wstb,
output [31:0] bram_wdata
`ifdef DEBUG_FIFO
,
output waddr_under,
output wdata_under,
output wresp_under,
output waddr_over,
output wdata_over,
output wresp_over,
output [3:0] waddr_wcount,
output [3:0] waddr_rcount,
output [3:0] waddr_num_in_fifo,
output [3:0] wdata_wcount,
output [3:0] wdata_rcount,
output [3:0] wdata_num_in_fifo,
output [3:0] wresp_wcount,
output [3:0] wresp_rcount,
output [3:0] wresp_num_in_fifo,
output [3:0] wleft,
output [3:0] wlength,
output reg [3:0] wlen_in_dbg
`endif
);
// wire rst=~aresetn;
// **** Write channel: ****
......@@ -84,7 +112,7 @@ module axibram_write #(
wire [11:0] wid_out;
reg write_in_progress=0;
reg [ADDRESS_BITS-1:0] write_address; // transfer address (not including lower bits
reg [ 3:0] write_left; // number of read transfers
reg [ 3:0] write_left; // number of write transfers
// will ignore arsize - assuming always 32 bits (a*size[2:0]==2)
reg [ 1:0] wburst; // registered burst type
reg [ 3:0] wlen; // registered awlen type (for wrapped over transfers)
......@@ -105,12 +133,9 @@ module axibram_write #(
(wburst[0]? (write_address[ADDRESS_BITS-1:0]+1):(write_address[ADDRESS_BITS-1:0]));
assign bram_we_w= w_nempty_ready && write_in_progress;
// assign bram_we_nonmasked= w_nempty && write_in_progress;
// assign start_write_burst_w=aw_nempty && (!write_in_progress || (w_nempty && (write_left[3:0]==4'b0)));
// assign start_write_burst_w=aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));
assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));
// assign write_in_progress_w=aw_nempty || (write_in_progress && !(w_nempty && (write_left[3:0]==4'b0)));
assign write_in_progress_w=aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0)));
// assign write_in_progress_w= aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0)));
assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0)));
always @ (posedge aclk or posedge rst) begin
if (rst) wburst[1:0] <= 0;
......@@ -161,17 +186,31 @@ module axibram_write #(
assign bram_wstb = wstb_out[3:0];
assign bram_wdata = wdata_out[31:0];
fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
`ifdef DEBUG_FIFO
assign wleft=write_left;
assign wlength[3:0]=wlen[3:0];
always @ (posedge aclk) begin
wlen_in_dbg <= awlen[3:0];
end
`endif
fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
waddr_i (
.rst(rst),
.clk(aclk),
.we(awvalid && awready),
.re(start_write_burst_w),
.data_in({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),
.data_out({awid_out[11:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to awsize_out ignored, since the identifier is never used
.nempty(aw_nempty),
.full(),
.half_full(aw_half_full)
.rst (rst),
.clk (aclk),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),
.data_out ({awid_out[11:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to awsize_out ignored, since the identifier is never used
.nempty (aw_nempty),
.half_full (aw_half_full)
`ifdef DEBUG_FIFO
,
.under (waddr_under), // output reg
.over (waddr_over), // output reg
.wcount (waddr_wcount), // output[3:0] reg
.rcount (waddr_rcount), // output[3:0] reg
.num_in_fifo(waddr_num_in_fifo) // output[3:0]
`endif
);
fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
wdata_i (
......@@ -182,20 +221,45 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),
.data_out({wid_out[11:0],wlast_out,wstb_out[3:0],wdata_out[31:0]}), //SuppressThisWarning ISExst Assignment to wlast ignored, since the identifier is never used
.nempty(w_nempty),
.full(),
.half_full(w_half_full)
`ifdef DEBUG_FIFO
,
.under (wdata_under), // output reg
.over (wdata_over), // output reg
.wcount (wdata_wcount), // output[3:0] reg
.rcount (wdata_rcount), // output[3:0] reg
.num_in_fifo(wdata_num_in_fifo) // output[3:0]
`endif
);
//debugging - slow down bresp
reg was_bresp_re=0;
wire bresp_re;
assign bresp_re=bready && bvalid && !was_bresp_re;
always @ (posedge rst or posedge aclk) begin
if (rst) was_bresp_re<=0;
else was_bresp_re <= bresp_re;
end
fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))
wresp_i (
.rst(rst),
.clk(aclk),
.we(bram_we_w),
.re(bready && bvalid),
// .re(bready && bvalid),
.re(bresp_re), // not allowing RE next cycle after bvalid
.data_in({wid_out[11:0],bresp_in[1:0]}),
.data_out({bid[11:0],bresp[1:0]}),
.nempty(bvalid),
.full(),
.half_full()
`ifdef DEBUG_FIFO
,
.under (wresp_under), // output reg
.over (wresp_over), // output reg
.wcount (wresp_wcount), // output[3:0] reg
.rcount (wresp_rcount), // output[3:0] reg
.num_in_fifo(wresp_num_in_fifo) // output[3:0]
`endif
);
endmodule
ddrc_test01.v
View file @ 5450474d
......@@ -20,6 +20,7 @@
*******************************************************************************/
`timescale 1ns/1ps
`define use200Mhz 1
`define DEBUG_FIFO 1
module ddrc_test01 #(
parameter PHASE_WIDTH = 8,
parameter SLEW_DQ = "SLOW",
......@@ -136,6 +137,7 @@ module ddrc_test01 #(
// AXI write interface signals
//(* keep = "true" *)
wire axi_aclk; // clock - should be buffered
// wire axi_naclk; // debugging
// wire axi_aresetn; // reset, active low
//(* dont_touch = "true" *)
wire axi_rst; // reset, active high
......@@ -312,8 +314,12 @@ module ddrc_test01 #(
else axi_rst_pre <= 1'b0;
end
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
//BUFG bufg_axi_naclk_i (.O(axi_naclk),.I(~fclk[0]));
always @ (posedge axi_aclk) begin
port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle
......@@ -326,6 +332,37 @@ always @ (posedge axi_rst or posedge axi_aclk) begin
else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
end
`ifdef DEBUG_FIFO
wire waddr_under, wdata_under, wresp_under;
wire waddr_over, wdata_over, wresp_over;
reg waddr_under_r, wdata_under_r, wresp_under_r;
reg waddr_over_r, wdata_over_r, wresp_over_r;
wire fifo_rst= frst[2];
wire [3:0] waddr_wcount;
wire [3:0] waddr_rcount;
wire [3:0] waddr_num_in_fifo;
wire [3:0] wdata_wcount;
wire [3:0] wdata_rcount;
wire [3:0] wdata_num_in_fifo;
wire [3:0] wresp_wcount;
wire [3:0] wresp_rcount;
wire [3:0] wresp_num_in_fifo;
wire [3:0] wleft;
wire [3:0] wlength; // output[3:0]
wire [3:0] wlen_in_dbg; // output[3:0] reg
always @(posedge fifo_rst or posedge axi_aclk) begin
if (fifo_rst) {waddr_under_r, wdata_under_r, wresp_under_r,waddr_over_r, wdata_over_r, wresp_over_r} <= 0;
else {waddr_under_r, wdata_under_r, wresp_under_r, waddr_over_r, wdata_over_r, wresp_over_r} <=
{waddr_under_r, wdata_under_r, wresp_under_r, waddr_over_r, wdata_over_r, wresp_over_r} |
{waddr_under, wdata_under, wresp_under, waddr_over, wdata_over, wresp_over};
end
`endif
/*
dly_addr[1],
......@@ -341,6 +378,7 @@ end
//MEMCLK
wire [63:0] gpio_in;
assign gpio_in={
frst[3]?{
16'b0,
1'b1, // 1
MEMCLK, // 1/0? - external clock
......@@ -360,13 +398,11 @@ assign gpio_in={
// dly_addr[0], 0
// clkin_stopped_mmcm, 0
// clkfb_stopped_mmcm, 0
tmp_debug[3:0], // 4'b1100 -> 4'bxx00
tmp_debug[3:0], // 4'b1100 -> 4'bxx00
// ddr_rst, 1 1 4000609c -> 0 , 40006098 -> 1
// rst_in, 0 0
// dci_rst, 0 1
// dly_rst 0 1
phy_locked_mmcm, // 1 1
phy_locked_pll, // 1 1
phy_dci_ready, // 1 0
......@@ -375,20 +411,47 @@ assign gpio_in={
locked_mmcm, // 1 1
locked_pll, // 1 1
dci_ready, // 1 0
dly_ready, // 1 0
dly_ready // 1 0
}:{
waddr_wcount[3:0],
waddr_rcount[3:0],
waddr_num_in_fifo[3:0],
wdata_wcount[3:0],
wdata_rcount[3:0],
wdata_num_in_fifo[3:0],
wresp_wcount[3:0],
wresp_rcount[3:0],
wresp_num_in_fifo[3:0],
wleft[3:0],
wlength[3:0],
wlen_in_dbg[3:0]
},
//ps_out[7:4], // 4'b0 input[7:0] 4'b0
ps_out[7:4], // 4'b0 input[7:0] 4'b0
//ps_out[3:0], // 4'b0 input[7:0] 4'b0
1'b0,
waddr_under_r,
wdata_under_r,
wresp_under_r,
ps_out[3:0], // 4'b0 input[7:0] 4'b0
1'b0,
waddr_over_r,
wdata_over_r,
wresp_over_r, // ???
run_busy, // input // 0
locked, // input // 1
ps_rdy, // input // 1
axi_arready, // 1
axi_awready, // 1
axi_wready, // 1
fclk[0], // 0/1
axi_awready, // 1
axi_wready, // 1 - sometimes gets stuck with 0 (axi_awready==1) ? TODO: Add timeout
fifo_rst, // fclk[0], // 0/1
axi_rst_pre //axi_rst // 0
};
......@@ -423,7 +486,29 @@ assign DUMMY_TO_KEEP = 1'b0; // dbg_toggle[0];
.bram_waddr (axiwr_bram_waddr[AXI_WR_ADDR_BITS-1:0]), // output[9:0]
.bram_wen (axiwr_bram_wen), // output
.bram_wstb (axiwr_bram_wstb[3:0]), // output[3:0] //SuppressThisWarning ISExst Assignment to axiwr_bram_wstb ignored, since the identifier is never used
.bram_wdata (axiwr_bram_wdata[31:0]) // output[31:0]
.bram_wdata (axiwr_bram_wdata[31:0]) // output[31:0]
`ifdef DEBUG_FIFO
,
.waddr_under (waddr_under), // output
.wdata_under (wdata_under), // output
.wresp_under (wresp_under), // output
.waddr_over (waddr_over), // output
.wdata_over (wdata_over), // output
.wresp_over (wresp_over), // output
.waddr_wcount(waddr_wcount), // output[3:0]
.waddr_rcount(waddr_rcount), // output[3:0]
.waddr_num_in_fifo(waddr_num_in_fifo), // output[3:0]
.wdata_wcount(wdata_wcount), // output[3:0]
.wdata_rcount(wdata_rcount), // output[3:0]
.wdata_num_in_fifo(wdata_num_in_fifo), // output[3:0]
.wresp_wcount(wresp_wcount), // output[3:0]
.wresp_rcount(wresp_rcount), // output[3:0]
.wresp_num_in_fifo(wresp_num_in_fifo), // output[3:0]
.wleft (wleft[3:0]),
.wlength (wlength[3:0]), // output[3:0]
.wlen_in_dbg (wlen_in_dbg[3:0]) // output[3:0] reg
`endif
);
/* Instance template for module axibram_read */
......@@ -976,8 +1061,10 @@ run_busy
.FPGAIDLEN(1'b1), //Idle PL AXI interfaces (active low), input
// AXI PS Master GP0
// AXI PS Master GP0: Clock, Reset
// .MAXIGP0ACLK(axi_aclk), // AXI PS Master GP0 Clock , input
.MAXIGP0ACLK(fclk[0]), // AXI PS Master GP0 Clock , input
.MAXIGP0ACLK(axi_aclk), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(fclk[0]), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(~fclk[0]), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(axi_naclk), // AXI PS Master GP0 Clock , input
//
.MAXIGP0ARESETN(), // AXI PS Master GP0 Reset, output
// AXI PS Master GP0: Read Address
......
ddrc_test01_testbench.sav
View file @ 5450474d
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ddrc_test01_testbench.tf
View file @ 5450474d
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python/exp_gpio.py
View file @ 5450474d
#!/usr/bin/env python
# -*- coding: utf-8 -*-
from __future__ import print_function
# Copyright (C) 2013, Elphel.inc.
# Export range of GPIO (EMIO)registers
# This program is free software: you can redistribute it and/or modify
......@@ -23,7 +24,6 @@ __maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
from __future__ import print_function
import sys
if len(sys.argv) < 3 or (sys.argv[1] != "in" and sys.argv[1] != "out") :
print ("Usage: ", sys.argv[0]+" <in|out> <gpio_number>[<gpio_max_number>]")
......
python/mon_gpio.py
View file @ 5450474d
#!/usr/bin/env python
# -*- coding: utf-8 -*-
from __future__ import print_function
# Copyright (C) 2013, Elphel.inc.
# Monitor a range of GPIO bits (should be exported first)
# This program is free software: you can redistribute it and/or modify
......@@ -22,7 +23,6 @@ __version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
from __future__ import print_function
import sys
if len(sys.argv) < 2 :
print ("Usage: ", sys.argv[0]+" <gpio_number>[<gpio_max_number>]")
......
util_modules/fifo_same_clock.v
View file @ 5450474d
......@@ -19,7 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`define DEBUG_FIFO 1
module fifo_same_clock
#(
parameter integer DATA_WIDTH=16,
......@@ -32,67 +32,80 @@ module fifo_same_clock
input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data
output [DATA_WIDTH-1:0] data_out, // output data
output reg nempty, // FIFO has some data
output reg full, // FIFO full
output nempty, // FIFO has some data
output reg half_full // FIFO half full
`ifdef DEBUG_FIFO
,output reg under, // debug outputs - under - attempt to read from empty
output reg over, // overwritten
output reg [DATA_DEPTH-1:0] wcount,
output reg [DATA_DEPTH-1:0] rcount,
output [DATA_DEPTH-1:0] num_in_fifo
`endif
);
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
//ISExst: FF/Latch ddrc_test01.axibram_write_i.waddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
//ISExst: FF/Latch ddrc_test01.axibram_read_i.raddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
//ISExst: FF/Latch ddrc_test01.axibram_write_i.wdata_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
// Do not understand - why?
reg [DATA_DEPTH :0] fill=0;
reg just_one,two_or_less;
reg [DATA_DEPTH-1:0] fill=0; // RAM fill
reg [DATA_WIDTH-1:0] inreg;
reg [DATA_WIDTH-1:0] outreg;
reg [DATA_DEPTH-1:0] ra;
reg [DATA_DEPTH-1:0] wa;
wire [DATA_DEPTH :0] next_fill;
wire outreg_use_inreg;
wire [DATA_DEPTH-1:0] next_fill;
reg wem;
wire rem;
reg out_full=0; //output register full
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
// assign next_fill = fill[4:0]+((we && ~re)?1:((~we && re)?5'b11111:5'b00000));
// assign data_out = just_one?inreg:outreg;
assign data_out = out_full?outreg:inreg;
assign rem = (!out_full || re)&& (just_one? wem : re);
assign outreg_use_inreg=(out_full && two_or_less) || just_one;
// assign next_fill = fill[4:0]+((we && ~rem)?1:((~we && rem)?5'b11111:5'b00000));
// TODO: verify rem is not needed instead of re
assign next_fill = fill[DATA_DEPTH:0]+((we && ~re)?1:((~we && re)?-1:0)); //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target.
reg ram_nempty;
assign next_fill = fill[DATA_DEPTH-1:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
assign rem= ram_nempty && (re || !out_full);
assign data_out=outreg;
assign nempty=out_full;
`ifdef DEBUG_FIFO
assign num_in_fifo=fill[DATA_DEPTH-1:0];
`endif
always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0;
else fill <= next_fill;
// else if (we && ~re) fill <= fill+1; //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target.
// else if (~we && re) fill <= fill-1; //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target.
if (rst) wem <= 0;
else wem <= we;
if (rst) ram_nempty <= 0;
else ram_nempty <= (next_fill != 0);
if (rst) wa <= 0;
else if (wem) wa <= wa+1; //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) ra <= 1; // 0;
else if (re) ra <= ra+1; //now ra is 1 ahead //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
else if (!nempty) ra <= wa+1; // Just recover from bit errors TODO: fix //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) nempty <= 0;
else nempty <= (next_fill != 0);
else if (wem) wa <= wa+1;
if (rst) ra <= 0;
else if (rem) ra <= ra+1;
else if (!ram_nempty) ra <= wa; // Just recover from bit errors
if (rst) out_full <= 0;
else if (rem && ~re) out_full <= 1;
else if (re && ~rem) out_full <= 0;
`ifdef DEBUG_FIFO
if (rst) wcount <= 0;
else if (we) wcount <= wcount + 1;
if (rst) rcount <= 0;
else if (re) rcount <= rcount + 1;
`endif
end
// no reset elements
always @ (posedge clk) begin
if (wem) ram[wa] <= inreg;
just_one <= (next_fill == 1);
two_or_less <= (next_fill == 1) | (next_fill == 2);
half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
full <= (fill & (1<< DATA_DEPTH ))!=0;
if (wem) ram[wa] <= inreg;
if (we) inreg <= data_in;
// if (rem) outreg <= just_one?inreg:ram[ra];
if (rem) outreg <= outreg_use_inreg ? inreg : ram[ra];
wem <= we;
if (rem) outreg <= ram[ra];
`ifdef DEBUG_FIFO
under <= ~we & re & ~nempty; // underrun error
over <= we & ~re & (fill == (1<< (DATA_DEPTH-1))); // overrun error
`endif
end
endmodule
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