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Commit c7b65d94 authored by Andrey Filippov's avatar Andrey Filippov
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.project
View file @ c7b65d94
......@@ -46,77 +46,77 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140515155524262.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140515155524262.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140515155524262.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140515155524262.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140515155524262.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140515155524262.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140515155524262.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140515155524262.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140515155524262.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140515155524262.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140515133627717.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140515155524262.log</location>
</link>
<link>
<name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140515133627717.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140515155524262.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-place.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140515133627717.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140515155524262.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-route.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140515133627717.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140515155524262.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-synth.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140515133627717.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140515155524262.dcp</location>
</link>
</linkedResources>
</projectDescription>
phy/byte_lane.v
View file @ c7b65d94
......@@ -122,32 +122,7 @@ generate
);
end
endgenerate
/*
dq_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.IOSTANDARD(IOSTANDARD_DQ),
.SLEW(SLEW_DQ),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dm_i(
.dq(dm), // DM output pad
.iclk(iclk), // source-synchronous clock (BUFR from DQS)
.clk(clk), // free-running system clock, same frequency as iclk (shared for R/W)
.clk_div(clk_div), // free-running half clk frequency, front aligned to clk (shared for R/W)
.inv_clk_div(inv_clk_div), // invert clk_div for R channel (clk_div is shared between R and W)
.rst(rst),
.dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
.dly_data(dly_data_r), // delay value (3 LSB - fine delay)
.din(din_dm_r[3:0]) , // parallel data to be sent out
.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
.dout(), // parallel data received from DDR3 memory
.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
.ld_odelay(ld_odly_dm), // clk_div synchronous set odealy value from loaded
.set_idelay(1'b0), // clk_div synchronous load idelay value from dly_data
.ld_idelay(1'b0) // clk_div synchronous set idealy value from loaded
);
*/
dm_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
......@@ -157,20 +132,15 @@ dm_single #(
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dm_i(
.dm(dm), // DM output pad
// .iclk(iclk), // source-synchronous clock (BUFR from DQS)
.clk(clk), // free-running system clock, same frequency as iclk (shared for R/W)
.clk_div(clk_div), // free-running half clk frequency, front aligned to clk (shared for R/W)
// .inv_clk_div(inv_clk_div), // invert clk_div for R channel (clk_div is shared between R and W)
.rst(rst),
.dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
.dly_data(dly_data_r), // delay value (3 LSB - fine delay)
.din(din_dm_r[3:0]) , // parallel data to be sent out
.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
// .dout(), // parallel data received from DDR3 memory
.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
.ld_odelay(ld_odly_dm) // clk_div synchronous set odealy value from loaded
// .set_idelay(1'b0), // clk_div synchronous load idelay value from dly_data
// .ld_idelay(1'b0) // clk_div synchronous set idealy value from loaded
);
dqs_single #(
......
phy/test_phy_top_01.v
View file @ c7b65d94
......@@ -68,7 +68,9 @@ module test_phy_top_01#(
input clk_in, // master input clock, initially assuming 100MHz
input rst_in, // reset delays/serdes\
input fake_din,
input fake_en
input fake_en,
input fake_oe,
output fake_dout
);
// SuppressWarnings VEditor
(* keep = "true" *) wire clk; // output
......@@ -105,8 +107,22 @@ module test_phy_top_01#(
reg [6:0] dly_addr; // select which delay to program
reg ld_delay; // load delay data to selected iodelayl (clk_iv synchronous)
reg set; // clk_div synchronous set all delays from previously loaded values
reg [63:0] dout_r;
reg locked_r;
reg [ 7:0] ps_out_r;
// Create fake data sources for all input
assign fake_dout= locked_r;
always @ (posedge mclk) begin
if (!fake_oe) begin
dout_r <= dout;
locked_r <=locked;
ps_out_r <=ps_out;
end else if (fake_en) begin
{locked_r,dout_r,ps_out_r} <= {dout_r,ps_out_r,1'b0};
end
if (fake_en)
{
in_a,
......
phy/test_phy_top_01.xdc
View file @ c7b65d94
......@@ -194,6 +194,14 @@ set_property PACKAGE_PIN T9 [get_ports {fake_din}]
set_property IOSTANDARD SSTL15 [get_ports {fake_en}]
set_property PACKAGE_PIN T10 [get_ports {fake_en}]
# input fake_oe,
set_property IOSTANDARD SSTL15 [get_ports {fake_oe}]
set_property PACKAGE_PIN V8 [get_ports {fake_oe}]
# output fake_dout
set_property IOSTANDARD SSTL15 [get_ports {fake_dout}]
set_property PACKAGE_PIN W8 [get_ports {fake_dout}]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
......
wrap/ram_1kx32_1kx32.v 0 → 100644
View file @ c7b65d94
/*******************************************************************************
* Copyright (c) 2014 Elphel, Inc.
* ram_1kx32_1kx32.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ram_1kx32_1kx32.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*******************************************************************************/
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
RAMB18E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[13:0] | D[0] | --- |
| 2 | A[13:1] | D[1:0] | --- |
| 4 | A[13:2] | D[3:0[ | --- |
| 9 | A[13:3] | D[7:0] | DP[0] |
| 18 | A[13:4] | D[15:0] | DP[1:0] |
+-----------+---------+---------+---------+
RAMB18E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 32/36 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 32/ 1 | A[13:0] | D[0] | --- |
| 32/ 2 | A[13:1] | D[1:0] | --- |
| 32/ 4 | A[13:2] | D[3:0[ | --- |
| 36/ 9 | A[13:3] | D[7:0] | DP[0] |
| 36/ 18 | A[13:4] | D[15:0] | DP[1:0] |
| 36/ 36 | A[13:5] | D[31:0] | DP[3:0] |
+------------+---------+---------+---------+
RAMB36E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[14:0] | D[0] | --- |
| 2 | A[14:1] | D[1:0] | --- |
| 4 | A[14:2] | D[3:0[ | --- |
| 9 | A[14:3] | D[7:0] | DP[0] |
| 18 | A[14:4] | D[15:0] | DP[1:0] |
| 36 | A[14:5] | D[31:0] | DP[3:0] |
|1(Cascade) | A[15:0] | D[0] | --- |
+-----------+---------+---------+---------+
RAMB36E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 64/72 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 64/ 1 | A[14:0] | D[0] | --- |
| 64/ 2 | A[14:1] | D[1:0] | --- |
| 64/ 4 | A[14:2] | D[3:0[ | --- |
| 64/ 9 | A[14:3] | D[7:0] | DP[0] |
| 64/ 18 | A[14:4] | D[15:0] | DP[1:0] |
| 64/ 36 | A[14:5] | D[31:0] | DP[3:0] |
| 64/ 72 | A[14:6] | D[63:0] | DP[7:0] |
+------------+---------+---------+---------+
*/
module ram_1kx32_1kx32
#(
parameter integer registers = 0 // 1 - registered output
)
(
input rclk, // clock for read port
input [ 9:0] raddr, // read address
input ren, // read port enable
input regen, // output register enable
output [31:0] data_out, // data out
input wclk, // clock for read port
input [ 9:0] waddr, // write address
input we, // write port enable
input [ 3:0] web, // write byte enable
input [31:0] data_in // data out
);
RAMB36E1
#(
.RSTREG_PRIORITY_A("RSTREG"), // Valid: "RSTREG" or "REGCE"
.RSTREG_PRIORITY_B("RSTREG"), // Valid: "RSTREG" or "REGCE"
.DOA_REG(registers), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 36)
.DOB_REG(registers), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 36)
.RAM_EXTENSION_A("NONE"), // Cascading, valid: "NONE","UPPER", LOWER"
.RAM_EXTENSION_B("NONE"), // Cascading, valid: "NONE","UPPER", LOWER"
.READ_WIDTH_A(36), // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
.READ_WIDTH_B(0), // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
.WRITE_WIDTH_A(0), // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
.WRITE_WIDTH_B(36), // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
.RAM_MODE("TDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
.WRITE_MODE_A("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.WRITE_MODE_B("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
.SIM_COLLISION_CHECK("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE("7SERIES"), // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
.EN_ECC_READ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry)
.EN_ECC_WRITE("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry)
// .INIT_A(36'h0), // Output latches initialization data
// .INIT_B(36'h0), // Output latches initialization data
// .SRVAL_A(36'h0), // Output latches initialization data (copied at when RSTRAM/RSTREG activated)
// .SRVAL_B(36'h0) // Output latches initialization data (copied at when RSTRAM/RSTREG activated)
/*
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
*/
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
.DOADO(data_out[31:0]), // Port A data/LSB data[31:0], output
.DOPADOP(), // Port A parity/LSB parity[3:0], output
.DIADI(32'h0), // Port A data/LSB data[31:0], input
.DIPADIP(4'h0), // Port A parity/LSB parity[3:0], input
.ADDRARDADDR({1'b1,raddr[9:0],5'b11111}), // Port A (read port in SDP) address [15:0]. used from [14] down, unused should be high, input
.CLKARDCLK(rclk), // Port A (read port in SDP) clock, input
.ENARDEN(ren), // Port A (read port in SDP) Enable, input
.REGCEAREGCE(regen), // Port A (read port in SDP) register enable, input
.RSTRAMARSTRAM(1'b0), // Port A (read port in SDP) set/reset, input
.RSTREGARSTREG(1'b0), // Port A (read port in SDP) register set/reset, input
.WEA(4'b0), // Port A (read port in SDP) Write Enable[3:0], input
// Port B
.DOBDO(), // Port B data/MSB data[31:0], output
.DOPBDOP(), // Port B parity/MSB parity[3:0], output
.DIBDI(data_in[31:0]), // Port B data/MSB data[31:0], input
.DIPBDIP(4'b0), // Port B parity/MSB parity[3:0], input
.ADDRBWRADDR({1'b1,waddr[9:0],5'b11111}), // Port B (write port in SDP) address [15:0]. used from [14] down, unused should be high, input
.CLKBWRCLK(wclk), // Port B (read port in SDP) clock, input
.ENBWREN(we), // Port B (read port in SDP) Enable, input
.REGCEB(1'b0), // Port B (read port in SDP) register enable, input
.RSTRAMB(1'b0), // Port B (read port in SDP) set/reset, input
.RSTREGB(1'b0), // Port B (read port in SDP) register set/reset, input
.WEBWE({4'b0,web[3:0]}), // Port B (read port in SDP) Write Enable[7:0], input
// Error correction circuitry
.SBITERR(), // Single bit error status, output
.DBITERR(), // Double bit error status, output
.ECCPARITY(), // Genearted error correction parity [7:0], output
.RDADDRECC(), // ECC read address[8:0], output
.INJECTSBITERR(1'b0),// inject a single-bit error, input
.INJECTDBITERR(1'b0),// inject a double-bit error, input
// Cascade signals to create 64Kx1
.CASCADEOUTA(), // A-port cascade, output
.CASCADEOUTB(), // B-port cascade, output
.CASCADEINA(1'b0), // A-port cascade, input
.CASCADEINB(1'b0) // B-port cascade, input
);
endmodule
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