Commit c676b5f2 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

working on ddr3 phy

parent a0c1b572

.editor_defines

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  // This file may be used to define same pre-processor macros to be included into each parsed file

  // It can be used to check different `ifdef branches

  `define XIL_TIMING //Simprim

.project

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@@ -43,25 +43,80 @@ 
		<nature>com.elphel.vdt.veditor.HdlNature</nature>

	</natures>

	<linkedResources>

		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140429103628186.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140429103628186.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140429103628186.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140515133627717.log</location>

		</link>

		<link>

			<name>vivado_state/eddr3-opt-phys.dcp</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140515133627717.dcp</location>

		</link>

		<link>

			<name>vivado_state/eddr3-place.dcp</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140515133627717.dcp</location>

		</link>

		<link>

			<name>vivado_state/eddr3-route.dcp</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140515133627717.dcp</location>

		</link>

		<link>

			<name>vivado_state/eddr3-synth.dcp</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140429103628186.dcp</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140515133627717.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

.settings/com.elphel.vdt.FPGA_project.prefs

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FPGA_project_2_ImplementationTopFile=phy/test_dqs07.v

FPGA_project_2_ImplementationTopFile=phy/test_phy_top_01.v

FPGA_project_4_part=xc7z030fbg484-2

com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->

eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoPlace.prefs

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VivadoPlace_111_verbose_place=true

com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->

eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoSynthesis.prefs

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VivadoSynthesis_102_ConstraintsFiles=phy/test_dqs07_placement.xdc<-@\#\#@->

VivadoSynthesis_102_ConstraintsFiles=phy/test_phy_top_01.xdc<-@\#\#@->

com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->

eclipse.preferences.version=1