moved files (c7b65d94) · Commits · Elphel / eddr3

.project

+15 −15

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		@@ -46,77 +46,77 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140515133627717.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140515155524262.log</location>
		</link>
		<link>
		<name>vivado_state/eddr3-opt-phys.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140515133627717.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140515155524262.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-place.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140515133627717.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140515155524262.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-route.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140515133627717.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140515155524262.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-synth.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140515133627717.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140515155524262.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

phy/byte_lane.v

+1 −31

Original line number	Diff line number	Diff line
		@@ -122,32 +122,7 @@ generate
		);
		end
		endgenerate
		/*
		dq_single #(
		.IODELAY_GRP(IODELAY_GRP),
		.IBUF_LOW_PWR(IBUF_LOW_PWR),
		.IOSTANDARD(IOSTANDARD_DQ),
		.SLEW(SLEW_DQ),
		.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
		.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
		) dm_i(
		.dq(dm), // DM output pad
		.iclk(iclk), // source-synchronous clock (BUFR from DQS)
		.clk(clk), // free-running system clock, same frequency as iclk (shared for R/W)
		.clk_div(clk_div), // free-running half clk frequency, front aligned to clk (shared for R/W)
		.inv_clk_div(inv_clk_div), // invert clk_div for R channel (clk_div is shared between R and W)
		.rst(rst),
		.dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
		.dly_data(dly_data_r), // delay value (3 LSB - fine delay)
		.din(din_dm_r[3:0]) , // parallel data to be sent out
		.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
		.dout(), // parallel data received from DDR3 memory
		.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
		.ld_odelay(ld_odly_dm), // clk_div synchronous set odealy value from loaded
		.set_idelay(1'b0), // clk_div synchronous load idelay value from dly_data
		.ld_idelay(1'b0) // clk_div synchronous set idealy value from loaded
		);
		*/

		dm_single #(
		.IODELAY_GRP(IODELAY_GRP),
		.IBUF_LOW_PWR(IBUF_LOW_PWR),
		@@ -157,20 +132,15 @@ dm_single #(
		.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
		) dm_i(
		.dm(dm), // DM output pad
		// .iclk(iclk), // source-synchronous clock (BUFR from DQS)
		.clk(clk), // free-running system clock, same frequency as iclk (shared for R/W)
		.clk_div(clk_div), // free-running half clk frequency, front aligned to clk (shared for R/W)
		// .inv_clk_div(inv_clk_div), // invert clk_div for R channel (clk_div is shared between R and W)
		.rst(rst),
		.dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
		.dly_data(dly_data_r), // delay value (3 LSB - fine delay)
		.din(din_dm_r[3:0]) , // parallel data to be sent out
		.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
		// .dout(), // parallel data received from DDR3 memory
		.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
		.ld_odelay(ld_odly_dm) // clk_div synchronous set odealy value from loaded
		// .set_idelay(1'b0), // clk_div synchronous load idelay value from dly_data
		// .ld_idelay(1'b0) // clk_div synchronous set idealy value from loaded
		);

		dqs_single #(

phy/test_phy_top_01.v

+17 −1

Original line number	Diff line number	Diff line
		@@ -68,7 +68,9 @@ module test_phy_top_01#(
		input clk_in, // master input clock, initially assuming 100MHz
		input rst_in, // reset delays/serdes\
		input fake_din,
		input fake_en
		input fake_en,
		input fake_oe,
		output fake_dout
		);
		// SuppressWarnings VEditor
		(* keep = "true" *) wire clk; // output
		@@ -105,8 +107,22 @@ module test_phy_top_01#(
		reg [6:0] dly_addr; // select which delay to program
		reg ld_delay; // load delay data to selected iodelayl (clk_iv synchronous)
		reg set; // clk_div synchronous set all delays from previously loaded values

		reg [63:0] dout_r;
		reg locked_r;
		reg [ 7:0] ps_out_r;

		// Create fake data sources for all input
		assign fake_dout= locked_r;
		always @ (posedge mclk) begin
		if (!fake_oe) begin
		dout_r <= dout;
		locked_r <=locked;
		ps_out_r <=ps_out;
		end else if (fake_en) begin
		{locked_r,dout_r,ps_out_r} <= {dout_r,ps_out_r,1'b0};
		end

		if (fake_en)
		{
		in_a,

phy/test_phy_top_01.xdc

+8 −0

Original line number	Diff line number	Diff line
		@@ -194,6 +194,14 @@ set_property PACKAGE_PIN T9 [get_ports {fake_din}]
		set_property IOSTANDARD SSTL15 [get_ports {fake_en}]
		set_property PACKAGE_PIN T10 [get_ports {fake_en}]

		# input fake_oe,
		set_property IOSTANDARD SSTL15 [get_ports {fake_oe}]
		set_property PACKAGE_PIN V8 [get_ports {fake_oe}]
		# output fake_dout
		set_property IOSTANDARD SSTL15 [get_ports {fake_dout}]
		set_property PACKAGE_PIN W8 [get_ports {fake_dout}]




		set_property INTERNAL_VREF 0.750 [get_iobanks 34]

phy/wrap/idelay_ctrl.v→wrap/idelay_ctrl.v

+0 −0

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