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Commit 01028931 authored by Andrey Filippov's avatar Andrey Filippov
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bug fixes, implemented read pattern test, so all major DDR3 modes are tested:... 

bug fixes, implemented read pattern test, so all major DDR3 modes are tested: write and read leveling, write and read
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.project
View file @ 01028931
...@@ -56,77 +56,77 @@ ...@@ -56,77 +56,77 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140531175841733.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140531223145240.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140531175841733.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140531223145240.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140531175841733.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140531223145240.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140531175841733.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140531223145240.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140531175841733.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140531223145240.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140531175841733.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140531223145240.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140531175605664.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140531222614445.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140531180006073.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140531223145240.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140531175605664.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140531222614445.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140531175841733.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140531223145240.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140531175605664.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140531222614445.log</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-opt-phys.dcp</name> <name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140531175841733.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140531223145240.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-place.dcp</name> <name>vivado_state/eddr3-place.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140531175841733.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140531223145240.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-route.dcp</name> <name>vivado_state/eddr3-route.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140531175841733.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140531223145240.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-synth.dcp</name> <name>vivado_state/eddr3-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140531175605664.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140531222614445.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
.settings/com.elphel.vdt.FPGA_project.prefs
View file @ 01028931
FPGA_project_0_SimulationTopFile=ddrc_test01_testbench.tf FPGA_project_0_SimulationTopFile=ddrc_test01_testbench.tf
FPGA_project_1_SimulationTopModule=ddrc_test01_testbench FPGA_project_1_SimulationTopModule=ddrc_test01_testbench
FPGA_project_2_ImplementationTopFile=ddrc_test01.v FPGA_project_2_ImplementationTopFile=ddrc_test01.v
FPGA_project_4_part=xc7z030fbg484-2 FPGA_project_4_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@-> com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
axi/axibram_read.v
View file @ 01028931
...@@ -121,6 +121,7 @@ module axibram_read #( ...@@ -121,6 +121,7 @@ module axibram_read #(
reg start_read_burst_1; reg start_read_burst_1;
reg [11:0] pre_rid0; reg [11:0] pre_rid0;
reg [11:0] pre_rid; reg [11:0] pre_rid;
// External memory interface - synchronization with ready // External memory interface - synchronization with ready
assign pre_araddr= araddr_out[ADDRESS_BITS-1:0]; assign pre_araddr= araddr_out[ADDRESS_BITS-1:0];
assign start_burst= start_read_burst_w; assign start_burst= start_read_burst_w;
...@@ -130,10 +131,9 @@ module axibram_read #( ...@@ -130,10 +131,9 @@ module axibram_read #(
assign bram_raddr = read_in_progress?read_address[ADDRESS_BITS-1:0]:{ADDRESS_BITS{1'b1}}; // read address assign bram_raddr = read_in_progress?read_address[ADDRESS_BITS-1:0]:{ADDRESS_BITS{1'b1}}; // read address
assign bram_ren = bram_reg_re_w; // read port enable assign bram_ren = bram_reg_re_w; // read port enable
assign bram_regen = bram_reg_re_w; // output register enable assign bram_regen = bram_reg_re_w; // output register enable
assign rdata[31:0] = bram_rdata; // data out assign rdata[31:0] = bram_rdata; // data out
always @ (posedge aclk or posedge rst) begin always @ (posedge aclk or posedge rst) begin
if (rst) pre_last_in_burst_r <= 0; if (rst) pre_last_in_burst_r <= 0;
......
ddrc_test01.v
View file @ 01028931
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
`timescale 1ns/1ps `timescale 1ns/1ps
`define use200Mhz 1
module ddrc_test01 #( module ddrc_test01 #(
parameter PHASE_WIDTH = 8, parameter PHASE_WIDTH = 8,
parameter SLEW_DQ = "SLOW", parameter SLEW_DQ = "SLOW",
...@@ -27,12 +27,21 @@ module ddrc_test01 #( ...@@ -27,12 +27,21 @@ module ddrc_test01 #(
parameter SLEW_CMDA = "SLOW", parameter SLEW_CMDA = "SLOW",
parameter SLEW_CLK = "SLOW", parameter SLEW_CLK = "SLOW",
parameter IBUF_LOW_PWR = "TRUE", parameter IBUF_LOW_PWR = "TRUE",
`ifdef use200Mhz
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else
parameter real REFCLK_FREQUENCY = 300.0, parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000, parameter SDCLK_PHASE = 0.000,
...@@ -233,27 +242,40 @@ module ddrc_test01 #( ...@@ -233,27 +242,40 @@ module ddrc_test01 #(
wire [ 3:0] dqs_tri_off_pattern; wire [ 3:0] dqs_tri_off_pattern;
wire [ 3:0] wbuf_delay; wire [ 3:0] wbuf_delay;
wire port0_rd_match;
reg port0_rd_match_r; // rd address matched in previous cycle
assign port0_rd_match=(((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
// assign en_cmd0_wr= axiwr_bram_wen && (axiwr_bram_waddr[11:10]==2'h1); // assign en_cmd0_wr= axiwr_bram_wen && (axiwr_bram_waddr[11:10]==2'h1);
// assign en_port0_rd= axird_bram_ren && (axird_bram_raddr[11:10]==2'h0); // assign en_port0_rd= axird_bram_ren && (axird_bram_raddr[11:10]==2'h0);
// assign en_port0_regen= axird_bram_regen && (axird_bram_raddr[11:10]==2'h0); // assign en_port0_regen= axird_bram_regen && (axird_bram_raddr[11:10]==2'h0);
// assign en_port1_wr= axiwr_bram_wen && (axiwr_bram_waddr[11:10]==2'h0); // assign en_port1_wr= axiwr_bram_wen && (axiwr_bram_waddr[11:10]==2'h0);
assign en_cmd0_wr= axiwr_bram_wen && (((axiwr_bram_waddr ^ CMD0_ADDR) & CMD0_ADDR_MASK)==0); assign en_cmd0_wr= axiwr_bram_wen && (((axiwr_bram_waddr ^ CMD0_ADDR) & CMD0_ADDR_MASK)==0);
assign en_port0_rd= axird_bram_ren && (((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
assign en_port0_regen= axird_bram_regen && (((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0); // assign en_port0_rd= axird_bram_ren && (((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
// assign en_port0_regen= axird_bram_regen && (((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
assign en_port0_rd= axird_bram_ren && port0_rd_match;
assign en_port0_regen= axird_bram_regen && port0_rd_match_r;
assign en_port1_wr= axiwr_bram_wen && (((axiwr_bram_waddr ^ PORT1_WR_ADDR) & PORT1_WR_ADDR_MASK)==0); assign en_port1_wr= axiwr_bram_wen && (((axiwr_bram_waddr ^ PORT1_WR_ADDR) & PORT1_WR_ADDR_MASK)==0);
assign axiwr_dev_ready = ~axiwr_dev_busy; //may combine (AND) multiple sources if needed assign axiwr_dev_ready = ~axiwr_dev_busy; //may combine (AND) multiple sources if needed
assign axird_bram_rdata= select_port0? port0_rdata[31:0]:(select_status?status_rdata[31:0]:32'bx); assign axird_bram_rdata= select_port0? port0_rdata[31:0]:(select_status?status_rdata[31:0]:32'bx);
assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed
always @ (posedge axi_aclk) begin
port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle
end
always @ (posedge axi_rst or posedge axi_aclk) begin always @ (posedge axi_rst or posedge axi_aclk) begin
if (axi_rst) select_port0 <= 1'b0; if (axi_rst) select_port0 <= 1'b0;
else if (axird_start_burst) select_port0 <= (((axird_pre_araddr^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0); else if (axird_start_burst) select_port0 <= (((axird_pre_araddr^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
if (axi_rst) select_status <= 1'b0; if (axi_rst) select_status <= 1'b0;
else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0); else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
end end
// Clock and reset from PS // Clock and reset from PS
......
ddrc_test01_testbench.sav
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ddrc_test01_testbench.tf
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ddrc_test01_timing.xdc
View file @ 01028931
...@@ -18,9 +18,8 @@ ...@@ -18,9 +18,8 @@
# You should have received a copy of the GNU General Public License # You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> . # along with this program. If not, see <http://www.gnu.org/licenses/> .
################################################################################# #################################################################################
#create_clock -period 2.500 -name clk -waveform {0.000 1.250} [get_ports CLK]
#axi_aclk [get_pins -hierarchical *pll*CLKIN1] create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
create_clock -name axi_aclk -period 10 [get_nets -hierarchical *axi_aclk]
#Clock Period Waveform Attributes Sources #Clock Period Waveform Attributes Sources
......
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