debugging error handling (d7e78d92) · Commits · Elphel / x393_sata

.project

+17 −17

Original line number	Diff line number	Diff line
		@@ -52,87 +52,87 @@
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ahci/ahci_dma.v

+39 −46

Original line number	Diff line number	Diff line
		@@ -345,11 +345,11 @@ module ahci_dma (

		if (cmd_start) dev_wr_mclk <= dev_wr;

		if (mrst) cmd_busy <= 0;
		if (mrst \|\| cmd_abort) cmd_busy <= 0;
		else if (cmd_start) cmd_busy <= 1;
		else if (cmd_done) cmd_busy <= 0;

		if (mrst) ct_busy <= 0;
		if (mrst \|\| cmd_abort) ct_busy <= 0;
		else if (cmd_start) ct_busy <= 1;
		else if (ct_done_mclk) ct_busy <= 0;

		@@ -380,11 +380,6 @@ module ahci_dma (
		always @ (posedge hclk) begin
		hrst_r <= hrst;

		// axi_dirty_r <= (\|afi_wacount) \|\| (\|afi_rcount); // afi_wacount of afi_rcount are non-zero (assuming afi_wcount should be zero as addresses are posted first

		// if (abort_or_reset && axi_dirty_r) abort_busy_hclk <= 1'b1;


		addr_data_rq_r <= addr_data_rq_w;

		prd_start_hclk_r <= prd_start_hclk;
		@@ -400,19 +395,19 @@ module ahci_dma (

		// overall sequencing makes sure that there will be no new requests until older served
		// additionally they are mutuially exclusive - only one may be pending at a time
		if (hrst) raddr_ct_pend <= 0;
		if (hrst \|\| cmd_abort_hclk) raddr_ct_pend <= 0;
		else if (raddr_ct_rq) raddr_ct_pend <= 1;
		else if (axi_set_raddr_ready) raddr_ct_pend <= 0;

		if (hrst) raddr_prd_pend <= 0;
		if (hrst \|\| cmd_abort_hclk) raddr_prd_pend <= 0;
		else if (raddr_prd_rq) raddr_prd_pend <= 1;
		else if (axi_set_raddr_ready) raddr_prd_pend <= 0;

		if (hrst) raddr_data_pend <= 0;
		if (hrst \|\| cmd_abort_hclk) raddr_data_pend <= 0;
		else if (raddr_data_rq) raddr_data_pend <= 1;
		else if (axi_set_raddr_ready) raddr_data_pend <= 0;

		if (hrst) waddr_data_pend <= 0;
		if (hrst \|\| cmd_abort_hclk) waddr_data_pend <= 0;
		else if (waddr_data_rq) waddr_data_pend <= 1;
		else if (axi_set_waddr_ready) waddr_data_pend <= 0;

		@@ -572,8 +567,8 @@ module ahci_dma (
		.WCNT_BITS (21),
		.ADDRESS_BITS (3)
		) ahci_dma_rd_fifo_i (
		.mrst (mrst), // input
		.hrst (hrst), // input
		.mrst (mrst \|\| abort_busy_mclk), // input
		.hrst (hrst \|\| cmd_abort_hclk), // input
		.mclk (mclk), // input
		.hclk (hclk), // input
		.wcnt (wcount[21:1]), // input[20:0]
		@@ -596,8 +591,8 @@ module ahci_dma (
		.WCNT_BITS (21),
		.ADDRESS_BITS (3)
		) ahci_dma_wr_fifo_i (
		.mrst (mrst), // input
		.hrst (hrst), // input
		.mrst (mrst \|\| abort_busy_mclk), // input
		.hrst (hrst \|\|cmd_abort_hclk), // input
		.mclk (mclk), // input
		.hclk (hclk), // input
		.wcnt (wcount[21:1]), // input[20:0]
		@@ -617,8 +612,6 @@ module ahci_dma (
		.din_rdy (sys_nfull), // output
		.din_avail (sys_we) // input
		);


		// mclk -> hclk cross-clock synchronization
		pulse_cross_clock #(
		.EXTRA_DLY(0)

ahci/ahci_fis_receive.v

+12 −15

Original line number	Diff line number	Diff line
		@@ -34,6 +34,7 @@ module ahci_fis_receive#(
		)(
		input hba_rst, // @posedge mclk - sync reset
		input mclk, // for command/status
		input pcmd_st_cleared, // ~= hba_rst?
		// Control Interface
		output reg fis_first_vld, // fis_first contains valid FIS header, reset by get_*
		// Debug features
		@@ -241,7 +242,7 @@ localparam DATA_TYPE_ERR = 3;
		assign fis_first_invalid = fis_first_invalid_r;

		always @ (posedge mclk) begin
		if (hba_rst \|\| dma_in_stop) dma_in <= 0;
		if (hba_rst \|\| dma_in_stop \|\| pcmd_st_cleared) dma_in <= 0;
		else if (dma_in_start) dma_in <= 1;

		if (hba_rst) was_data_in <= 0;
		@@ -254,7 +255,7 @@ localparam DATA_TYPE_ERR = 3;
		else if ((dma_in_valid && data_in_dwords_r[11]) \|\|
		(wreg_we_r && dwords_over)) too_long_err <= 1;

		if (hba_rst \|\| dma_in_start) fis_extra_r <= 0;
		if (hba_rst \|\| dma_in_start \|\| pcmd_st_cleared) fis_extra_r <= 0;
		else if (data_in_ready && (hba_data_in_type == DATA_TYPE_DMA) && dma_prds_done) fis_extra_r <= 1;


		@@ -294,13 +295,12 @@ localparam DATA_TYPE_ERR = 3;

		end

		if (hba_rst) fis_rec_run <= 0;
		if (hba_rst \|\| pcmd_st_cleared) fis_rec_run <= 0;
		else if (get_fis) fis_rec_run <= 1;
		else if (is_fis_end && data_in_ready) fis_rec_run <= 0;

		if (hba_rst \|\|get_fis) dwords_over <= 0;
		if (hba_rst \|\|get_fis \|\| pcmd_st_cleared) dwords_over <= 0;
		else if (wreg_we_r && !(\|fis_dcount)) dwords_over <= 1;
		/// else if (wreg_we_r && (!(\|fis_dcount) \|\| is_fis_end)) dwords_over <= 1;

		if (hba_rst) wreg_we_r <= 0;
		else wreg_we_r <= fis_rec_run && data_in_ready && !is_fis_end && !dwords_over && (\|fis_dcount \|\| !wreg_we_r) &&
		@@ -308,7 +308,7 @@ localparam DATA_TYPE_ERR = 3;

		fis_end_r <= {fis_end_r[0], fis_end_w};

		if (hba_rst) get_fis_busy_r[0] <= 0;
		if (hba_rst \|\| pcmd_st_cleared) get_fis_busy_r[0] <= 0;
		else if (get_fis) get_fis_busy_r[0] <= 1;
		else if (too_long_err \|\| fis_end_w) get_fis_busy_r[0] <= 0;

		@@ -316,9 +316,7 @@ localparam DATA_TYPE_ERR = 3;

		get_fis_done <= get_fis_busy_r[0] && (too_long_err \|\| fis_end_w);

		/// if (hba_rst \|\| get_fis) fis_first_vld <= 0;
		/// if (hba_rst \|\| fis_end_w) fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis
		if (hba_rst \|\| (\|get_fis_busy_r))fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis
		if (hba_rst \|\| (\|get_fis_busy_r) \|\| pcmd_st_cleared) fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis
		else if (is_FIS_HEAD) fis_first_vld <= 1;

		if (hba_rst \|\| get_fis) fis_ok <= 0;
		@@ -356,6 +354,7 @@ localparam DATA_TYPE_ERR = 3;
		else if (update_prdbc_r) reg_addr <= CLB_OFFS32 + 1; // location of PRDBC

		if (reg_d2h \|\| reg_sdb[0] \|\| reg_ds[0]) fis_i <= hba_data_in[14];

		if (reg_sdb) sdb_n <= hba_data_in[15];
		if (reg_ds[0]) {dma_a,dma_d} <= {hba_data_in[15],hba_data_in[13]};

		@@ -381,7 +380,6 @@ localparam DATA_TYPE_ERR = 3;
		xfer_cntr_zero_r <= xfer_cntr_r[31:2] == 0;

		update_err_sts_r <= update_pio \|\| update_err_sts \|\| clear_bsy_drq \|\| set_bsy \|\| set_sts_7f \|\| set_sts_80;
		// update_pio_r <= update_pio;
		update_prdbc_r <= update_prdbc; // same latency as update_err_sts
		update_sig_r <= update_sig && pUpdateSig_r; // do not update if not requested

		@@ -395,9 +393,8 @@ localparam DATA_TYPE_ERR = 3;
		else if (store_sig[3]) sig_available <= 1;

		// Maybe it is not needed if the fsm will send this pulse?
		// data_in_words_apply <= dma_in_stop && (hba_data_in_type == DATA_TYPE_OK);

		if (hba_rst \|\| (\|get_fis_busy_r)) fis_first_invalid_r <= 0;
		if (hba_rst \|\| (\|get_fis_busy_r) \|\|pcmd_st_cleared) fis_first_invalid_r <= 0;
		else fis_first_invalid_r <= is_FIS_NOT_HEAD;

		if (!fis_first_invalid_r) fis_first_flushing_r <= 0;

ahci/ahci_fis_transmit.v

+36 −54

Original line number	Diff line number	Diff line
		@@ -30,6 +30,7 @@ module ahci_fis_transmit #(
		)(
		input hba_rst, // @posedge mclk - when port is reset (even COMINIT)?
		input mclk, // for command/status
		input pcmd_st_cleared, // ~= hba_rst?
		// Command pulses to execute states
		input fetch_cmd, // Enter p:FetchCmd, fetch command header (from the register memory, prefetch command FIS)
		// wait for either fetch_cmd_busy == 0 or pCmdToIssue ==1 after fetch_cmd
		@@ -232,7 +233,7 @@ module ahci_fis_transmit #(
		always @ (posedge mclk) begin
		// Mutliplex between DMA and FIS output to the output routed to transmit FIFO
		// Count bypassing DMA dwords to generate FIS_last condition?
		if (hba_rst) todev_full_r <= 0;
		if (hba_rst \|\| pcmd_st_cleared) todev_full_r <= 0;
		else if (write_or_w) todev_full_r <= 1; // do not fill the buffer if FIFO is not ready
		else if (todev_ready) todev_full_r <= 0;

		@@ -240,16 +241,6 @@ module ahci_fis_transmit #(

		if (hba_rst) todev_type <= 3; // invalid? - no, now first and last word in command FIS (impossible?)
		else if (write_or_w) todev_type <= dma_en_r? {dx_dma_last_w , 1'b0} : fis_data_type;
		// else if (was_dma_ndav[1]) todev_type <= {1'b1, 1'b0}; // type = last in FIS

		// if (hba_rst) was_dma_ndav <= 0;
		// else was_dma_ndav <= {was_dma_ndav[1:0], ~dma_dav & todev_full_r & watch_prd_end_w} ;

		// if (hba_rst \|\| dma_dav \|\| !todev_full_r \|\| !watch_prd_end_w) was_dma_ndav <= 0;
		// else was_dma_ndav <= (was_dma_ndav << 1) \| 1;

		// if (hba_rst \|\| dx_xmit \|\| done_w) watch_prd_end <= 0;
		// else if (masked_last_h2d_data) watch_prd_end <= 1;
		// Read 3 DWORDs from the command header

		if (hba_rst) fetch_chead_r <= 0; // running 1
		@@ -291,22 +282,19 @@ module ahci_fis_transmit #(
		else if (chead_done_w) pCmdToIssue_r <= 1;
		else if (clearCmdToIssue) pCmdToIssue_r <= 0;

		if (hba_rst) fetch_cmd_busy_r <= 0;
		if (hba_rst \|\| pcmd_st_cleared) fetch_cmd_busy_r <= 0;
		else if (fetch_cmd) fetch_cmd_busy_r <= 1;
		else if (dma_start) fetch_cmd_busy_r <= 0;

		//CFIS/ATAPI common

		// if (hba_rst \|\| cfis_xmit) anc_fis_r <= 0;
		// else if (atapi_xmit) anc_fis_r <= 1;

		// fetch and send command/atapi FIS
		if (hba_rst \|\| acfis_xmit_start_w) acfis_xmit_pend_r <= 0;
		if (hba_rst \|\| acfis_xmit_start_w \|\| pcmd_st_cleared) acfis_xmit_pend_r <= 0;
		else if (cfis_xmit \|\| atapi_xmit) acfis_xmit_pend_r <= 1;

		acfis_xmit_start_r <= !hba_rst && acfis_xmit_start_w;

		if (hba_rst) acfis_xmit_busy_r <= 0;
		if (hba_rst \|\| pcmd_st_cleared) acfis_xmit_busy_r <= 0;
		else if (acfis_xmit_start_r) acfis_xmit_busy_r <= 1;
		else if (acfis_xmit_end) acfis_xmit_busy_r <= 0;

		@@ -332,8 +320,6 @@ module ahci_fis_transmit #(

		//TODO: update xfer length, prdtl (only after R_OK) - yes, do it outside

		// if (dx_xmit) xfer_cntr_is_set <= !xfer_cntr_zero; // if it was zero - rely on PRDs

		if (dx_xmit) dx_dwords_left[11:0] <= (xfer_cntr_zero \|\| (\|xfer_cntr[31:13])) ? 12'h800 : {1'b0,xfer_cntr[12:2]};
		else if (dma_re_w) dx_dwords_left[11:0] <= dx_dwords_left[11:0] - 1;

		@@ -341,10 +327,10 @@ module ahci_fis_transmit #(
		else if (dma_re_w) dwords_sent <= dwords_sent + 1;

		// send FIS header
		if (hba_rst \|\| write_or_w) dx_fis_pend_r <= 0;
		if (hba_rst \|\| write_or_w \|\|pcmd_st_cleared) dx_fis_pend_r <= 0;
		else if (dx_xmit) dx_fis_pend_r <= 1;

		if (hba_rst \|\| dx_dma_last_w \|\| (\|dx_err_r)) dma_en_r <= 0;
		if (hba_rst \|\| dx_dma_last_w \|\| (\|dx_err_r) \|\| pcmd_st_cleared) dma_en_r <= 0;
		else if (dx_fis_pend_r && write_or_w) dma_en_r <= 1;

		// Abort on transmit errors
		@@ -357,9 +343,7 @@ module ahci_fis_transmit #(
		if (hba_rst \|\| any_cmd_start) dx_err_r[2] <= 0;
		else if (xrdy_collision) dx_err_r[2] <= 1;

		if (hba_rst) dx_busy_r <= 0; // sending CFIS, AFIS or data FIS (until error or R_OK)
		// else if (dx_xmit) dx_busy_r <= 1;
		// else if (dx_dma_last_w \|\| (\|dx_err_r)) dx_busy_r <= 0;
		if (hba_rst \|\| pcmd_st_cleared) dx_busy_r <= 0; // sending CFIS, AFIS or data FIS (until error or R_OK)
		else if (dx_xmit \|\| acfis_xmit_start_r) dx_busy_r <= 1;
		else if (xmit_ok \|\| (\|dx_err_r)) dx_busy_r <= 0;

		@@ -369,15 +353,13 @@ module ahci_fis_transmit #(
		if (hba_rst) done <= 0;
		else done <= done_w;

		if (hba_rst) busy <= 0;
		if (hba_rst \|\| pcmd_st_cleared) busy <= 0;
		else if (any_cmd_start) busy <= 1;
		else if (done_w) busy <= 0;

		if (hba_rst) xmit_ok_r <= 0;
		else xmit_ok_r <= dx_busy_r && !(\|dx_err_r) && xmit_ok;



		dma_cmd_abort <= done_w && (\|dx_err_r);

		if (cfis_xmit) dbg_was_ct_re_r <= {ct_re_r, ct_re_w};

ahci/ahci_sata_layers.v

+10 −5

Original line number	Diff line number	Diff line
		@@ -138,6 +138,9 @@ module ahci_sata_layers #(
		wire ll_incom_start; // link -> // if started an incoming transaction assuming this and next 2 are single-cycle
		wire ll_incom_done; // link -> // if incoming transition was completed
		wire ll_incom_invalidate; // link -> // if incoming transition had errors
		reg ll_incom_invalidate_r; // error delayed by 1 clock - if eof was incorrect (because of earlier data error)
		// let last data dword to pass through

		// wire incom_ack_good = send_R_OK; // -> link // transport layer responds on a completion of a FIS
		// wire incom_ack_bad = send_R_ERR; // -> link // oob sequence is reinitiated and link now is not established or rxelecidle

		@@ -177,6 +180,7 @@ module ahci_sata_layers #(
		wire rxelsfull;
		wire rxelsempty;


		wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer


		@@ -262,7 +266,7 @@ module ahci_sata_layers #(
		.link_reset (ll_link_reset), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle
		.sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction
		.sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception?
		.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current recieving session
		.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current receiving session
		.link_established (link_established),
		// inputs from phy
		.phy_ready (phy_ready), // input wire // phy is ready - link is established
		@@ -277,14 +281,15 @@ module ahci_sata_layers #(
		);

		always @ (posedge clk) begin
		ll_incom_invalidate_r <= ll_incom_invalidate;
		// FIS receive D2H
		// add head if ll_d2h_valid and (d2h_type_in == D2H_TYPE_OK) \|\| (d2h_type_in == D2H_TYPE_ERR)? Or signal some internal error
		if (rst \|\| ll_incom_start) d2h_type_in <= D2H_TYPE_FIS_HEAD; // FIS head
		else if (ll_d2h_valid) d2h_type_in <= D2H_TYPE_DMA; // FIS BODY
		else if (ll_incom_done \|\| ll_incom_invalidate) d2h_type_in <= ll_incom_invalidate ? D2H_TYPE_ERR: D2H_TYPE_OK;
		else if (ll_incom_done \|\| ll_incom_invalidate_r) d2h_type_in <= ll_incom_invalidate_r ? D2H_TYPE_ERR: D2H_TYPE_OK;

		if (rst) fis_over_r <= 0;
		else fis_over_r <= (ll_incom_done \|\| ll_incom_invalidate) && (d2h_type_in == D2H_TYPE_DMA); // make sure it is only once
		else fis_over_r <= (ll_incom_done \|\| ll_incom_invalidate_r) && (d2h_type_in == D2H_TYPE_DMA); // make sure it is only once
		// Second - generate internal error?

		// FIS transmit H2D
		@@ -342,7 +347,7 @@ module ahci_sata_layers #(
		.WIDTH(9)
		) fifo_h2d_control_i (
		.clk (clk), // input
		.rst (rst), // input
		.rst (rst \|\| pcmd_st_cleared), // input
		.wr (h2d_fifo_wr), // input
		.rd (h2d_fifo_rd), // input
		.nempty (h2d_nempty), // output
		@@ -376,7 +381,7 @@ module ahci_sata_layers #(
		.WIDTH(9)
		) fifo_d2h_control_i (
		.clk (clk), // input
		.rst (rst), // input
		.rst (rst \|\| pcmd_st_cleared), // input
		.wr (d2h_fifo_wr), // input
		.rd (d2h_fifo_rd), // input
		.nempty (d2h_nempty), // output

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